libretro/mame2003-plus-libretro
1
0 Fork 0
mirror of https://github.com/libretro/mame2003-plus-libretro.git synced 2026-11-07 12:28:04 -10:00
Code Issues Packages Projects Releases 1 Wiki Activity

Compare commits

base: libretro/mame2003-plus-libretro:cpu-clock-scale-setting-change
libretro/mame2003-plus-libretro:master libretro/mame2003-plus-libretro:arcadez2003-patch-11 libretro/mame2003-plus-libretro:arcadez2003-patch-10 libretro/mame2003-plus-libretro:arcadez2003-patch-9 libretro/mame2003-plus-libretro:arcadez2003-patch-8 libretro/mame2003-plus-libretro:markwkidd-patch-1 libretro/mame2003-plus-libretro:arcadez2003-patch-7 libretro/mame2003-plus-libretro:arcadez2003-patch-6 libretro/mame2003-plus-libretro:arcadez2003-patch-5 libretro/mame2003-plus-libretro:arcadez2003-patch-4 libretro/mame2003-plus-libretro:cpu-clock-scale-setting-change libretro/mame2003-plus-libretro:arcadez2003-patch-3 libretro/mame2003-plus-libretro:arcadez2003-patch-2 libretro/mame2003-plus-libretro:arcadez2003-patch-1 libretro/mame2003-plus-libretro:Call2
libretro/mame2003-plus-libretro:Current
...
compare: libretro/mame2003-plus-libretro:master
libretro/mame2003-plus-libretro:master libretro/mame2003-plus-libretro:arcadez2003-patch-11 libretro/mame2003-plus-libretro:arcadez2003-patch-10 libretro/mame2003-plus-libretro:arcadez2003-patch-9 libretro/mame2003-plus-libretro:arcadez2003-patch-8 libretro/mame2003-plus-libretro:markwkidd-patch-1 libretro/mame2003-plus-libretro:arcadez2003-patch-7 libretro/mame2003-plus-libretro:arcadez2003-patch-6 libretro/mame2003-plus-libretro:arcadez2003-patch-5 libretro/mame2003-plus-libretro:arcadez2003-patch-4 libretro/mame2003-plus-libretro:cpu-clock-scale-setting-change libretro/mame2003-plus-libretro:arcadez2003-patch-3 libretro/mame2003-plus-libretro:arcadez2003-patch-2 libretro/mame2003-plus-libretro:arcadez2003-patch-1 libretro/mame2003-plus-libretro:Call2
libretro/mame2003-plus-libretro:Current
135 Commits
cpu-clock-scale-setting-change ... master
Author SHA1 Message Date
mahoneyt944 dff0ba6365 segas32 use opaque blending by default - dbzvrvs backgrounds working. (#2211) 
* Update segas32.c

* Update segas32.c

* Update .gitlab-ci.yml

* Update segas32.c

* Update segas32.h

* Update segas32.c

* Update segas32.c

* Update .gitlab-ci.yml
 2026-11-07 07:35:08 -05:00
arcadez2003 1035485897 Merge pull request #2210 from libretro/arcadez2003-patch-11 
3on3dunk
 2026-11-06 21:07:03 +00:00
arcadez2003 a0e0e75905 Merge pull request #2209 from libretro/arcadez2003-patch-10 
3on3 Dunk Madness video code
 2026-11-06 21:06:47 +00:00
arcadez2003 a45b70e19e Merge pull request #2208 from libretro/arcadez2003-patch-9 
Attempt to support 3on3 Dunk Madness
 2026-11-06 21:06:32 +00:00
arcadez2003 ea291bf560 3on3dunk 2026-11-06 21:02:07 +00:00
arcadez2003 0dd483f4c0 3on3 Dunk Madness video code 2026-11-06 20:59:50 +00:00
arcadez2003 7f35678403 Attempt to support 3on3 Dunk Madness 
Ported from AdvanceMAME
 2026-11-06 20:58:34 +00:00
zanacandClaude Opus 5.5 888122871c namcos22: Time Crisis light gun as MAME, with crosshair (#2207) 
- the gun ports use MAME's position ranges (X 68-694, Y 43-284), what
  the game reads, instead of 8-bit values scaled in the handler;
- the screen edges read as off screen, as MAME: before, an off-screen
  position (1 or 254) reached the game as a shot at the edge;
- the crosshair (core option) is drawn where the game sees the shot,
  as MAME's PORT_CROSSHAIR(X/Y, 1.0, 0.0, 0).


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-11-06 03:33:05 -05:00
arcadez2003 d41198a39d Mention Akka Arrh can now be played using this core 2026-11-05 21:56:10 +00:00
zanacandClaude Opus 5.5 34988bc120 Namco System 22 / Super System 22 from current MAME (#2206) 
Replaces the old namcos22 driver (no DSPs, every game not working) with a
C89 backport of the current MAME driver:

- new Namco C71 core (TMS320C25 with internal ROM) for the master and
  slave DSPs: MAME's tms320c2x instructions, a page table memory system;
- Super System 22 (68EC020, M37710 MCU with C352 and MB87078 volume) and
  System 22 (68020, C74 MCU with internal BIOS);
- the video: display list simulation, z-sorted polygons and sprites,
  text layer, fog, fades, alpha, spot RAM, gamma; MAME's rasterizer
  rules, single threaded, with 1/z every 8 pixels and fast paths;
- the "Threaded Video" option (was "ST-V Threaded Video") draws the
  frame in bands on 2 to 4 threads (3D scene, text layer, mix, gamma),
  same picture;
- M37710: timer A event counters count up or down (output pin or up/down
  register, as MAME), for the Prop Cycle pedal and the Armadillo Racing
  trackball;
- C352: optional routing of the four outputs to the stereo stream (rear
  speakers, cabinet speakers), as current MAME maps them to stereo; off
  unless a driver asks for it, System 11/12 unchanged;
- game I/O as MAME: driving games and Cyber Commando on System 22,
  Alpine Racer steplock motor, Alpine Surfer ROM banking, Armadillo
  Racing trackball, default EEPROMs.

System 22 sets (namcoc74 BIOS): ridgerac, ridgeraca, ridgeracb,
ridgeracc, ridgeracj, ridgera2, ridgera2j, ridgera2ja, ridgera28,
cybrcomm, raverace, raveracej, raveraceja, acedrive, victlap, victlapa,
victlapj.

Super System 22 sets: alpinerd, alpinerc, alpinerjc, airco22b, cybrcycc,
cybrcyccj, dirtdash, dirtdasha, dirtdashb, dirtdashj, timecris,
timecrisa, timecrisj, propcycl, propcyclj, alpines, tokyowar, tokyowarj,
aquajet, alpinr2b, alpinr2a, adillor, adillorj.


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-11-05 13:08:58 -05:00
zanacandClaude Opus 5.5 af0f783b1e Cyclone mode: DrZ80(snd) also takes the unflagged sound Z80; default list cleanup (#2157) (#2205) 
DrZ80(snd) and Cyclone+DrZ80(snd) only replaced the Z80s flagged
CPU_AUDIO_CPU, and many sound Z80s are not flagged (CPS2, Taito,
Toaplan, the Mega Drive based boards...): those games kept the C Z80
with no sign in the log.

Now, on a board with no flagged CPU whose first CPU is not a Z80, its
first Z80 is taken as the sound CPU too, except where DrZ80 can't run
it: a Z80 with a daisy chain (DrZ80 has none), the CPS1 QSound Z80
(Kabuki-encrypted opcodes) and the Tatsumi sound Z80 (Round Up 5
hangs). The log says which Z80s are replaced and which are kept.

frontend_list.h: removed the entries that could do nothing, with the
same result for every game: 82 names not in the core, 531 games with
neither a 68000 nor a Z80, and a second zzyzzyx2 entry never reached.


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-11-05 03:36:34 -05:00
arcadez2003 b8afd2ddde Sigh this time surely 2026-11-04 22:48:46 +00:00
arcadez2003 00e1f93fc6 Fix build 2026-11-04 22:42:20 +00:00
arcadez2003 ae8299f57c Rename akkaarrh to akkaarrh.c 2026-11-04 22:32:18 +00:00
arcadez2003 11b6dd20a8 FFS try that again 2026-11-04 22:14:36 +00:00
arcadez2003 b6b9bae087 akkaarrh 2026-11-04 20:51:10 +00:00
arcadez2003 9f568e318b Declare akkaarrh 2026-11-04 20:46:46 +00:00
arcadez2003 5a0269a6fd New Driver Atari's Akka Arrh prototype 
With thanks to AdvanceMAME
 2026-11-04 20:44:15 +00:00
zanacandClaude Opus 5.5 91f2f15e15 ST-V: Cotton Boomerang English translation (cottonbme) (#2204) 
Bootleg clone set of cottonbm in English: the stage result lines, the
character select panels, the full names of the characters in the
attract mode, and the translation credit under the title logo. The game always
runs in its Japanese (translated) mode, so the whole translation shows
with every BIOS region. The four changed chips are built from cottonbm
with github.com/zanac/cottonbm, which writes a complete cottonbme.zip.


Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX

Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-11-04 01:38:45 -05:00
zanacandClaude Opus 5.5 b974d670cc Golden Axe: the FD1094 sets goldnaxb, goldnaxc and goldnaxj working (#2203) 
goldnaxb (317-0110), goldnaxc (317-0122) and goldnaxj (317-0121) are the
Golden Axe sets with the FD1094 encrypted 68000 (MAME goldnaxe1,
goldnaxeu, goldnaxej). They were marked not working.

- The decryption keys are added to the sets and the code is decrypted
  with the FD1094 module already used by Cotton (C 68000 core).
- They get their own memory maps: the ones of goldnaxa (171-5797 board)
  and goldnaxe (171-5704 board) without the handlers that stand in for
  the 8751 in the work RAM; these sets have no 8751, they read the I/O
  and send the sound commands themselves.
- The 315-5195 memory mapper, as far as these games use it: register 3 is
  the sound command, and every frame the program moves the sprite RAM to
  one of 8 bases (0x200000-0x900000), so the sprite RAM follows the base
  in register 0x19. The mapper registers are in the save states.


Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX

Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-11-03 20:16:15 -05:00
zanacandClaude Opus 5.5 ab52620ee4 ST-V and Model 2: save states, run-ahead and netplay; SCSP slot allocation (#2202) 
Save states on ST-V were broken on master: a loaded state, a run-ahead
rewind or a netplay resync did not continue the emulation the same way.
Model 2 was almost right (hpyagu98 differed after a rewind).

Core:
- SH-2: each CPU registers its own state (both used to register the
  boot buffer), and the rest of the CPU is saved: delay slot, divider,
  interrupt queue and lines, on-chip registers, FRT, DMA timers.
- Memory banks are registered after the driver init, where the drivers
  point them (ST-V work RAM was saved from the wrong buffer).
- cpu_spinuntil_time / cpu_yielduntil_time trigger counters are saved.
- The crosshair idle timer is saved (the crosshair hid at another frame
  after a load or a rewind).

ST-V:
- SMPC, SCU registers and interrupts, SCU DSP, I/O, sound CPU control,
  CD block scalars, VDP1 clipping, CRTC line counter are saved.
- The RTC starts from the host date and time at boot and then follows the
  emulated time (it read the host clock at every query, so two runs from
  the same state could read different times).

SH-2 recompiler: the polling loop skip counted a whole chain of blocks
that came back to the loop start as one loop iteration, skipping the
writes and calls in between. It now only skips when the block ran one
turn of the loop. Results with a warm or a cold block cache are now the
same.

Model 2: the polygon count of the last display list is saved.

SCSP (issue #2194, regression of #2198): a key off on a slot that had
already stopped (a one-shot sample past its end) left its envelope at the
level it stopped at, because a stopped slot no longer updates it. The
monitor register (0x408) then showed the slot as still sounding, the
sound drivers took it for busy and, after a while, put every new note on
the one slot left. Cotton Boomerang lost all but the drums at the first
boss, Winter Heat's voices cut each other from the first attract demo on.
Such a slot now ends its release at once.


Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX

Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-11-03 12:04:40 -05:00
zanacandClaude Opus 5.5 7ed1af5370 Model 2: faster 3D, 2D layers, SCSP DSP, i960 and SHARC (#2201) 
Renderer:
- texture sheets also kept one byte per texel, the texel fetch reads them
  straight (inlined, an opaque and a translucent span)
- the pixel of each texel worked out once for the colours of a polygon
- translucent texel pairs packed from a table; a translucent pixel sure to
  be discarded skips the next mipmap level
- 3D pixels kept as the 15-bit colour of the bitmap
- the tile layers drawn straight into the bitmap: the polygons are only
  drawn over the tile pixels behind them, no copy passes

System 24 tiles (rgb version, Model 1 and 2): eight pixels at a time, a
group all of the layer's priority without a test each, the last pixels of
the line as groups too.

SCSP DSP: the steps that only multiply and accumulate on a short path,
decoded when MPRO changes; the delay RAM float packing from a table.

i960: opcodes read straight from the memory block of the last fetch
(memory_get_read_range), execute_op inlined.

SHARC: no DMA call while channels 6 and 7 are idle.

AArch64 (QEMU, instructions per frame): fvipers -26%, doa -28%, daytona
-31%, vf2 -25%. Frames and audio are the same on the Model 2 sets, the
ST-V sets and in save states.


Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX

Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-11-03 02:19:01 -05:00
arcadez2003 35fee378f5 Merge pull request #2200 from zanac/stv-perf 
ST-V: faster VDP2 and VDP1 drawing, SH-2 polling loops skipped, FTCSR as in MAME
 2026-11-02 23:27:07 +00:00
VanniandClaude Opus 5.5 40dab5fe44 ST-V: faster VDP2 and VDP1 drawing, SH-2 polling loops skipped, FTCSR as in MAME 
VDP2 tiles:
- vdp2_drawgfx_alpha drew every pixel through vdp2_window_process; with a
  window it now draws the runs of each line the windows show, from the line
  cache of vdp2_drawgfx_transpen (same pixels), and with no window it
  copies without checks. Both work out the window key once per tile and
  check the cached line inline.
- Each decoded element keeps two masks of its rows (a pixel other than
  pen 0; no pen 0). With transparency vdp2_drawgfx_transpen skips tiles
  and rows of pen 0 only and copies whole the rows without it.

VDP1 sprites: without color calculation draw_sprites walks the window runs
of the line instead of calling vdp2_window_process for every pixel.

SH-2:
- Only a read that includes FRC resyncs it (MAME frc_r); TIER and FTCSR
  reads (MAME ftcsr_r) do not.
- The recompiler skips the iterations of polling loops that only read, as
  it already did for the SGL idle loop: a block that starts with a short
  loop back to itself which leaves every register as it found it and read
  only RAM or TIER/FTCSR repeats the same iteration until the end of the
  timeslice, so those iterations are counted at once.

Makefile (unix): -fvisibility=hidden, only retro_* leaves the library.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX
 2026-11-02 22:34:25 +01:00
arcadez2003 cc4bfcdf71 Merge pull request #2198 from zanac/stv-sound-2194 
SCSP sound for ST-V and Model 2: voices, timers and interrupts from current MAME, Batman Forever RAX board
 2026-11-02 19:30:41 +00:00
VanniandClaude Opus 5.5 93b073496c ST-V sound: SCSP voices from current MAME, Batman Forever RAX board 
SCSP (also used by Model 2):
- The slot engine from current MAME: key off goes to the release, the
  envelope tables and the dB curve of the decay, pitch, interpolation,
  the four loop modes, FM from the ring buffer, noise (SSCTL), SBCTL,
  LPSLNK, STWINH/SDIR; 8-bit samples read in big-endian byte order.
- The monitor register 0x408 returns CA, SGC and EG of the slot set in
  MSLC: the sound drivers look there for a free slot, and Winter Heat
  played every voice on slot 0, each one cutting the previous.
- Real timers for timers A, B and C, as in MAME: counting them with the
  generated samples delayed every interrupt until the next stream update.
- Interrupts as in MAME: each source raises its own level until it is
  acknowledged in SCIRE, and an acknowledged expired timer is pending
  again with no new interrupt. Reading MIBUF drops the MIDI interrupt:
  left raised, the sound CPU took it again on an empty FIFO and read
  stale bytes as MIDI data, which broke music commands in Model 2
  (Fighting Vipers, Dead or Alive, Manx TT).
- The DMA used the common registers 0x412 words past them, inside the
  slots: now as in MAME.
- The common registers are 0x400-0x42f only (0x500 is not a mirror),
  the ring buffer at 0x600 can be read and written, the LFO saw wave and
  rate as in MAME.
- ST-V: a 16-bit access of the SH-2 touches only its half of the SCSP
  registers.

Batman Forever: the Acclaim RAX sound board (ADSP-2181), moved from zn.c
to sndhrdw/acclaim_rax.c and shared by NBA Jam Extreme and Batman
Forever, which writes its commands to 0x04800000 as in MAME.

docs/sega-model2.md: the MIDI interrupt of the sound link.

Fixes #2194.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX
 2026-11-02 18:47:50 +01:00
GoodLuckTrying (Wolfric) 4930bf5be7 Ghosts'n Goblins: Princess Prin Prin Edition Hacks (#2196) 
* Add files via upload

* Add files via upload
 2026-11-02 07:41:43 -05:00
zanacandClaude Opus 5.5 6d162f313c ST-V: critcrsh hammer on the right input ports, lightgun crosshair (#2197) 
critcrsh / tatacot: the hammer was read from input ports 10 and 11,
which don't exist (the lightgun ports are 7 and 8), so the game always
saw it in the top left corner. The lightgun ports default to the
centre, since in this core the lightgun moves from the default value,
and the crosshair is drawn as in MAME. Fixes #2195.


Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX

Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-11-02 07:41:07 -05:00
mahoneyt944 e455f1783a Add files via upload 2026-11-01 07:01:14 -05:00
zanacandClaude Opus 5.5 9275a6a775 ST-V: trackball for the medal games, max geometry from the screen size (#2193) 
- techbowl, patocar, skychal, supgoal: trackball on the 315-5649 port G
  counters, as in MAME (mode register bit 7, counter select and byte in
  port G, auto-increment on read, reset when bit 7 is clear). New input
  stvtrack with trackball X/Y. Fixes #2189.
- libretro video: the max geometry and the conversion buffer use the
  larger of the default visible area and the screen size for raster
  games, so ST-V frames up to 704x480 fit. Fixes #2190.


Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX

Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-11-01 06:50:07 -05:00
zanacandClaude Opus 5.5 4d5e7f3e17 Sega ST-V: faster video (VDP1 clear, VDP2 windows, tiles, sprites, rotation copy); no freeze on reset (#2192) 
Video, same results:
- vdp1_clear_framebuffer: rows filled as one or two runs, eight bytes at
  a time, instead of a masked index per pixel.
- VDP2 windows: the coordinates of each line cached for the whole screen
  update (one entry per line), and the runs of pixels each line shows for
  the current layer cached too; the tiles of a window layer are drawn in
  those runs instead of testing the windows on each pixel.
- Transparent tiles: four pixels tested at once, a transparent group is
  skipped.
- Sprites: in a run of zero frame buffer pixels, four skipped at once.
- vdp2_copy_roz_bitmap: the layer settings read once per line.

Reset (#2188): the machine's timers are freed at each reset, but
machine_init only allocated the SCU DMA, hopper and SMPC INTBACK timers
when its pointers were NULL, so after a reset it adjusted freed timers
and the timer list looped forever. They are allocated at each
machine_init, as the other drivers do.

Fixes #2188


Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX

Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-11-01 02:04:12 -05:00
zanacandClaude Opus 5.5 b168882c39 SH-2 recompiler: compare for CMP/EQ on AArch64 (ST-V black screens) (#2187) 
jit_cmp() asked the flags of the compare with SLJIT_SET(cond & ~1). For
SLJIT_EQUAL that is SLJIT_SET(0), no flag at all: the x86 back ends
compare anyway, the AArch64 one does not, so CMP/EQ Rm,Rn and CMP/EQ
#imm,R0 set T from stale flags. The ST-V BIOS then took wrong branches
and games stayed on a black screen or ran with broken graphics with the
SH-2 Dynarec option on. The zero flag is now asked with SLJIT_SET_Z, as
the SH-3 recompiler already does.


Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX

Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-10-31 15:46:16 -04:00
zanacandClaude 4125e63480 CV1000: faster SH-3 bus timing and screen copy, same results (#2186) 
The cache and bus timing of every SH-3 data access (and of the
instruction fetch sampled with it) was most of the time spent on ARM.
Same output, cycle for cycle:

- fast RAM regions found through a 64 KB page table
- the time of the last bus access kept in 32 bits, relative to the
  start of the timeslice (exact up to 2^30 cycles, "far" beyond, where
  the timing only compares with small counts); the 64-bit value is
  still the one saved in the states
- the tag of the most recently used way of each cache block kept next
  to it, rebuilt eagerly instead of checked on every access
- the cycle count kept in locals across the fetch and data penalties
- the timing fields at the start of the CPU state
- the screen copy in at most two runs per line, with SSE2/NEON


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude <[email protected]>
 2026-10-31 14:22:28 -04:00
zanacandClaude Opus 5.5 90149e76d2 Sega ST-V: cotton2e and puyosune, English translation bootlegs (#2185) 
- cotton2e: Cotton 2 with the story scenes, ending and staff roll,
  continue screen hints, prologue and character profiles in English,
  from the English fan translation of the Saturn port. All eight ROMs
  differ from cotton2; https://github.com/zanac/Cotton2 builds them.
- puyosune: Puyo Puyo Sun with the win quotes, story scenes, endings,
  menus and in-game lettering in English, from the Puyo Nexus English
  translation of the Windows version. Three ROMs differ from puyosun;
  https://github.com/zanac/sega_st-v_puyosune builds them.

znpwfve (All Japan Pro-Wrestling, English) is already in master.


Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX

Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-10-31 03:13:49 -04:00
zanacandClaude Opus 5.5 273f904d7d Sega ST-V: driver, VDP1/VDP2 video and SCU from current MAME, optional SH-2 recompiler and threaded video (#2124) 
- Driver, SCU (DMA, interrupts, timers, DSP), SMPC, MINIT/SINIT, EEPROM
  and the protection chips as current MAME; the current MAME sets.
- VDP1/VDP2 video as current MAME's (one stvvid.c), with exact speedups:
  partial redraw of the rotation plane cache, rotation copy, sprite
  passes, window evaluation once per line.
- SH-2 recompiler on the bundled sljit (x86, x86-64, ARM32, ARM64; the
  "SH-2 Dynarec" core option, off by default): blocks with chaining,
  page tables for direct memory access, memory handlers called from the
  blocks; the SGL idle loop is skipped exactly; context switch by
  pointer. Same output as the interpreter on all the sets.
- "ST-V Threaded Video" core option (off by default): the screen drawn
  in strips by 2-4 threads (libretro-common rthreads, where thread-local
  storage is native), same output.

Two more sets of Zen Nippon Pro-Wrestling Featuring Virtua, both on the
Taiwan BIOS (the core selects it):
- znpwfvt: All Japan Pro-Wrestling Featuring Virtua (Taiwan), as in
  current MAME.
- znpwfve: English translation (bootleg) on the Taiwan program, with the
  graphics the English mode left in Japanese redrawn; the ROMs are built
  from the original ones by https://github.com/zanac/znpwfvt


Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX

Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-10-30 21:57:04 -04:00
mahoneyt944 df60f6466d F1en fix attract sound - JD (#2184) 2026-10-30 12:28:35 -04:00
zanaczanacClaude Opus 5.5
 		b47967f1f2 Sega System E MC-8123, Super Hang-On, Enduro Racer backports; Zero Team save states (#2183) 
System E (segasyse.c, segasyse_vidhrdw.c, mc8123.c, sn76496.c):
- MC-8123 key based decryption from current MAME: Opa Opa (317-0042)
  and Fantasy Zone II (317-0057) now run (MAME set names and keys)
- 315-5124 VDP as in MAME: per VDP status, line counter and frame
  interrupts (only VDP #1 drives /INT), output levels, per-line CRAM and
  scroll latching, front layer backdrop, mode 4 sprites
- Sega PSG clock (10.738635 MHz / 3) and noise
- trackball state saved (Riddle of Pythagoras, Megumi Rescue)

Super Hang-On (outrun.c): backport of MAME segaorun for shangon,
shangon1, shangon2, shangon3, shangon3d, shangonle (FD1089B, memory
mapper, interrupt timing, ADC, YM2151 + SegaPCM).

Enduro Racer (sharrier.c): backport of MAME segahang: FD1089B, both
8255 PPIs (mode 2 sound handshake), ADC0804, sub CPU mirrors, YM2151 and
YM2203 sound boards, Space Harrier sprites and road. Sets enduror,
endurora, endurorb, enduror1, endurobl, endurob2, endurord, enduror1d.
The Hang-On conversions shangonrb and shangonrb2 (old shangonb) use the
same code with the Hang-On main board map.

Sound:
- SegaPCM: register layout as in MAME (current address at 0x84,
  loop at 0x04), 7-bit volumes, 8-voice discrete mode, save states;
  Super Hang-On PCM pitch fixed
- Seibu sound: latches, IRQ vectors and bank saved (Zero Team save
  states, run ahead and netplay now work)


Claude-Session: https://claude.ai/code/session_014P4GcczkZTrzVfrRW8odFY

Co-authored-by: zanac <[email protected]>
Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-10-30 03:39:56 -04:00
zanacandClaude a1fb5c7993 Sega System C/C2 as in current MAME: segac2.c only C/C2, the Mega Drive part in machine/megadriv.c, 25 new sets (#2181) 
- machine/megadriv.c / includes/megadriv.h: the Mega Drive part shared by
  the Mega-Tech, Mega Play, bootleg, Y-BOX and Sun Mixing boards (the VDP
  interrupts, also used by System C/C2, the sound Z80 and its bus, the I/O,
  the machine drivers), moved out of segac2.c; the Mega-Tech / Mega Play
  BIOS VDP ports go to megatech.c, its interrupt to megaplay.c; dead code
  removed (the unused cart maps, inputs and I/O init)
- segac2.c: only System C/C2, with the sets, ROMs, titles, inputs and DIP
  switches of current MAME (57 sets instead of 32; puyopuyo/puyopuya/puyopuyb are now
  puyoj/puyoja/puyobl, columns2 and stkclmns (Japan) are now column2j and
  stkclmnsj, with the World sets as parents)
- the protection chip as the EPM5032 logic of each game of current MAME
  (identical to the old tables where they were real; Ribbit!, Poto Poto and
  Puyo Puyo 2 had fake tables and workarounds)
- the alternate palette mode of Ribbit! and Twin Squash (control bit 2),
  through palette lookups in the VDP, instead of watching Ribbit! ROM reads
- the 68000 at XL2/6 (8.95 MHz) and the refresh at 59.92 Hz as in current
  MAME (it was XL2/7 and 60 Hz); V-INT and H-INT held until the 68000
  acknowledges them, as on the board
- YM2612/YM3438 (shared): the busy flag for 192 clocks after a data write,
  and a timer started long after its last overflow runs a whole period, as
  in current MAME
- Mega Play: the BIOS VDP V-INT about 12 lines after the Mega Drive VBLANK,
  as in current MAME (Tecmo World Cup could stay on a black screen)
- Mega Play / System E: the BIOS VDP tile lines read byte by byte (wrong
  colours on big-endian hosts)
- the address mirrors, the battery-backed work RAM (0xff filled), the coin
  meters on the I/O chip, the Waku Waku Marine / Anpanman wheel
- save states: the alternate palette mode and the Bloxeed YM3438 kludge
- metadata/mame2003-plus.xml, CHANGELOG.md


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude <[email protected]>
 2026-10-30 03:39:39 -04:00
zanacandClaude d7117cdcdc Save states: exact load for Ms. Pac-Man, SNK, Bubble Bobble, OPL, SCSP and Sega Model 2 (#2182) 
- mspacman: the mapped ROM (decoded set or boot ROM)
- snk.c: the sound command/busy register, the sprite blink parity, the
  tile cache marked dirty after a load
- fmopl.c: the whole YM3812/YM3526/Y8950 state (channels, operators,
  envelopes, LFO, noise, timers, status, Delta-T ADPCM); replaces the
  register replay of #2045 (3812intf.c back to its earlier version)
- scsp.c: chip registers, slots, LFOs, DSP, timers, MIDI FIFOs, DMA
- model2: which CPU waits on the i960/copro FIFOs, the SCSP IRQ line
- bublbobl: ROM bank, display enable, sound NMI, MCU port latches
- m6800.c: the 6801/6803/63701 internal registers (ports, timer, TCSR,
  RAM control, WAI state)
- mb86233.c: the stall flag


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude <[email protected]>
 2026-10-30 02:47:53 -04:00
arcadez2003 0ad96d5104 Merge pull request #2180 from zanac/z80-busyloop 
Z80: the delay-loop shortcut counts the DEC cycles
 2026-10-29 22:11:06 +00:00
Claude f80f7223f4 Z80: the delay-loop shortcut counts the DEC cycles of each skipped iteration 
The TIME_LOOP_HACKS shortcut skips the iterations of a
DEC rr / LD A,r / OR r / JR NZ (or JP NZ) delay loop by burning their
cycles in one go. Each skipped iteration runs four opcodes (R is
advanced by 4), but only LD, OR and the jump were counted: the DEC was
left out, so every iteration took 6 cycles too few (20 instead of 26
with JR) and such delays ran about 23% short.

Count the DEC as well, for the BC, DE and HL loops with JR and JP.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX
 2026-10-29 18:16:53 +01:00
SquirbieSquirbieClaude Opus 5.5
 		ff5f1bd024 mame-memory: leave read-only banks of 1 MiB or more out of the save state (#2178) 
register_banks() registers the RAM behind every bank that appears in a
memory map. Banks that only ever show up in read maps are ROM (the ST-V
cartridge bank, 48 MB, or the CAGE sound-board ROM banks, 2 + 16 MB),
but they were still copied into every save state, so states were
20-53 MB for those boards, and netplay, rewind and run-ahead keep many
states at once.

Remember whether each bank appears in a write map and skip a bank of
0x100000 bytes or more that never does. RAM banks and smaller banks are
unchanged, so the state layout of other drivers stays the same. An INFO
log line reports each skipped bank.

Co-authored-by: Squirbie <[email protected]>
Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-10-29 06:08:50 -04:00
SquirbieSquirbieClaude Opus 5.5
 		dfc61f1689 H6280: register CPU state; battlera/actfancr: save HuC6270 VDC and driver state (#2177) 
The H6280 core registered nothing with the save-state system, and the
HuC6270 video chip of the battlera board (VRAM, registers, palette,
scanline/IRQ bookkeeping) and the driver's port select / ADPCM toggle
were not registered either. After a state load the CPU kept running
from its own PC, registers, MMR bank map and timer, and the screen was
drawn from the old VRAM, so netplay guests saw a blank or diverging
screen and rewind / run-ahead diverged.

- h6280.c: register PPC/PC/SP/ZP/EA, A/X/Y/P, the 8 MMR registers, the
  IRQ mask, timer status/ack/value/load, extra cycles and the IRQ lines
  (plus NZ with LAZY_FLAGS) per CPU in h6280_init(), as m6809_init() does.
- battlera_vidhrdw.c: register VRAM, the 20 VDC registers, the VDC
  pointers and flags, last_line (was a function-local static) and the
  palette RAM; a postload handler marks everything dirty and rebuilds
  the palette.
- battlera.c: register control_port_select, msm5205next and the ADPCM
  toggle (was a function-local static) from a new DRIVER_INIT.

Co-authored-by: Squirbie <[email protected]>
Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-10-29 06:06:22 -04:00
zanacandClaude c6a2aa4700 Genie / Y-BOX and Sun Mixing boards in their own drivers (megadriv_ybox.c, megadriv_sunmix.c), as in current MAME (#2179) 
Phase 2.4/5 of the Sega VDP / segac2.c clean-up: Puckman Pockimon and the
other Y-BOX games, and Super Bubble Bobble (Sun Mixing), move from
drivers/segac2.c to drivers/megadriv_ybox.c and drivers/megadriv_sunmix.c,
as in current MAME.

- Sets as in current MAME: puckpkmn is the Genie 2000 set of MAME, the old
  puckpkmn set is now its clone puckpkmnb; new jingling and topshoot.
  xmvsfmb (not working in MAME) is not added: no ROMs.
- The Y-BOX games run on the Mega Drive machine, as MAME's md_ntsc (they
  ran on the System C board): 68000, Z80, the YM3438 on the Z80 bus, I/O
  (no pads), the RAM mirrors, and the VDP interrupts and HBLANK status as
  on the real hardware (genesis_enable_iack). Songjiangyanyi Final waits
  on HBLANK to write the scroll of each line: it hung on a grey screen,
  it now works (imperfect graphics, as in MAME).
- Songjiangyanyi / Shuihu Feng Yun Zhuan protection as in MAME: two read
  back latches selected by A2 (it was a list of fixed addresses), the
  0x70001c value per game, the ROM address remapping at 0x600000 of
  Shuihu Feng Yun Zhuan (an address XOR while a value is latched: the
  data reads through a handler, the opcodes through an opbase handler).
- Jingling Jiazu / Puckman Pockimon: the ID at 0x4b2476 and 0x70001c.
- Top Shooter: the shared RAM inputs of the MCU (not emulated, as in MAME).
- Save states: the protection and remapping state.
- Metadata: mame2003-plus.xml, CHANGELOG.md.


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude <[email protected]>
 2026-10-29 06:00:09 -04:00
zanacandClaude 6266128ce8 Save states: the missing YM2203/YM2610/YM2612, MultiPCM and 6809 state (RunAhead, netplay) (#2176) 
Loading a state, and so every RunAhead or netplay rollback, put back an
incomplete sound chip or CPU, and the game went on differently from the
run that never loaded: the audio of the Mega Drive based boards, Neo Geo
and the YM2203 games diverged, and on the 6809 games the game itself.

OPN chips (sound/fm.c):
- The reset sets the L/R pan of all the channels (0xb4-0xb6) and clears
  0x30-0xb2 without storing them in REGS; the postload rewrites REGS, so
  a channel the game never panned itself was muted after a load (the DAC
  of the Bare Knuckle games). The reset values are now in REGS (YM2203,
  YM2608, YM2610, YM2612), and the YM2612 DAC select too.
- The postloads of the YM2608 and YM2610 skipped 0xb6 (pan, AMS, PMS of
  the 3rd channel of each bank), as the YM2612 one did before.
- The chip recomputes its phase steps and envelope rates only when a
  register asks for it, so they can lag behind the registers (e.g. after
  a 3 slot mode change). They are now saved as they are, with the key
  codes and the LFO step, instead of being remade from the registers. The
  YM2612 and YM2610 extra state is one shared block (OPN_EXT), now also
  used by the YM2203, which had none.
- The YM2612 DAC value is saved as it is: before the first write it is 0,
  which is not what the register gives (aladmdb).
- YM2610: the extra FM and SSG state was opt-in (only zn.c asked for it);
  it is now always saved (Neo Geo). The opt-in FM timers stay as they were.

SSG (sound/ay8910.c): the periods of the SSG of a YM chip are saved as they
were made; the register rewrite of the postload remade them with the
current clock. The YM2203 now saves the SSG extra state too.

MultiPCM (sound/multipcm.c): the sample pointer of a voice was remade from
the registers at load, without the bank and with the sample number of now,
not of the key on; it is saved as its offset in the ROM. The release
counter is saved too (Star Wars Arcade).

6809 family: the M6809 did not save the accumulators (D), the HD6309 D and
W; the M6809, HD6309 and Konami did not save the cycles of an interrupt
taken outside the execute loop.


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude <[email protected]>
 2026-10-28 23:13:45 -04:00
zanacandClaude 9649c81834 Sega Mega Drive bootlegs in their own driver (drivers/megadriv_acbl.c), as in current MAME (#2175) 
Phase 2.3/5 of the Sega VDP / segac2.c clean-up: the coin-op bootlegs of
Mega Drive games move from drivers/segac2.c to drivers/megadriv_acbl.c,
with the board variants of current MAME, and the nine new sets we have
the ROMs for are added. The Mega Drive part stays shared with the other
Mega Drive based boards (includes/segac2.h).

- Moved: aladmdb, barek2ch, barek3mb, jparkmb, sonic2mb, sonic3mb,
  twinktmb (titles as in current MAME). Same code paths as before: frames
  and audio identical to the previous build.
- New: barekch, barek2mb, barek3mba, biohzdmb, bk3ssrmb, mk3mdb, srmdb,
  srssf2mb, ssf2mdb.
- The board variants of MAME: the version register, 6 button pads (MAME's
  TH counter with the 1.5ms timeout), the 3rd I/O port coins, the DIP
  switches at 0x770070 of the scrambled boards (and the coins at 0x770078
  of biohzdmb), the 6MB linear map of ssf2mdb, the PIC16C57 of barek2mb (emulated, with its latches; the
  68000 byte writes reach both halves of the bus as on the real CPU; T0
  is not connected), the simulated PIC of barek3mba.
- The new sets take V-INT / H-INT through the VDP interrupt enables, as on
  the real hardware (mk3mdb took a V-INT before its RAM vector was set
  and crashed); the moved sets keep the old mode.
- Big-endian hosts: the descrambling of the bootlegs uses BYTE_XOR_LE,
  and the PIC program of barek2mb is put in the host order the PIC core
  fetches its opcodes in.
- Mega Drive VDP: in H32 mode the sprite table base uses bit 0 of
  register 5 (AT9), as on the real VDP and in MAME; it was always masked
  as in H40 (ssf2mdb sets 0x6d in H32: the fighters were missing; the sprites
  of mt_bbros were garbled).
- PIC16C5x core: the PC wraps at the end of the program memory (the 2K
  parts start at 0x7ff and ran past the ROM), and the save states no
  longer register the ports and STATUS through R.picRAM before it is set
  (a NULL pointer: saving a game with a PIC crashed). They are in the data
  RAM, saved with the CPU memory.
- Save states: the pad, frame counter and PIC latch state.
- Metadata: mame2003-plus.xml (the bootleg entries regenerated),
  CHANGELOG.md.


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude <[email protected]>
 2026-10-28 23:10:27 -04:00
mahoneyt944 0e919473ca Add files via upload 2026-10-28 19:36:32 -04:00
arcadez2003 fa9eea238c Merge pull request #2173 from grant2258/Makefile 
Makefile (Auto-Dependency Generation)
 2026-10-28 20:59:25 +00:00
arcadez2003 ad755f06ad Merge pull request #2172 from grant2258/fixit 
add Sky Robo and Big Fighter mcu support
 2026-10-28 20:36:18 +00:00
Grantonius maximus 5b5d6f8a23 update gitignore 2026-10-28 20:33:19 +00:00
Grantonius maximus faa5ddf4e9 Makefile (Auto-Dependency Generation) 2026-10-28 20:32:18 +00:00
Grantonius maximus 46f354464a i dont want meee gold 2026-10-28 20:22:55 +00:00
Grantonius maximus 3b41adc749 add Sky Robo and Big Fighter mcu support 2026-10-28 20:19:28 +00:00
arcadez2003 bdfdc977c2 Mention Sky Robo / Tatakae! Big Fighter now works + credits 2026-10-28 20:05:19 +00:00
arcadez2003 5e593b6462 Sky Robo / Big Fighter fix MCU commands grant2258 2026-10-28 19:55:37 +00:00
zanacandClaude da7b539232 Sega Mega-Tech in its own driver (drivers/megatech.c), as in current MAME (#2170) 
Phase 2.2/5 of the Sega VDP / segac2.c clean-up: the Mega-Tech BIOS,
memory maps, inputs, machine drivers, ROMs and game drivers move from
drivers/segac2.c to drivers/megatech.c. The Mega Drive part stays shared
with the other Mega Drive based boards (includes/segac2.h); genesis_base
now starts from the plain cartridge map, each board sets its own.

- Sets, ROM names and dumps as in current MAME (good dumps of mt_bbros,
  mt_ggolf, mt_gng and mt_tetri), the instruction ROMs in the cart at
  0x300000, titles and years as in current MAME.
- The Master System carts run on the Mega Drive in Mark III mode, as in
  current MAME: the 68000 is off, the sound Z80 runs the cart with the
  Sega mapper, 8KB of RAM, the PSG and the VDP in mode 4 (the 315-5313
  variant of the 315-5124 core of MAME). Astro Warrior, Great Golf,
  Shinobi, After Burner and Parlour Games work; Great Soccer is a bad
  dump (as in MAME).
- The BIOS cart slots as in current MAME (the CXD1095 port E slot select,
  the banked RAM per slot, the 0x6000 bank latch and the 0x8000 window
  into the cart): the menu lists the cart in slot 1 only, not in all 8.
- The BIOS display: the 315-5246 224 line mode the menu uses (the MENU
  title was cut), drawn line by line, its own palette levels.
- The Mega Drive VDP line timing and partial updates count its own lines
  below the BIOS screen (segavdp line_scale; 1 for the other boards).
- The H32 games are centred in the 320 pixel screen.
- Mega Play: the BIOS overlay is transparent on colour 0 of both its
  palettes and covers its borders, as in current MAME (the boot logo
  screen was behind a green background).
- Crash fix: the 68000 writes to 0xa02000-0xa03fff went to the Mega Play
  BIOS RAM pointer, NULL on the other boards (Great Golf crashed). The
  Mega Play handler moves to drivers/megaplay.c.
- Save states: the Mega-Tech BIOS, the slots and the Mark III mode state.
- Metadata: mame2003-plus.xml (Mega-Tech entries regenerated), CHANGELOG.md.


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude <[email protected]>
 2026-10-28 15:22:08 -04:00
zanacandClaude eb11c10f08 Sega Mega Play in its own driver (drivers/megaplay.c), as in current MAME (#2168) 
Phase 2.1/5 of the Sega VDP / segac2.c clean-up: the Mega Play BIOS, memory
maps, inputs, machine driver, NVRAM, ROMs and game drivers move from
drivers/segac2.c to drivers/megaplay.c. The Mega Drive part (68000, sound
Z80, I/O chip, interrupts, sound interfaces, pads) stays shared with the
other Mega Drive based boards and is declared in includes/segac2.h; the
Mega Play interrupt acknowledge is enabled through genesis_enable_iack().

- Set names as in current MAME: mp_twc is now mp_twcup, the BIOS version 2
  ROM is epr-a15294.ic2; new clone mp_gaxe2a (Golden Axe II, original
  revision), as in MAME.
- The Mega Play save state registrations move with the BIOS; the unused
  BIOS variables (bios_game, bios_6204, bios_6402) are removed.
- Metadata: driver.c, mame2003-plus.xml (Mega Play entries regenerated),
  catver.ini, history.dat, CHANGELOG.md.


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude <[email protected]>
 2026-10-28 15:00:00 -04:00
mahoneyt944 b3328713bb segas32 fix priority for dbzvrvs and f1lap (#2169) 2026-10-28 14:43:44 -04:00
arcadez2003 7ec7d077f2 Merge pull request #2167 from zanac/sega-vdp 
Phase 1: the Sega Mega Drive VDP (315-5313) as a shared module
 2026-10-28 14:13:14 +00:00
arcadez2003 5c6f346782 Come back to it later 2026-10-28 12:49:34 +00:00
arcadez2003 51e87e8a46 FFS Forgot this 2026-10-28 12:41:15 +00:00
arcadez2003 6926b424a6 Attempt to get the main and prot MCU's talking :) 2026-10-28 12:27:07 +00:00
Claude 122405bb79 Sega VDP (315-5313) as a module shared by System C/C2, Mega-Tech, Mega Play and System 18 
The Mega Drive VDP was part of the System C/C2 video code and System 18 used
it through file-static state and a few flags, so a change for one board could
reach the others. It is now a module, vidhrdw/segavdp.c:

- all its state is in one struct, cleared at every start;
- each user starts it with its own configuration (struct segavdp_interface):
  where the CRAM writes go (paletteram16, or the 64 System 18 colors set
  directly at 0x1800), the initial palette bases, the scanline base of the
  partial updates, the initial display enable, whether register 12 resizes
  the screen, and the interrupt callback for writes to registers 0/1;
- the boards use accessors (segavdp_get_reg, segavdp_set_palbank, ...);
- vidhrdw/segac2_vidhrdw.c keeps only the C/C2, Mega-Tech, Mega Play and
  bootleg video glue, vidhrdw/segas18.c the System 18 one.

Fixed on the way (state left over from a previous game in the same process):
the display enable and the Mega Play interrupt-acknowledge/HBLANK mode
(now also reset by the C/C2 machine init). The window X
position/width and the VBLANK flag are now in the save states. The dead
ddcrew/aquario VDP kludges of the old System 18 video are removed.

Save states loaded in a new instance (netplay, RunAhead with a second
instance) now continue exactly as the instance that saved them:
- Mega Drive based boards (drivers/segac2.c): the Z80 RAM and bus state
  (running flag, bank latch) and the Mega-Tech / Mega Play BIOS registers
  and RAM were not saved (mp_gunhe and mp_mazin went out of sync);
- sound/sn76496.c: the PSG had no save state at all;
- sound/fm.c: the YM2612 postload read the DAC enable from register 0x2d
  instead of 0x2b (the DAC channel was lost or computed as FM after a load).

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX
 2026-10-28 09:51:57 +01:00
arcadez2003 f51acae279 terraf_io_w 2026-10-28 00:43:49 +00:00
arcadez2003 02beadf6c1 hmmmmm 2026-10-28 00:30:19 +00:00
arcadez2003 c542bf7d24 Forgot cant share via port io's in this core 2026-10-28 00:11:52 +00:00
arcadez2003 4d19fd28b8 Adjust the MCU mem and port loading 2026-10-28 00:05:49 +00:00
arcadez2003 34bf3c28c6 Merge pull request #2165 from zanac/cotton 
Sega System 18 and Cotton from current MAME
 2026-10-27 23:41:19 +00:00
arcadez2003 ca185b19ad skyrobo and bigfghtr 2026-10-27 19:55:15 +00:00
arcadez2003 a2960b3fca Support Sky Robo / Tatakae! Big Fighter hook up I8071 MCU 
With thanks to AdvanceMAME

MAME WIP

0.182: Dumped i8751 MCU for Sky Robo / Tatakae! Big Fighter and added basic hookup to make it work - Game now playable. Fixed screen refresh rate in Tatakae! Big Fighter [Team CAPS0ff, Angelo Salese]. Fixed service switch and updated DIPS/inputs with locations and content to match those showing on screen and observation [Tafoid]. Added debug code for initial area and promoted game to working [Angelo Salese]. Clocks verified for Sky Robo / Tatakae! Big Fighter [Guru]. Documented DACs for clone Tatakae! Big Fighter (Japan) [AJR]. Added I8751 (8MHz) CPU3. Changed VSync to 59.314620 Hz.

0.142u2: Angelo Salese merged Tatakae! Big Fighter driver into ArmedF driver.

0.141u1: Changed Z80 CPU2 clock speed to 4MHz.

0.140u3: Angelo Salese fixed service mode and removed ROM patches in clone 'Tatakae! Big Fighter'. Changed description of clone 'Tatakae! Big Fighter' to 'Tatakae! Big Fighter (Japan)'.

0.113u2: Stefan Lindberg added 'Sky Robo' (Nichibutsu 1989).

0.86: Tomasz Slanina added 'Tatakae! Big Fighter' (Nichibutsu 1989). TODO: Scroll, controls and dips.

15th August 2004: Tomasz Slanina - Tatatake! Big Fighter preliminary driver (based on my old one). Game doesn't work due to protection (RAM shared with 8751 MCU).

1st September 2003: Tomasz Slanina - VERY preliminary Tatake! Big Fighter driver. Unemulated protection (MCU). Only attract mode is working. Partially...
 2026-10-27 19:51:44 +00:00
Claude 7d3a3547e3 Sega System 18 and Cotton from current MAME (FD1094 sets, mapper, VDP, save states) 
Cotton (System 16B): the FD1094 sets cotton, cottonu, cottonj and cottonja
now run, with the decryption of machine/fd1094.c (from Moonwalker), and the
missing bootlegs cottonud, cottonjd and cottonjad are added. The dummy
cotton/cottona of system16.c are removed.

System 18: the games run on the 315-5195 mapper layout each of them sets
(read from MAME), the segaic16 video and the VDP layer, as in MAME's
segas18.cpp:
- Alien Storm (astorm, astorm3, astormu, astormj and bootlegs), Bloxeed
  (bloxeed, bloxeeda, bloxeedd), Clutch Hitter (cltchitr, cltchitrj and
  bootlegs), D. D. Crew (the six FD1094 sets and their bootlegs, 4 players
  through the 8255), Desert Breaker (desertbr, desertbrj and bootlegs),
  Laser Ghost (lghost, lghostu, lghostj and bootlegs, light guns through
  the MSM6253, MAME's gun offset correction), Wally wo Sagase! (wwallyj,
  wwallyja, wwallyja3p and bootlegs, uPD4701 trackballs), Shadow Dancer
  (shdancer, shdancerj, shdancer1, were shdancer, shdancrj, shdancrb).
- 171-5987 ROM board: ROM 1 at 200000, tile and sprite banking, 1MB and
  2MB program ROMs; fd1094.c decrypts several address windows.
- The VDP layer shows one frame after the other layers, as in MAME, and the
  VDP sees the VBLANK (VIDEO_EOF of segac2) for its partial updates.
- astormbl, shdancbl, moonwlkb, aquario, hamaway and mwalk are unchanged.

Save states (RunAhead, netplay):
- System 16B: uPD7759, sound ROM bank, segaic16 tilemap and sprite banks,
  flip, scroll latches, display enable.
- System 18: RF5C68 (registers and wave RAM), YM2612/YM3438 (envelope and
  LFO counters, key, frequencies, algorithm memory, FM timer overflow time;
  the postload also rewrites the b6/1b6 registers), sound ROM bank, VDP
  layer, mapper and I/O registers.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX
 2026-10-27 11:53:07 +01:00
markwkidd 993403d033 Merge pull request #2159 from markwkidd/cpu-clock-core-options 
Add a CPU Clock Scale core option for each CPU
 2026-10-26 16:20:17 -04:00
zanacandClaude Opus 5.5 64b3c38ac6 Sound: 0-100 volume standard for the mixer and samples, fix filter.c float build (#2164) 
- sample_set_volume()/sample_set_stereo_volume() take 0-100 like the
  mixer. The 0-255 callers are converted with identical results; Sea Wolf
  II and Thief get the full volume they meant, and the Sea Wolf II dive
  channels (always silent) work as in MAME 0.264.
- The mixer clamps volumes, mixing levels and default levels to 0-100.
  The old 0-255 default level conversion is removed; the drivers that
  used it get its result (25) explicitly. Buggy Boy's doubled YM2149 gain
  is kept with a doubled mixing level.
- filter.c: the non-integer build did not compile and scaled the
  coefficients twice; both builds now divide by the gain.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX
 2026-10-26 13:31:46 -04:00
markwkidd 42176a69d1 Fix discrete adjuster ports and defaults (#2161) 2026-10-26 03:51:14 -04:00
zanacVanni BruttoClaude Opus 5.5
 		bbb49d84d7 PSX GPU: 11-bit signed coordinates for rectangles, sprites, lines and dots (#2162) 
Soul Calibur draws the attract transitions (the windows that open from
the title screen onto the next scene, and the wipes before each demo)
with rectangles whose coordinates only make sense as 11-bit signed
values. The core took them as 16-bit values, so the rectangles were
drawn in the wrong place or not at all, and the new scene showed
through white or washed out instead of in full colour.

As in current MAME (S11_COORD_X / S11_COORD_Y), rectangles, 8x8 and
16x16 sprites, lines and dots now take 11-bit signed coordinates, like
the polygons already did. The frame buffer fill (GP0 02h) keeps its
unsigned coordinates.


Claude-Session: https://claude.ai/code/session_01MEgow1uRCv8pxMErKhmoHZ

Co-authored-by: Vanni Brutto <[email protected]>
Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-10-26 03:49:56 -04:00
markwkidd 79a4e690a4 Update descriptions for core resolution options (#2155) 2026-10-26 03:48:57 -04:00
Mark W. Kidd 75f4dbb1d9 Name the romset in the CPU Clock Scale core option keys 2026-10-25 22:53:22 -04:00
arcadez2003 fd95cd4b28 Mention Heavy Unit and new code contributors 2026-10-25 23:39:17 +00:00
Mark W. Kidd e0815b5b43 Add a CPU Clock Scale core option for each CPU 2026-10-25 19:26:21 -04:00
arcadez2003 f584d820f6 Merge pull request #2158 from sunlollyking/model1-tgp-names 
Model 1: rename the TGP's fadd, fsub, fmul, fdiv and fsqrt
 2026-10-25 23:23:45 +00:00
arcadez2003 d373dcb4b1 New ones 2026-10-25 22:35:19 +00:00
Chris 0c777d48e6 Model 1: rename the TGP's fadd, fsub, fmul, fdiv and fsqrt 
glibc declares fadd, fsub, fmul, fdiv and fsqrt in math.h for C23, and
GCC 15 builds as C23 by default, so the static TGP functions of the same
names conflict with them and model1_machine.c no longer builds. They are
tgp_fadd and so on now.
 2026-10-25 22:33:44 +00:00
arcadez2003 8a0a74c79f Merge pull request #2154 from libretro/arcadez2003-patch-8 
Add the two missing games to the Cave CV1000 driver
 2026-10-25 22:31:03 +00:00
arcadez2003 4060e4c8e1 Hush Hush On The QT 2026-10-25 22:29:56 +00:00
arcadez2003 1f8b8b71b1 Try again another time 2026-10-25 22:15:46 +00:00
arcadez2003 ae45f94fc9 Revert for now 2026-10-25 22:15:04 +00:00
arcadez2003 e7b2e2706c FFS 2026-10-25 22:08:32 +00:00
arcadez2003 cf8d7da002 Update YGV608 namcond1 video code to MAME 113 part 2 2026-10-25 21:48:53 +00:00
arcadez2003 bbf2784396 Update YGV608 namcond1 video code to MAME 113 2026-10-25 21:47:29 +00:00
arcadez2003 7a361d0dad Merge pull request #2156 from zanac/mariner-sound 
Mariner / Triple Punch: AY-8910 clock of current MAME, new clones; Galaxian/Scramble hardware save states
 2026-10-25 21:09:21 +00:00
Claude ce9db6e3cc Mariner, Triple Punch: AY-8910 clock of current MAME, new clones; Galaxian/Scramble hardware save states 
- AY-8910 of the Triple Punch board (Triple Punch, Knock Out!!, Mariner,
  800 Fathoms) at 18432000/12 = 1.536 MHz, as current MAME ("verified on
  hardware"): the sound was 16.7% too high and too fast. Mariner keeps
  GAME_IMPERFECT_SOUND: its discrete sound circuits are not emulated, in
  current MAME either; 800 Fathoms gets the flag, as in MAME
- new clones from current MAME: triplepa, knockoutb, knockoutc, 800fatha
  (names and manufacturers of the sets as in MAME)
- save states of the Galaxian/Scramble/Frogger hardware (rollback, RunAhead,
  netplay diverged):
  - Galaxian video: star scroll/blink state, star timer start, flip, graphics
    banks, background and bullet colors, rockclim scroll; a postload restores
    the tilemap flip, column scroll and tiles
  - 7474 flip-flops (machine/7474.c), registered by TTL7474_config
  - Scramble sound: the sound CPU RAM (scobra map) in the saved memory, the
    AY port B timer computed from the sound CPU cycles as current MAME
    (no state, no 32-bit overflow; same values)
  - RC filters of the sound streams (streams.c) and the global sound enable
    (mixer.c)
  - Galaxian sound statics (LFO, noise, tone generator)

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX
 2026-10-25 21:12:09 +01:00
arcadez2003 0742497860 Merge pull request #2152 from zanac/tx1 
Tatsumi TX-1 / Buggy Boy from current MAME
 2026-10-25 20:08:32 +00:00
arcadez2003 02cbb28183 Merge pull request #2151 from zanac/ymf278b-state 
YMF278B, YMF262 and Fuuki FG-3: save states
 2026-10-25 20:03:31 +00:00
arcadez2003 aca3960858 Add the two missing games to the Cave CV1000 driver 
redone as per recent commits
 2026-10-25 20:03:01 +00:00
arcadez2003 daf2acebc9 Merge pull request #2143 from zanac/mwalk 
Moonwalker: the original System 18 board (FD1094 + 8751)
 2026-10-25 19:38:30 +00:00
arcadez2003 f8aebaebbc Merge pull request #2153 from zanac/toaplan2-savestates 
Toaplan 2: save states, RunAhead and netplay
 2026-10-25 19:15:05 +00:00
arcadez2003 9dcf3f94ed Merge pull request #2150 from zanac/toaplan2-v25 
Toaplan 2: NEC V25 sound CPU (Dogyuun, Knuckle Bash, FixEight, Grind Stormer / V-Five, Batsugun)
 2026-10-25 19:08:06 +00:00
Claude ccdf3afc6a Tatsumi TX-1 / Buggy Boy from current MAME (TX-1, Buggy Boy, Buggy Boy Junior) Closes #1478 
The driver of current MAME (Phil Bennett) in C89: the two 8086 CPUs and the
arithmetic unit, the road, object and character layers of the three screens,
the engine/noise sound with the AY-8910 / YM2149s, save states.

- 6 sets: tx1, tx1jb, tx1jc, buggyboy, buggyboyb, buggyboyjr
- the cockpit sets show their three screens side by side (768x240, 12:3), or
  only the middle one with the new core option "TX-1 / Buggy Boy Screens"
  (offered for those sets only)
- i86 core: the TEST input (WAIT instruction) and an opt-in 16-bit data bus
  (an aligned word is one access for the handlers); both off by default, the
  other i86/i186 games run as before
- the layer select and the TX-1 road pixel logic are lookup tables built
  from MAME's logic: same pixels, TX-1 about 40% faster

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX
 2026-10-25 19:42:25 +01:00
VanniandClaude Opus 5.5 e764a06a04 Toaplan 2: save states, RunAhead and netplay (video, driver state, V25 timers) 
The frames after loading a state are now the same as after the save, in
every Toaplan 2 / Raizing game, also when the state is loaded in the same
process as RunAhead and netplay do at every frame.

- Video (toaplan2_vidhrdw.c): the RAM of the GP9001 controllers (layers,
  sprites), their registers (scroll, flip, VRAM offset), the RAM of the
  68000 map written through a handler (palette, text layer, text tiles),
  as MAME's GP9001; after a load the tilemaps get their scroll and flip
  again and the text tiles in RAM whose bytes changed are decoded again
  (Batrider and Battle Bakraid: from a copy of the RAM when they were
  decoded).
- Driver: scanline counter, sound CPU latches and replies, Z80 bank,
  Raizing and FixEight bootleg OKI banks, Ghox paddles, the 68000 side of the Dogyuun location
  test shared RAM (now allocated once, 0x1000 bytes).
- V25: the timers are in the timer state; after a load only the clock
  divider is set again.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX
 2026-10-25 18:11:56 +01:00
Claude 0c9afd4989 YMF278B, YMF262 and Fuuki FG-3: save states 
None of the YMF278B (OPL4 PCM), YMF262 (OPL3) or Fuuki FG-3 state was in
the save states: after a load (RunAhead, netplay rollback, rewind) the
sound kept the voices of the frames run before the load, the YMF278B
timers and IRQ their old values, the sprites buffered by two frames and
the RAM shared by the two CPUs of the FG-3 too.

- YMF278B: every slot, the chip registers, timers and IRQ state.
- YMF262: every slot and channel, the chip registers; the slot outputs
  (pointers to the channel outputs) are saved as indexes.
- Fuuki FG-3: the two buffered sprite RAMs and tile banks, the shared RAM.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX
 2026-10-25 17:09:58 +01:00
VanniandClaude Opus 5.5 127a425837 Toaplan 2: NEC V25 sound CPU (Dogyuun, Knuckle Bash, FixEight, Grind Stormer / V-Five, Batsugun) 
New NEC V25 CPU core (src/cpu/nec/v25.c), a port of MAME 0.264's v25.cpp
and v25sfr.cpp, with the opcode decryption tables of the Toaplan chips.

The Toaplan 2 games with a V25 now run their sound program as in MAME
0.264, in place of the sample tables (Knuckle Bash, Batsugun) or no sound
(Dogyuun, Grind Stormer, V-Five). FixEight works: its V25 reads the inputs
and the EEPROM holding the settings and the region.

- 68000 and V25 memory maps, clocks, shared RAM, the V25 reset (coin
  register and RESET instruction), DIP switches and jumpers read by the V25.
- The GP9001 video status as in MAME (blank in the horizontal sync too):
  the boot RAM tests of these games now take the same time as in MAME.
- Sets and names of MAME 0.264: new dogyuuna, dogyuunb, dogyuunt, kbashk,
  kbashp, batsuguna, batsugunc, batsugunb, 13 FixEight regional sets;
  grindsta -> grindstma, batugnsp -> batsugunsp, fixeighb -> fixeightbl;
  grindstm is now the parent of vfive; new ROMs for dogyuun and batsugun.
- Memory: no save state zone for a CPU without a memory region.
- Metadata (xml, history, cheats, catver) and frontend list updated.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX
 2026-10-25 17:00:58 +01:00
zanacandClaude eedb4b5ce0 CV1000: about 40% faster (SH-3 cache model, recompiler, SSE2/NEON blitter), same results (#2149) 
- SH-3 cache model: a fast path for a hit in the most recently used way
  of its block (no LRU update, no miss handling); the bus timing inlined
  in the memory accessors.
- SH-3 recompiler: block table of 512K entries instead of 64K (two code
  areas of some games shared the entries and recompiled each other).
- SH-3: memory accessors inlined, the fast RAM region of the previous
  access first; DMA byte transfers to fast RAM without a region lookup
  per byte.
- Blitter: uploads a row at a time; draws 8 pixels at a time with SSE2
  or NEON, the blend tables computed exactly (T(a, b) = (a * b) / 31 =
  mulhi(a * b, 2115) for every product up to 31 * 63). The C loop stays
  for the other hosts.

The save states are byte-identical to before, with the interpreter and
with the recompiler.


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude <[email protected]>
 2026-10-25 11:35:37 -04:00
zanacandClaude Opus 5.5 65456ae709 Random numbers: the emulation's generator in place of the C library's rand()): (#2144) 
* Random numbers: the emulation's generator in place of the C library's rand()

The C library's rand() gives other numbers on each host and C library,
and its state is not in the save states: the games using it (the
Astrocade noise, the speech chips, the HuC6280 noise...) ran differently
after a state load (RunAhead, netplay rollback, rewind) and on another
host (netplay).

The code that only changes the picture gets a generator of its own, also
in the save states: the screen updates don't run on the skipped frames,
and the frameskip depends on the host speed.

Radar Scope's star noise compared mame_rand() with RAND_MAX, which is
0x7fff on MSVC.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

* Astrocade sound: the noise counter of the chip, not of the sample

The noise byte was refreshed reading current_count_N[i], with i the
sample position (up to the samples per frame), out of the array of two:
other variables and whatever follows them in memory, which is not the
same on every host and compiler.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

---------

Co-authored-by: Claude <[email protected]>
 2026-10-25 09:23:14 -04:00
zanacandClaude ff31c50883 Astrocade: save states (sound chip, video, machine, speech) (#2145) 
Nothing of the Astrocade games was in the save states: after a load
(RunAhead, netplay rollback, rewind) the interrupt and colour registers,
the magic RAM and pattern board, the sound chip and the speech word
being built kept their values from the frames run before the load.

The pattern board registers, the colour block counter and the Gorf timer
skip counter were static in their functions; they are now file statics.


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude <[email protected]>
 2026-10-25 09:22:39 -04:00
zanacandClaude Opus 5.5 650346ec75 Cave CV1000: SH-3 (SH7709S) with recompiler, driver, EPIC12 blitter, YMZ770 Closes #751 (#2146) 
* Save states: the audio frame length (samples per frame) and its fraction

When the frame rate doesn't divide the sample rate, the frames alternate
their number of samples; where they are in that was not in the save state,
so after a load the mixer asked the streams for a different number of
samples and the audio drifted from the run that never loaded (netplay CRC
mismatches in the mixer state, RunAhead audio).

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

* Cave CV1000: SH-3 (SH7709S) with recompiler, driver, EPIC12 blitter, YMZ770

The Cave CV1000-B and CV1000-D games (Mushihime-Sama, Ibara, Espgaluda II,
Muchi Muchi Pork, Pink Sweets, Mushihime-Sama Futari, Deathsmiles, DoDonPachi
Dai-Fukkatsu and their sets), ported to C89 from current MAME:

- src/cpu/sh3: the SH7709S interpreter (current MAME's SH-3 with the cycle
  counts of MAME's recompiler and its cache and bus timing model), the
  interrupt controller, timers, DMA, ports.
- src/cpu/sh3/sh3jit.c: an SH-3 recompiler on sljit with the same results
  as the interpreter, cycle for cycle (save states, netplay and RunAhead
  don't depend on it); core option "SH-3 Dynarec", on by default, offered
  on x86, x86-64, ARMv7 and AArch64.
- src/drivers/cv1k.c: memory maps, NAND flash, RTC9701, idle loop
  speedups, the sets.
- src/vidhrdw/cv1k_vidhrdw.c: the EPIC12 blitter (16-bit VRAM).
- src/sound/ymz770.c and the AMM variant of MPEG audio in mpeg_audio.c.

Everything is in the save states. Details in docs/cave-cv1000.md.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

---------

Co-authored-by: Claude <[email protected]>
 2026-10-25 09:22:06 -04:00
VanniandClaude Opus 5.5 3a553e7fb4 Moonwalker: the original System 18 board, with FD1094 and 8751 
The original sets now run: mwalk, mwalku and mwalkj (FD1094 encrypted 68000)
and their decrypted versions mwalkd, mwalkud and mwalkjd, as in MAME 0.264.
moonwalk and moonwlka are renamed to the current MAME names (mwalk, mwalku).

- machine/fd1094.c: FD1094 decryption (the algorithm of MAME's fd1094.cpp,
  BSD-3-Clause). The decrypted opcodes are cached per state and fetched
  through the 68000 opcode base; the state follows CMPI.L #imm,D0, the
  interrupts and RTE through new hooks in the C 68000 core (NULL unless an
  FD1094 game runs).
- system18.c: the 8751 (315-5437) drives the game through the 315-5195
  mapper registers (68000 interrupts, 68000 memory reads and writes, sound
  CPU latches, 68000 reset), as MAME's system18_i8751. The game uses the
  segaic16 video like ddcrew, with the 171-5874 tile banking.

The FD1094 sets give the same frames as the decrypted ones, and the attract
mode and the first 2140 frames of a scripted game match MAME 0.264 pixel for
pixel.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX
 2026-10-25 08:59:27 +01:00
zanacandClaude cc7b0dd9a1 Makefile: no fused multiply-add (-ffp-contract=off) (#2142) 
GCC and clang fuse a*b+c into one FMA instruction where the CPU has one
(AArch64, ARMv7 VFPv4, PowerPC): rounded once instead of twice, so the
floating point results differ from x86, where there is no FMA in the
baseline instruction set. With the flag every host computes the same
values: netplay between x86 and ARM, save states and RunAhead.

x86 and x86-64: the generated code is the same with and without the flag.


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude <[email protected]>
 2026-10-25 03:25:40 -04:00
zanacVanniClaude Opus 5.5
 		d57fdfe4ee hvyunit: boots and plays (#2140) (#2141) 
The black screen came from the protection MCU (Mermaid, i8051) clock: this
core takes the i8051 clock already divided by 12 (I8051_CLOCK_DIVIDER, as
the System 1 8751), the driver gave the 6MHz crystal, so the MCU ran 12
times too fast and its handshake with the slave Z80 never completed.

With that, the rest of the driver is brought in line with current MAME's
hvyunit.cpp:
- the slave Z80 <-> MCU latches as MAME's generic_latch_8 (reading a latch
  clears it, P0 bit 0 low reads the slave's byte and acknowledges INT0,
  P0 bit 4 updates the coin counters and lockouts), MCU ports at 0xff on
  start;
- the slave's vblank interrupt is held until it acknowledges it on port
  0x0e (it was the coin counter);
- the master's interrupts at lines 240 (vector 0xfd) and 64 (0xff);
- the YM2203 interrupt drives the sound CPU (no more vblank interrupt).

All four sets boot and play the first stage; the death/respawn sequence
and the music tempo match MAME 0.264.


Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX

Co-authored-by: Vanni <[email protected]>
Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-10-25 03:23:05 -04:00
zanacandClaude 4c70822b8f CPS1/CPS2: complete the save states (#2136) 
Rollback (RunAhead, netplay) diverged on CPS2 games: the raster interrupt
counters, the object RAM bank, the sprite priorities and the latched
sprite lists were not saved, and the palette cache kept the values of the
discarded frames. The EEPROM didn't save its "sending" flag either.

- save scanline1/2, scancalls, scancount (moved out of cps2_interrupt),
  the object RAM bank, the sprite priorities and the buffered sprite lists
- after a load, recalculate the video RAM pointers and rebuild the whole
  palette on the next update
- EEPROM: save the "sending" flag


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude <[email protected]>
 2026-10-24 21:44:15 -04:00
arcadez2003 ef0071b1bd Merge pull request #2139 from libretro/arcadez2003-patch-6 
hvyunit sets
 2026-10-25 00:44:43 +01:00
arcadez2003 9e2bb67fe4 Merge pull request #2138 from libretro/arcadez2003-patch-5 
Declare hvyunit.c
 2026-10-25 00:44:28 +01:00
arcadez2003 30ed1cd5ad Merge pull request #2137 from libretro/arcadez2003-patch-4 
New driver for Heavy Unit
 2026-10-25 00:44:14 +01:00
arcadez2003 3e2c0db497 hvyunit sets 2026-10-25 00:17:01 +01:00
arcadez2003 38d906cb98 Declare hvyunit.c 2026-10-25 00:13:32 +01:00
arcadez2003 084b3535b3 New driver for Heavy Unit 2026-10-25 00:11:52 +01:00
arcadez2003 e49db47d7d paletteram_xxxxRRRRGGGGBBBB split types 1 and 2 2026-10-25 00:02:40 +01:00
arcadez2003 d87508ce4f New paletteram split types 2026-10-24 23:59:34 +01:00
arcadez2003 4fd1c76422 Merge pull request #2135 from zanac/seibuspi-v2 
Seibu SPI and SYS386I: driver and i386 CPU from current MAME (57 sets)
 2026-10-24 17:17:44 +01:00
zanacandClaude c262d4a4b6 Random numbers: the generator of current MAME, in the save states (#434, #445, #212) (#2132) 
The drivers used the C library's rand() for game logic (protection,
hardware reads, the 4-way joystick restrictor). Its numbers:
- differ between C libraries (glibc, MSVC, bionic, macOS), so two netplay
  machines on different systems get different numbers;
- come from one sequence shared by the whole process: the frontend and the
  core's own drawing and sound code take numbers from it too, so how many
  the game gets depends on them;
- are not in the save states, so after a load (RunAhead, netplay rollback,
  rewind) the game gets other numbers than the first time.

mame_rand() is now the generator of current MAME (running_machine::rand()
in src/emu/machine.cpp): a linear congruential generator with MAME's seed,
rotated by 16 bits, whose 32-bit state is in the save states. It replaces
the Mersenne Twister of 0.78, whose state was not saved. mame_rand_int()
gives the same range as rand(). The rand() calls that change the state of
the emulation now use it; the ones that only draw, make sound noise or fill
memory at startup are unchanged.


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude <[email protected]>
 2026-10-24 12:08:55 -04:00
zanacandClaude c47cda1f40 Save states: timer system and CPU scheduling (#434, #445, #212) (#2133) 
A save state did not include the timer system: after a load, every timer
(interrupts, sound chip timers, CPU synchronizations, driver timers) went on
from where the running emulation was, not from the state. The CPU
scheduling state was also missing. So a loaded state ran differently from
the run it was saved from: RunAhead, netplay rollbacks and rewind replayed
the frames with other timings.

- timer.c: the timer pool and lists are saved, with the same fields as
  current MAME (param, enabled, period, start, expire). Pointers are saved
  as pool indexes and callbacks as their distance from timer_init(), which
  is the same on every machine running the same build; a fingerprint of the
  build is saved with them, and a state from another build loads without
  the timers, with a warning. Unlike current MAME, temporary timers
  (timer_set) are saved too: 0.78 drivers use them across frames. A new
  timer takes the lowest free slot, so a machine reset allocates the same
  slots again.
- cpuexec.c: suspend and eat-cycles states, trigger, interrupt loops,
  vblank countdown and frame number, as current MAME saves them in
  device_execute_interface, restored when the timers were loaded.
- cpuint.c: no second interrupt event timer after a load.
- Z80: the cycles taken by an interrupt. AY8910: the chip state.
- Input ports: the 4-way joystick states, the impulse and pressed states and
  the analog positions, which depend on the previous frames.
- libretro: retro_unserialize() refused to load at frame number 0, to block
  the automatic state loading at startup. A machine reset also sets the
  frame number to 0, so a rollback over the frame after a reset failed. It
  now refuses only until the first frame has run.


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude <[email protected]>
 2026-10-24 12:08:34 -04:00
zanacVanniClaude Opus 5.5
 		bc75df8087 Vector resolution: applied while the game runs (#435) (#2130) 
Changing the Vector Resolution core option no longer needs a restart. At
the next frame the core resizes the display and gives the frontend the new
size with RETRO_ENVIRONMENT_SET_SYSTEM_AV_INFO (it can grow past the old
maximum).

- mame.c: vector_resize_display() does what vh_open() does for the
  display: the size from the option, the artwork, a new screen bitmap,
  the visible area again.
- artwork.c: artwork_resize_display() keeps the loaded artwork and makes
  again what depends on the size: the layer bitmaps, the scaled pieces,
  a driver's generated overlays (drawn at the game's size), the UI areas;
  the next frame is drawn whole, not from the vector dirty pixels. The
  palette lookup is allocated once per game.
- vector.c: the pixels drawn on the old bitmap are forgotten, and the next
  refresh does not compare with the old vector list.
- common.c: auto_free_ptr() / auto_bitmap_free() free one auto_malloc
  block before its tag ends, so the old bitmaps don't pile up.
- core_options.c: the option is applied only when it really changes (other
  options no longer reset the size the artwork chose).

The frames after a change are identical to a game started at that
resolution (Lunar Lander: no artwork, .art backdrop/overlay, a generated
overlay with disks; 640x480, 1600x1200, original), memory stays flat over
61 changes, and without a change the output matches master.


Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX

Co-authored-by: Vanni <[email protected]>
Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-10-24 12:01:06 -04:00
zanacandClaude ea58c97b57 GAME_DOESNT_SERIALIZE: own flag bit, it was IMPERFECT_SOUND | WRONG_COLORS (#212) (#2131) 
GAME_DOESNT_SERIALIZE was 0x0420, which is GAME_IMPERFECT_SOUND (0x0400)
plus GAME_WRONG_COLORS (0x0020). state_get_dump_size() tests
flags & GAME_DOESNT_SERIALIZE, so every game flagged with imperfect sound
or wrong colors (323 games) reported a save state size of 0: no save
states, rewind, RunAhead or netplay, and the startup warning said the
game doesn't support save states. No driver uses the flag itself.

It now has its own bit, 0x0800, which no other flag uses.


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude <[email protected]>
 2026-10-24 11:58:08 -04:00
Claude 14e3abc89f Seibu SPI and SYS386I: driver and i386 CPU from current MAME (57 sets) 
- i386 CPU core: the C core of MAME 0.139 (mame2010-libretro), on the
  0.78 CPU interface, with save states. Fast memory: the driver gives
  its plain RAM and ROM, which the CPU fetches, reads and writes
  directly (a cached region per kind of access) instead of through
  the memory handlers.
- Seibu SPI driver from current MAME: the SXX2C main board with its
  cartridges, the SXX2E / SXX2F / SXX2G single boards and SYS386I.
  Senkyu / Battle Balls, Viper Phase 1, Raiden Fighters, Raiden
  Fighters 2 and Raiden Fighters Jet, 57 sets.
- Video, the CRTC, the tile and sprite decryption (SEI252, RISE10,
  RISE11) as current MAME.
- DS2404 RTC from current MAME. Its 256 Hz tick keeps the time it had
  left across a save state.
- intelfsh: 8-bit chips, the E28F008SA of the SPI main board.
- YMF271: the clock in the interface (16.384MHz on SXX2G).

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01MEgow1uRCv8pxMErKhmoHZ
 2026-10-24 17:54:15 +02:00
arcadez2003 ac620b3686 Merge pull request #2134 from zanac/ikarijpb-dualstick 
Closes #1581. **Ikari (joystick hack bootleg)** (`ikarijpb`) can now be played with two sticks
 2026-10-24 15:59:23 +01:00
Claude bd64b9de5e ikarijpb: dual stick aiming with the right stick, as a DIP switch (#1581) 
The bootleg has no rotary joystick: the game reads the direction the
player faces, and fires to, in the upper nibble of the joystick port, and
snk_rot8_ikarijpb() sets it from the joystick, so the player fires where
he walks. A new 'Aim with Right Stick' setting (a DIP switch that is not on
the board, Off by default) makes a pushed right stick set it instead: the
player walks with the left stick and aims with the right stick, in 8
directions. With the right stick released, the direction follows the
joystick again.

The right stick inputs (P1 Aim, P2 Aim) default to the right analog stick
of each player, and to I/J/K/L for player 1. They are read only by the
driver, not by the game. With the setting Off the game runs as before.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX
 2026-10-24 15:19:06 +02:00
zanacandClaude 196f1d69d3 libretro: ignore controller ports past the 8 players of the core (#445) (#2129) 
retro_set_controller_port_device() wrote options.active_control_type[in_port]
for any port. That array has MAX_PLAYER_COUNT (8) entries, but RetroArch
sets the device of all its users, and on a netplay client it sets all 16
netplay ports (the host's devices, in NETPLAY_CMD_SYNC). Ports 8-15 then
overwrote the options that follow the array: restrict_4_way, tate_mode,
crosshair_enable/appearance, mame_remapping, samplerate, use_samples /
mips_dynarec / adsp_dynarec / use_alt_sound and brightness.

On a netplay client this turned on the alternate 4-way restrictor and TATE
mode, so with the same inputs a 4-way game ran differently on the client
than on the host (desync). Ports past MAX_PLAYER_COUNT are now ignored.


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude <[email protected]>
 2026-10-24 04:52:48 -04:00
grant2258 2173c6021d llander map thruster too up/down (#2128) 2026-10-23 22:34:30 -04:00
arcadez2003 ab56912e49 Merge pull request #2127 from zanac/ymf271-stereo 
The YMF271 sends its left output to the right speaker and its right output to the left one. This PR swaps them back.
 2026-10-23 23:37:56 +01:00
Claude bf0dc9c8c0 YMF271: left and right outputs were swapped 
The stream channels took the interface volumes in the wrong order:
channel 0 (the chip's left output) got the high 16 bits of
YM3012_VOL, the right one. Regression of #2100: before it the chip
output the same mix on both channels, so the order did not show.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01MEgow1uRCv8pxMErKhmoHZ
 2026-10-23 23:45:22 +02:00
zanacandClaude 03fc843ad8 Namco System 10: MEM(M), MEM(N) and EXIO(G) boards from current MAME (14 sets) (#2125) 
The PSone based board with its ROM boards, from current MAME namcos10.cpp,
ns10crypt.cpp and nandflash.cpp:
- MEM(M): the Intel 28F640J5 flash (new in intelfsh, with the StrataFlash
  write buffer), the mask ROM banks, the type 1 decrypter (Mr. Driller 2)
- MEM(N): the Samsung K9F2808U0B NAND flashes, DMA channel 5, the type 2
  decrypter with the tables of each game
- the scramble of the data and of the boot loader copied to the BIOS space
- the I/O registers (inputs, DIP switches, EXIO ident, I2C, IRQ 10 at 100Hz)
- EXIO(G) without its MCU: the light gun counters of Point Blank 3 and
  Gunbalina
- the PSX DMA can end the GPU linked lists after 500 system clocks as MAME,
  for the drivers that ask for it (the movies of Point Blank 3)

Sets: mrdrilr2, mrdrilr2j, mrdrilr2u, gjspace, knpuzzle, mrdrilrg, chocovdr,
gamshara, gamsharao, panikuru, startrgn, konotako, ptblank3, gunbalina.


Claude-Session: https://claude.ai/code/session_01MEgow1uRCv8pxMErKhmoHZ

Co-authored-by: Claude <[email protected]>
 2026-10-23 15:07:52 -04:00
zanacandClaude 652fd97a6d n8080: Helifire uses 8 bits per gun output (#1150) (#2123) 
The sky and sea gradients of Helifire are 256-level red and blue ramps.
Without VIDEO_NEEDS_6BITS_PER_GUN the core outputs RGB565, so they show
as 32 color bands. The flag makes the core use XRGB8888 for this machine.


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude <[email protected]>
 2026-10-23 12:33:59 -04:00
arcadez2003 b79eb3e9fa Merge pull request #2118 from zanac/taito-gnet 
Taito G-NET: the 39 games of current MAME, PC card games copied into flash, Zoom sound
 2026-10-23 16:16:56 +01:00
arcadez2003 c0de8d54ba Merge pull request #2122 from zanac/asurabus-sets 
Asura Buster: fix repeated sounds (YMF278B key on), sets and DIP switches from current MAME (#911)
 2026-10-23 15:45:56 +01:00
Claude ce92716fca fuukifg3: Asura Buster sets and DIP switches from current MAME, fix repeated sounds (#911) 
Sound: the sound program of Asura Buster and Asura Blade writes the key
on of a PCM slot again about once a second while the sound plays, with
the key already on. The 0.78 YMF278B restarted the sample on every key
on write, so voices and sound effects were repeated. As in current MAME,
the key on bit is now tracked per slot and a sample is only started on
a key off -> key on change. The YMF262 (the FM part of the OPL4) runs at
33.8688MHz / 2.375 = 14260547 Hz, as in MAME 0.143u3.

Sets as in current MAME:
- asurabus: USA set (new, parent)
- asurabusj: Japan set 1 (the set that was `asurabus`)
- asurabusja: Japan set 2 (new)
- asurabusjr: Japan, ARCADIA review build (new); P1 button 4 pauses
  the game, so its inputs have a 4th button per player

DIP switches as in current MAME, for Asura Blade too:
- "Demo Sounds & Music" (SW1:3,4), was two "Unknown" switches
- Difficulty, Damage and Max Rounds labels and defaults fixed: the old
  Max Rounds default ($0040) is shown as "Error" in the service mode
- Coin A/B: 1C_2C to 1C_5C and "2C Start / 1C Continue" added
- DIP locations as comments (the core has no PORT_DIPLOCATION)

Metadata: XML entries from the core's generator, hiscore and catver
entries for the new sets, CHANGELOG.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX
 2026-10-23 15:51:13 +02:00
Claude 453b679c80 Taito G-NET: the 39 games of current MAME (PC card games in flash, Zoom sound) 
New: Intel/Sharp 16-bit flash memories (intelfsh.c), the RF5C296 PC card
controller with the ATA flash card and the three Taito locked cards
(ataflash.c), the G-NET board in zn.c (flash bank, control registers,
COM_DELAY, ZN-2 SPU toggle, the MCU protocol for analog and trackball
inputs, mahjong panel, Mawasunda handles), the Zoom board in flash mode
(samples read from the flashes), CHD metadata (CIS, IDNT, KEY), and a
PC hook in the PSX CPU for the IRQ hack of Space Invaders Anniversary
and Kollon. JP1 "Auto" for the mod BIOS and Compact Flash games.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01MEgow1uRCv8pxMErKhmoHZ
 2026-10-23 13:38:36 +02:00
316 changed files with 114509 additions and 26145 deletions
Expand all files Collapse all files

No files matched your search

.gitignore
+1
View File
@@ -4,5 +4,6 @@
*.exe
*.dll
*.so
*.d
package.json
.npmignore
CHANGELOG.md
+108 -2
View File
@@ -2,7 +2,8 @@
* Current repository maintainers: arcadez, mahoneyt944, markwkidd, twinaphex
* Past repository maintiners: arnoldsecret, grant2258
* Significant code contributors to this project: AMadvanceMAME, BritneysPAIRS, dink, FBN Dev, grant2258, iq_132, MAME Dev, Mistydreams, ShmupMAME
* Significant code contributors to this project: AMadvanceMAME, BritneysPAIRS, dink,
* FBN Dev, grant2258, iq_132, MAME Dev, Mistydreams, ShmupMAME, Zanac, AI agent claude
The list of direct contributors to the MAME 2003-Plus github repository can be found at https://github.com/libretro/mame2003-plus-libretro/graphs/contributors. Additional contributor credits can be found in LICENSE.md, CHANGELOG.old, and in the individual driver source files.
@@ -18,6 +19,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Adventure Canoe
* Air Attack
* Air Rescue
* Akka Arrh (prototype)
* Aladdin (bootleg of Megadrive version)
* Angler Dangler (Deco Cassette)
* Argus (Gottlieb, prototype)
@@ -26,11 +28,14 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Backfire!
* Back Fire (Tecmo)
* Bang Bang Busters
* Bare Knuckle (scrambled bootleg of Mega Drive version) - Romset `barekch` - 6 button pads
* Bare Knuckle II (bootleg of Mega Drive version) - Romset `barek2mb` - its PIC16C57 emulated
* Bare Knuckle II (chinese bootleg of Megadrive version)
* Bare Knuckle III (bootleg of Megadrive version)
* Baryon: Future Assault
* Beastie Feastie (Epos Tristar 9000) - Romset `beastf`; the Pac-Man conversion is now `beastfp`, as in current MAME
* Big Fight - Big Trouble In The Atlantic Ocean
* Bio-Hazard Battle (scrambled bootleg of Mega Drive version) - Romset `biohzdmb`
* Bomb Kick
* Boogie Wings
* Born To Fight
@@ -39,6 +44,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Bubble Bobble 2 - The Return Of Super Drunk (prototype)
* Bubble Buster
* Buccaneers
* Buggy Boy/Speed Buggy (cockpit, rev. D and B), Buggy Boy Junior/Speed Buggy (upright)
* Bullet (unprotected of FD1094 317-0041 set)" )
* Cabal (World, Joystick version)
* Calorie Kun vs Moguranian
@@ -49,6 +55,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Choky! Choky!
* Choutetsu Brikin'ger - iron clad
* Clockwork Aquario
* Columns II: The Voyage Through Time (World) - Romset `columns2`; the old `columns2` (Japan) is now its clone `column2j`, as in current MAME
* Combat Hawk
* Come Back Toto
* Cookie & Bibi
@@ -63,6 +70,8 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Cycle Warriors
* Daikaiju no Gyakushu
* Danger Express (prototype)
* Deathsmiles - Romset `deathsml`
* Deathsmiles MegaBlack Label - Romset `dsmbl`
* Deluxe 5
* Denjin Makai
* Deer Hunting
@@ -70,6 +79,8 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Dice - The Dice Game
* Diet Go Go
* Digger (CVS)
* DoDonPachi Dai-Fukkatsu (Ver 1.5 and 1.0) - Romsets `ddpdfk`, `ddpdfk10`
* DoDonPachi Dai-Fukkatsu Black Label - Romset `dfkbl`
* Dolmen
* Dodge Man
* DoDonPachi Dai-Ou-Jou
@@ -81,6 +92,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Dyna Gear
* Eeekk!
* ESPGaluda
* Espgaluda II (all sets) - Romsets `espgal2`, `espgal2a`, `espgal2b`
* F1 Super Lap (World)
* Fantasy Zone II - The Tears of Opa-Opa (System 16C version)
* Fever SOS
@@ -110,15 +122,19 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Hard Times
* Head On Channel (Japan, Prototype)
* Heavy Smash
* Heavy Unit
* Hoops '96
* Hypernoid
* Hyper Crash
* Hyper Street Fighter II (All Sets)
* Ibara (all sets) - Romsets `ibara`, `ibarao`
* Ibara Kuro Black Label (all sets) - Romsets `ibarablk`, `ibarablka`
* In Your Face
* Inca * Mature *
* Indian Battle
* Invasion
* Jammin (Atari Prototype)
* Jingling Jiazu Genie 2000 - Romset `jingling`
* Joe & Mac Returns
* Jolly Jogger
* Jurassic Park (Bootleg Of Megadrive Version)
@@ -151,11 +167,16 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Monsters World (Bootleg Of Super Pang)
* Monster Maulers
* More More
* Mortal Kombat 3 (scrambled bootleg of Mega Drive version) - Romset `mk3mdb` - 6 button pads
* Mortal Race
* Mouse Shooter GoGo
* Ms. Pacman Twin
* Mrs. Dynamite
* Muchi Muchi Pork! - Romset `mmpork`
* Multi Champ Deluxe * Mature *
* Mushihime-Sama (all sets) - Romsets `mushisam`, `mushisama`, `mushisamb`
* Mushihime-Sama Futari Black Label (all sets) - Romsets `futaribl`, `futariblj`
* Mushihime-Sama Futari Ver 1.5 and 1.0 (all sets) - Romsets `futari15`, `futari15a`, `futari10`
* New Zero Team
* Ninja Kazan
* Oo Parts (Japan, Prototype)
@@ -170,6 +191,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Passing Shot (Japan 2 players)
* Penky
* Photo Y2K 2
* Pink Sweets: Ibara Sorekara (all sets) - Romsets `pinkswts`, `pinkswtsa`, `pinkswtsb`, `pinkswtsx`
* Pirate Treasure
* Planet Probe
* Pochi & Nyaa
@@ -179,9 +201,12 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Power Instinct Matrimelee
* Power Up Baseball
* Progear
* Puckman Pockimon Genie 2000 - Romset `puckpkmn` - the set of current MAME; the old `puckpkmn` set is now its clone `puckpkmnb`, as in current MAME
* Puyo Puyo (World) - Romset `puyo`; the old `puyopuyo`, `puyopuya` and `puyopuyb` are now its clones `puyoj`, `puyoja` and `puyobl`, as in current MAME
* Puzz Loop 2 (All Sets)
* Puzzle Break
* Puzzle Star
* Puzzle! Mushihime-Tama (all sets) - Romsets `mushitam`, `mushitama`
* Puzzli 2
* Puzzli 2 Super
* Quick Shots (Clone Of Target Hits)
@@ -208,10 +233,13 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Sega Megaplay : Streets Of Rage II
* Sega Megaplay : Tecmo World Cup
* Sega Sonic Bros (Japan, Prototype)
* SegaSonic Cosmo Fighter (World and Japan) - Romsets `sonicfgt`, `sonicfgtj`
* SegaSonic Popcorn Shop (Rev B) - Romset `sonicpop` - the popcorn machine itself isn't emulated, as in current MAME
* Sengoku 3
* Shuihu Feng Yun Zhuan
* Skater (Deco Cassette)
* Skull Fang
* Sky Robo / Tatakae! Big Fighter
* Slap Shooter
* Snow Brothers 3 - Magical Adventure
* Snk Vs Capcom : Svc Chaos (MVS)
@@ -219,11 +247,13 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Sonic Boom
* Sonic The Hedgehog 2 (Bootleg Of Megadrive Version)
* Sonic The Hedgehog 3 (Bootleg Of Megadrive Version)
* Soreike! Anpanman Popcorn Koujou (Rev B and Rev A) - Romsets `anpanman`, `anpanmana` - the popcorn machine itself isn't emulated, as in current MAME
* Space Fever High Splitter
* Space Launcher
* Space Raider
* Spectrum 2000 (Euro)
* Squash
* Stack Columns (World) - Romset `stkclmns`; the old `stkclmns` (Japan) is now its clone `stkclmnsj`, as in current MAME
* Stadium Cross (World, linkable) and (US) - Romsets `scrossa`, `scrossu`; `scross` now uses the ROM names of current MAME
* Star Fire 2
* Steel Worker
@@ -233,8 +263,10 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Super Bishi Bashi Championship (ver JAA, 2 Players)
* Super Bubble Bobble (Sun Mixing, Megadrive clone hardware)
* Super Doubles Tennis (Deco Cassette)
* Sunset Riders (scrambled bootleg of Mega Drive version) - Romset `srmdb`
* Super Monaco GP
* Super Rider
* Super Street Fighter II - The New Challengers (scrambled bootleg of Mega Drive version) - Romset `ssf2mdb` - 6 button pads
* Super Trio
* SWAT Police
* Tang Tang
@@ -250,6 +282,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* ThunderForce AC (Japan, prototype, bootleg)
* Top Driving
* Top Roller
* Top Shooter - Romset `topshoot`
* Toppy & Rappy
* Torus * Mature *
* Touch & Go (Korea, unprotected)
@@ -261,14 +294,21 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Turkey Hunting
* Twin Cobra 2
* Twin Action
* Twin Squash - Romset `twinsqua`
* Twinkle
* Twinkle Tale (Bootleg Of Megadrive Version)
* TX-1 (World, Japan rev. B and C)
* Tylz
* Ufo Senshi Yohko Chan
* Varia Metal
* Vasara 2
* Virtua Bowling
* Virtua Fighter
* Waku Waku Anpanman (Rev A and original) - Romsets `wwanpanm`, `wwanpanmo`
* Waku Waku Jumbo (Rev A) - Romset `wwjumbo`
* Waku Waku Marine - Romset `wwmarine`
* Waku Waku Pajero - Romset `wwpajero`
* Waku Waku Sonic Patrol Car - Romset `soniccar`
* Wheels Runner
* Wing Force
* Wing Shooting Championship
@@ -283,15 +323,33 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
## New Clones
* 800 Fathoms (older), Knock Out!! (bootleg, set 2 and set 3), Triple Punch (set 2) - Romsets `800fatha`, `knockoutb`, `knockoutc`, `triplepa`
* Alien Storm (bootlegs of the 3 players and Japan sets) - Romsets `astorm3d`, `astormud`, `astormjd`
* Asura Buster - Eternal Warriors (USA), (Japan, set 2) and (Japan) (ARCADIA review build) - Romsets `asurabus`, `asurabusja`, `asurabusjr`; the Japan set 1 is now `asurabusj`, as in current MAME
* Bare Knuckle III (bootleg of Mega Drive version, alt set, the PIC simulated) - Romset `barek3mba` - not working, as in current MAME
* Bare Knuckle III / Sunset Riders (scrambled bootleg of Mega Drive versions) - Romset `bk3ssrmb` - not working, as in current MAME (only Bare Knuckle III boots)
* Bloxeed (US, C System, Rev A) - Romset `bloxeedu`
* Borench (set 2) and (Japan) - Romsets `borencha`, `borenchj`
* Columns (US, cocktail, Rev A) - Romset `columnsu`
* Print Club (World) and (Japan Vol.3) - Romsets `pclub`, `pclubjv3` - not working (camera and printer), as in current MAME
* Puzzle & Action: Ichidant-R (World) (bootleg) - Romset `ichirbl`
* Puzzle & Action: Tant-R (Japan) (bootleg set 3 and set 4) - Romsets `tantrbl3`, `tantrbl4`
* Ribbit! (Japan) - Romset `ribbitj`
* Sunset Riders / Super Street Fighter II - The New Challengers (scrambled bootleg of Mega Drive versions) - Romset `srssf2mb` - not working, as in current MAME (the order of the ROMs is not known)
* Battle Shark (Japan, Joystick)
* Bloxeed (bootleg) - Romset `bloxeedd`
* Botanic (French version)
* Bubble Bobble (prototype on tokio hardware)
* Calorie Kun vs Moguranian (bootleg)
* Cannon Dancer
* Clutch Hitter (bootlegs) - Romsets `cltchitrd`, `cltchitrjd`
* Competition Golf Final Round (old version) - `compglfo`
* Cotton (bootlegs of the US and Japan sets) - Romsets `cottonud`, `cottonjd`, `cottonjad`
* Crouching Tiger Hidden Dragon 2003
* Crouching Tiger Hidden Dragon 2003 Super Plus
* Crystal Castles (Joystick Version)
* D. D. Crew (bootlegs of the six FD1094 sets) - Romsets `ddcrewd`, `ddcrewud`, `ddcrew1d`, `ddcrew2d`, `ddcrewjd`, `ddcrewj2d`
* Desert Breaker (bootlegs) - Romsets `desertbrd`, `desertbrjd`
* DJ Boy (Japan)
* DoDonPachi Dai-Ou-Jou (Black Label)
* Double Dragon 3 - The Rosetta Stone (Japan)
@@ -305,6 +363,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Gals Panic DX * Mature *
* Ghox (Joystick)
* Ganbare! Gonta!! 2 / Party Time: Gonta the Diver II * Mature *
* Golden Axe II (Mega Play, original revision) - Romset `mp_gaxe2a`
* GunNail (Location Test)
* Guwange Special Version
* Hacha Mecha Fighter (bootleg)
@@ -317,6 +376,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* King of Gladiator
* Knuckle Bash 2
* Kyukyoku Tiger (Japan, 2 Players)
* Laser Ghost (bootlegs) - Romsets `lghostd`, `lghostud`
* Mad Ball V2.0 * Mature * - Romset `madball`
* Magical Drop
* Magical Drop Plus 1
@@ -325,6 +385,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Renegade (US, Bootleg)
* Safari Rally (World) - safarir
* Sexy Parodius (Ver AAA) * Mature *
* Shadow Dancer (World, Japan and US) - Romsets `shdancer`, `shdancerj`, `shdancer1` (were `shdancer`, `shdancrj`, `shdancrb`), now on the System 18 memory mapper and video as in current MAME
* Snk Vs Capcom : Svc Chaos (bootleg)
* Super Bishi Bashi Championship (ver KAA, 3 Players)
* Target Ball * Mature * (Romset `tgtballa`)
@@ -374,6 +435,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Metal Slug 2 - Turbo (Trap15, Hack)
* Midnight Resistance (joystick hack bootleg)
* Mortal Kombat 2 Plus Beta 2
* Pink Sweets: Suicide Club (2017 hack of Pink Sweets) - Romset `pinkswtssc`
* TANK III (joystick hack bootleg)
* The Eye Of The Typhoon (Beta 7)
* Tron freeplay custom rom
@@ -384,6 +446,8 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Agent Super Bond - Romset `superbon` - colors fixed
* Alcon - Romset: `alcon`
* Alien Storm (World and Japan 2 players, World and US 3 players) - Romsets `astorm`, `astormj`, `astorm3`, `astormu` - FD1094 encrypted 68000, Sega System 18
* Bloxeed (Japan, two sets) - Romsets `bloxeed`, `bloxeeda` - FD1094 encrypted 68000, Sega System 18
* Arch Rivals - Romset: `archrivl`
* Avengers In Galactic Storm US - Romset: `avengrgs`
* Avengers In Galactic Storm Japan - Romset: `avengrgsj`
@@ -401,10 +465,14 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Cheeky Mouse - Romset `cheekyms` - colors fixed
* Chouji Meikyuu Legion (ver 1.05) - Romset `legiono`
* Competition Golf Final Round (revision 3) - `compgolf`
* Cotton (World, US, Japan Rev A and Rev B) - Romsets `cotton`, `cottonu`, `cottonj`, `cottonja` - FD1094 encrypted 68000
* Clutch Hitter (US and Japan) - Romsets `cltchitr`, `cltchitrj` - FD1094 encrypted 68000, Sega System 18
* Crater Raider - Romset `crater`
* Crazy Climber 2 - Romset `cclimbr2`
* Dark Edge - Romset `darkedge`
* DD Crew - Romset `ddcrew`
* D. D. Crew (all FD1094 sets: World 2, 3 and 4 players, US, Japan 2 and 4 players) - Romsets `ddcrew`, `ddcrew1`, `ddcrew2`, `ddcrewu`, `ddcrewj`, `ddcrewj2` - Sega System 18, as in current MAME
* Desert Breaker (World and Japan) - Romsets `desertbr`, `desertbrj` - FD1094 encrypted 68000, Sega System 18
* Demolition Derby - Romset `demoderb`
* Die Hard Arcade - Romset `diehard` - Requires a fast system; video and sound issues remain
* Discs Of Tron - Romsets `dotron` and `dotrone`
@@ -446,6 +514,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Kick - Romset `kick`
* Kick'N Run- Romset `kicknrun`
* Kozmik Kroozr - Romset `kroozr`
* Laser Ghost (World, US and Japan) - Romsets `lghost`, `lghostu`, `lghostj` - FD1094 encrypted 68000, Sega System 18, light guns
* Legion (ver 2.03) - Romset `legion`
* Macho Mouse - Romset `machomou` - colors fixed
* Mario's Open Golf (Playchoice 10) - Romset `pc_moglf`
@@ -479,6 +548,15 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Satan's Hollow - Romset `shollow`
* Sega Megaplay : Golden Axe II - Romset `mp_gaxe2`
* Sega Megaplay : Sonic The Hedgehog - Romset `mp_sonic`
* Sega Mega-Tech : After Burner - Romset `mt_aftrb` - SMS based
* Sega Mega-Tech : Astro Warrior - Romset `mt_astro` - SMS based
* Sega Mega-Tech : Bonanza Bros. - Romset `mt_bbros` - the good dump of current MAME
* Sega Mega-Tech : Ghouls'n Ghosts - Romset `mt_gng` - the good dump of current MAME
* Sega Mega-Tech : Golden Axe II - Romset `mt_gaxe2`
* Sega Mega-Tech : Great Golf - Romset `mt_ggolf` - SMS based, the good dump of current MAME
* Sega Mega-Tech : Parlour Games - Romset `mt_parlg` - SMS based
* Sega Mega-Tech : Shinobi - Romset `mt_shnbi` - SMS based
* Sega Mega-Tech : Tetris - Romset `mt_tetri` - the good dump of current MAME
* Shisensho II * Mature * - Romset `shisen2`
* Shogun Warriors - Romset `shogwarr`
* Shrike Avenger - Romset `shrike`
@@ -487,6 +565,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Slipstream - Romset `slipstrm`
* Snowboard Championship - Romset `snowboar`
* Solar Fox - Romset `solarfox`
* Songjiangyanyi Final - Romset `songjang` - the Mega Drive board of current MAME, the HBLANK status it waits for
* Space Position - Romset `spcpostn`
* Space Seeker - Romset `spaceskr`
* Speed Spin - Romset `speedspn` - gfx glitches
@@ -515,6 +594,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Under Fire - Romset `undrfire`
* U.S. Classic - Romset `usclssic` - colors fixed
* VS. Hot Smash - `hotsmash`
* Wally wo Sagase! (rev A and B, 2 and 3 players) - Romsets `wwallyj`, `wwallyja`, `wwallyja3p` - FD1094 encrypted 68000, Sega System 18, trackballs
* Wonder Boy in Monster Land (Japan New Ver.) - Romset `wbml`
* Wonder Boy in Monster Land (Japan Old Ver.) - Romset `wbmljo`
* Xenophobe - Romset `xenophob`
@@ -584,10 +664,12 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
## Games now with improved sound
* 800 Fathoms, Knock Out!!, Mariner, Triple Punch: AY-8910 clock of current MAME (1.536 MHz, verified on hardware), the sound was 16% too high and too fast
* 1945kIII
* Air Buster
* Ashita no Joe
* Asterix
* Asura Blade, Asura Buster (no more repeated voices and sound effects)
* Athena
* Bandito
* Big Event Golf
@@ -705,6 +787,8 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
## New and/or Recommended Input Options and Settings
* Ikari (joystick hack bootleg): dual stick aiming. Set the 'Aim with Right Stick' DIP switch to On (Tab menu, Dip Switches): the player walks with the left stick and aims and fires with the right stick; with the right stick released he fires where he walks, as before. Off by default.
* Added 'X-Way Joystick' Option to Analog Controls Menu only for IPT_DIAL and IPT_DIAL_V devices. This option is for use with x-way rotary joysticks (where the joystick can rotate X discrete steps, 8 or 12 appears to be most common). The joystick can still move up, down, left, right and diagonally. The most famous game to use this control scheme is Ikari Warriors.
Notes on this option:
- When on, prevents the character from rotating two discrete steps sometimes when the rotary joystick is just rotated one step.
@@ -778,6 +862,24 @@ Notes on this option:
## Misc Changes
* Save states (RunAhead, netplay) of the Galaxian/Scramble/Frogger hardware: Galaxian video (stars, flip, banks, background), the 7474 flip-flops, the Scramble sound RAM and timer, the RC filters of the sound streams, the global sound enable
* Sega System 18: all the games on the 315-5195 memory mapper, the segaic16 video and the VDP layer as in current MAME (171-5874, 171-5987 and Shadow Dancer ROM boards, FD1094 sets, Laser Ghost light guns, Wally wo Sagase! trackballs); the old `astorm` and `astorm2p` are now `astormj` and `astorm`
* Sega Mega Drive VDP (315-5313): now a module of its own (`vidhrdw/segavdp.c`), started with its own configuration by System C/C2, Mega-Tech, Mega Play, the Mega Drive bootlegs and System 18, so a change for one board no longer reaches the others; a game loaded after a Mega Play game in the same session no longer inherits its interrupt mode (e.g. Columns attract out of sync), and the VDP window position and VBLANK flag are in the save states
* Sega Mega Play: its own driver (`drivers/megaplay.c`, as in current MAME), the Mega Drive part shared with the other Mega Drive based boards; Tecmo World Cup is now `mp_twcup` and the BIOS version 2 ROM `epr-a15294.ic2`, as in current MAME
* Sega Mega-Tech: its own driver (`drivers/megatech.c`, as in current MAME), sets, ROMs and names as in current MAME (good dumps of `mt_bbros`, `mt_ggolf`, `mt_gng`, `mt_tetri`, the instruction ROMs in the cart at 0x300000); the Master System carts now run, on the Mega Drive in Mark III mode as in current MAME (the VDP in mode 4, the Z80 with the Sega mapper); the BIOS cart slots as in current MAME (the menu lists the one cart in slot 1, the slot RAM, the window into the cart), the BIOS display in its 224 line mode (the MENU title was cut) and drawn line by line; the Mega Drive VDP line timing and partial updates now count its own lines below the BIOS screen (they used the scanlines of the double screen); the 68000 writes to 0xa02000 of the boards without the Mega Play BIOS no longer go through a NULL pointer (Great Golf and Great Soccer crashed)
* Sega Mega Play: the BIOS overlay is transparent on colour 0 of both its palettes and covers its borders, as in current MAME (the boot logo screen was hidden behind a green background)
* Sega Mega Drive based bootlegs: their own driver (`drivers/megadriv_acbl.c`, as in current MAME), with the board variants of current MAME (the 6 button pads, the DIP switches at 0x770070 of the scrambled boards, the 3rd I/O port coins, the PIC16C57 of `barek2mb`); the new sets take their V-INT / H-INT through the VDP interrupt enables as on the real hardware (Mortal Kombat 3 crashed at boot), the descrambling of the bootlegs and the PIC of `barek2mb` now also work on big-endian hosts
* Genie / Y-BOX and Sun Mixing boards: their own drivers (`drivers/megadriv_ybox.c`, `drivers/megadriv_sunmix.c`, as in current MAME); the Y-BOX games run on the Mega Drive machine as in MAME (Z80, I/O, the VDP interrupts and HBLANK as on the real hardware), with the protection read back latches and the ROM address remapping of Shuihu Feng Yun Zhuan of current MAME
* Sega System C/C2: `drivers/segac2.c` now has only System C/C2, the Mega Drive part shared by the other boards is in `machine/megadriv.c` (as `megadriv.cpp` in current MAME); the sets, ROMs, titles, inputs and DIP switches as in current MAME; the protection chip as the EPM5032 logic of each game of current MAME (no more Ribbit! and Puyo Puyo 2 workarounds and fake tables, Print Club Vol.2, 4 and 5 now get past the protection); the alternate palette mode of Ribbit! and Twin Squash (instead of the palette address watching of Ribbit!); the 68000 at 8.95 MHz and the 59.92 Hz refresh as in current MAME (it ran at 7.67 MHz and 60 Hz: the games now follow the timing of MAME frame for frame), the V-INT and H-INT held until the 68000 takes them as on the board, the address mirrors, the battery-backed work RAM (high scores kept, as in current MAME) and the coin meters on the I/O chip
* YM2612 / YM3438: the busy flag after a data write (192 clocks, as in current MAME), and a timer started long after its last overflow runs a whole period instead of firing at once (Thunder Force AC, Bloxeed and the other System C2 games follow MAME again)
* Sega Mega Play: the V-INT of the BIOS VDP comes about 12 lines after the Mega Drive VBLANK, as in current MAME (it came ~80 lines early, and the BIOS/game handshake on port C could miss: Tecmo World Cup stayed on a black screen)
* Sega Mega Play / System E: the tiles of the SMS-type VDP are read byte by byte, so they are drawn right on big-endian hosts (the Mega Play BIOS screen had the wrong colours)
* Sega Mega Drive VDP: in H32 mode the sprite table base uses bit 0 of register 5, as on the real VDP (the fighters of Super Street Fighter II were missing, the sprites of Bonanza Bros. on Mega-Tech were garbled)
* PIC16C5x CPU core: the program counter wraps at the end of the program memory (the 2K parts start at 0x7ff and ran past the ROM), and the save states no longer register the ports and STATUS through a NULL pointer (the save of a game with a PIC crashed); these are in the data RAM, saved with the CPU memory
* Save states (netplay, RunAhead with a second instance) of the Mega Drive based boards: the Z80 RAM and bus state and the Mega-Tech / Mega Play BIOS registers and RAM are saved (Gunstar Heroes and Mazin Wars Mega Play went out of sync after loading a state in a new instance); the SN76496 PSG is saved, and the YM2612 DAC enable is restored from its own register (0x2b, it was read from 0x2d)
* Sega System 18 (also Moonwalker): the VDP palette writes no longer overflow the System 16 palette RAM (they corrupted the memory after it, e.g. garbled graphics in Shadow Dancer), and the sprite shadows over the VDP layer no longer index past the palette
* Save states (RunAhead, netplay) of the Sega System 18 hardware: the RF5C68 PCM, the YM2612/YM3438 envelope, LFO, frequency and timer state, the VDP layer, the sound ROM bank
* Save states (RunAhead, netplay) of the Sega System 16B hardware: the uPD7759 ADPCM chip, the sound CPU ROM bank, the segaic16 tilemap and sprite banks, flip, scroll latches and display enable
* Added HD647180 MCU sound support for Fire Shark and Vimana [arcadez]
* Added sound sample support for Cosmic Alien [BritneysPAIRS, arcadez]
* Updated sample support for Donkey Kong and Donkey kong JR to MAME87 [BritneysPAIRS, arcadez]
@@ -1183,4 +1285,8 @@ could crash on the score calc between levels is sorted [amadvance, arcadez]
* Fixed Palette banking problems for Pleiads [MAMEDev, arcadez]
* Added fixes from later MAME so that Princess Clara Daisakusen now works [MAMEDev, arcadez]
* Ported a new raiden2.c driver Raiden II Raiden DX and Zero Team etc etc now playable [Salvia, MAMEDev, FBN, vanni and claude, arcadez]
* Ported the Cave CV1000 driver from current MAME: SH-3 CPU (interpreter and a recompiler with the same results), the blitter, the YMZ770 sound chip, the NAND flash and the RTC9701 [MAMEDev, vanni and claude]
* Added support for the hvyunit.c driver ported across from my xbox project [arcadez, mistydreams, vanni and claude]
* Added Sky Robo / Tatakae! Big Fighter to armedf.c and hooked it up to the new mcs51 cpu
[arcadez, grant2258, AdvanceMAME, Zanac]
* Ported a driver for Atari's Akka Arrh across from AdvanceMAME [arcadez, AdvanceMAME]
Makefile
+44 -1
View File
@@ -100,7 +100,9 @@ endif
ifeq ($(platform), unix)
TARGET = $(TARGET_NAME)_libretro.so
fpic = -fPIC
CFLAGS += $(fpic)
# only the retro_* entry points (RETRO_API) leave the library: the rest is
# reached directly instead of through the GOT and PLT
CFLAGS += $(fpic) -fvisibility=hidden
LDFLAGS += $(fpic) -shared -Wl,--version-script=link.T
# Linux Portable
@@ -828,6 +830,14 @@ ifeq (,$(findstring msvc,$(platform)))
CFLAGS += -Werror=vla -Werror=declaration-after-statement
endif
# no fused multiply-add: a*b+c rounded once (FMA) on AArch64, ARMv7 VFPv4
# and PowerPC gives other results than x86, where it is rounded twice;
# with it off the floating point results are the same on every host
# (netplay between them, save states and RunAhead)
ifeq (,$(findstring msvc,$(platform)))
CFLAGS += -ffp-contract=off
endif
# Required for RZIP support in cheat.c
CFLAGS += -DHAVE_ZLIB
@@ -864,6 +874,24 @@ ifeq ($(HAVE_ARMv6),1)
CFLAGS += -DHAVE_ARMv6
endif
# threads (libretro-common rthreads), as the other libretro cores do (beetle-psx):
# on by default, off where there is no thread library, and on the MSVC builds
# (the ST-V threaded video needs MSVC 2015's thread-local storage, the
# buildbot's MSVC lanes are 2005 and 2010: nothing would use the threads)
HAVE_THREADS ?= 1
ifneq (,$(filter $(platform), emscripten linux-portable ngc wii wiiu ps2 ps3 psl1ght psp1 ctr vita))
HAVE_THREADS = 0
endif
ifneq (,$(findstring msvc,$(platform)))
HAVE_THREADS = 0
endif
ifeq ($(HAVE_THREADS),1)
# pthreads are in the C library on Darwin and Android, Windows uses its own threads
ifeq (,$(findstring msvc,$(platform))$(findstring android,$(platform))$(findstring ios,$(platform))$(findstring tvos,$(platform))$(filter osx win,$(platform)))
LIBS += -lpthread
endif
endif
# include the various .mak files
ifneq (,$(filter $(INCLUDE_DRV),all))
include Makefile.common
@@ -948,3 +976,18 @@ ifeq ($(SPLIT_UP_LINK), 1)
@rm $@.in
endif
$(HIDE)rm -f $(OBJECTS) $(TARGET)
# 1. Map object files to dependency trackers
DEPFILES := $(OBJECTS:.o=.d)
# 2. ONLY read or handle dependencies if we are NOT running a clean command
ifneq ($(MAKECMDGOALS),clean)
-include $(DEPFILES)
# 3. FIXED: Generate a pure, clean dependency file directly using the -MM flag
%.d: %.c
@echo "Generating dependency tracker for $<..."
$(HIDE)$(CC) -MM -MP -MT $(@:.d=.o) -MF $@ $< $(CFLAGS)
# 4. Fallback stub to prevent build errors if a header file is deleted
$(DEPFILES):
endif
Makefile.common
+59 -4
View File
@@ -69,6 +69,7 @@ SOURCES_C += \
SOURCES_C += \
$(CORE_DIR)/machine/fd1089.c \
$(CORE_DIR)/machine/fd1094.c \
$(CORE_DIR)/machine/6522via.c \
$(CORE_DIR)/machine/6532riot.c \
$(CORE_DIR)/machine/6821pia.c \
@@ -79,6 +80,9 @@ SOURCES_C += \
$(CORE_DIR)/machine/8255ppi.c \
$(CORE_DIR)/machine/eeprom.c \
$(CORE_DIR)/machine/idectrl.c \
$(CORE_DIR)/machine/intelfsh.c \
$(CORE_DIR)/machine/ds2404.c \
$(CORE_DIR)/machine/ataflash.c \
$(CORE_DIR)/machine/mathbox.c \
$(CORE_DIR)/machine/mb87078.c \
$(CORE_DIR)/machine/random.c \
@@ -127,6 +131,7 @@ CPUS+=I186@
CPUS+=V20@
CPUS+=V30@
CPUS+=V33@
CPUS+=V25@
CPUS+=V60@
CPUS+=V70@
CPUS+=I8035@
@@ -167,6 +172,7 @@ CPUS+=TMS9995@
CPUS+=Z8000@
CPUS+=TMS32010@
CPUS+=TMS32025@
CPUS+=NAMCOC71@
CPUS+=TMS32031@
CPUS+=I960@
CPUS+=MB86233@
@@ -181,6 +187,7 @@ CPUS+=ADSP2115@
CPUS+=ADSP2181@
CPUS+=PSXCPU@
CPUS+=H83002@
CPUS+=I386@
CPUS+=MN10200@
CPUS+=M37702@
CPUS+=ASAP@
@@ -193,6 +200,7 @@ CPUS+=R3000@
CPUS+=R4600@
CPUS+=R5000@
CPUS+=SH2@
CPUS+=SH3@
CPUS+=DSP32C@
#CPUS+=PIC16C54@
CPUS+=PIC16C55@
@@ -492,7 +500,7 @@ SOURCES_C += \
$(CORE_DIR)/vidhrdw/mitchell_vidhrdw.c $(CORE_DIR)/drivers/mitchell.c \
$(CORE_DIR)/vidhrdw/cbasebal_vidhrdw.c $(CORE_DIR)/drivers/cbasebal.c \
$(CORE_DIR)/vidhrdw/cps1_vidhrdw.c $(CORE_DIR)/drivers/cps1.c $(CORE_DIR)/drivers/cps2.c $(CORE_DIR)/machine/cps2crypt.c\
$(CORE_DIR)/drivers/zn.c $(CORE_DIR)/sndhrdw/taitozoom.c $(CORE_DIR)/sound/zsg2.c $(CORE_DIR)/cpu/tms57002/tms57002.c \
$(CORE_DIR)/drivers/zn.c $(CORE_DIR)/sndhrdw/acclaim_rax.c $(CORE_DIR)/sndhrdw/taitozoom.c $(CORE_DIR)/sound/zsg2.c $(CORE_DIR)/cpu/tms57002/tms57002.c \
$(CORE_DIR)/drivers/cps3.c $(CORE_DIR)/sndhrdw/cps3_sndhrdw.c \
$(CORE_DIR)/vidhrdw/tms34061_vidhrdw.c \
$(CORE_DIR)/machine/capbowl_machine.c $(CORE_DIR)/vidhrdw/capbowl_vidhrdw.c $(CORE_DIR)/drivers/capbowl.c \
@@ -522,10 +530,10 @@ SOURCES_C += \
$(CORE_DIR)/drivers/system24.c $(CORE_DIR)/machine/system24_machine.c $(CORE_DIR)/vidhrdw/system24_vidhrdw.c \
$(CORE_DIR)/vidhrdw/segaic24.c $(CORE_DIR)/vidhrdw/segas18.c \
$(CORE_DIR)/drivers/segas32.c $(CORE_DIR)/machine/segas32.c $(CORE_DIR)/vidhrdw/segas32.c \
$(CORE_DIR)/vidhrdw/segac2_vidhrdw.c $(CORE_DIR)/drivers/segac2.c \
$(CORE_DIR)/vidhrdw/segavdp.c $(CORE_DIR)/vidhrdw/segac2_vidhrdw.c $(CORE_DIR)/machine/megadriv.c $(CORE_DIR)/drivers/segac2.c $(CORE_DIR)/drivers/megaplay.c $(CORE_DIR)/drivers/megatech.c $(CORE_DIR)/drivers/megadriv_acbl.c $(CORE_DIR)/drivers/megadriv_ybox.c $(CORE_DIR)/drivers/megadriv_sunmix.c \
$(CORE_DIR)/drivers/stv.c $(CORE_DIR)/drivers/stvhacks.c $(CORE_DIR)/machine/stvcd.c \
$(CORE_DIR)/machine/scudsp.c \
$(CORE_DIR)/vidhrdw/stvvdp1_vidhrdw.c $(CORE_DIR)/vidhrdw/stvvdp2_vidhrdw.c \
$(CORE_DIR)/vidhrdw/stvvid.c \
$(CORE_DIR)/vidhrdw/deniam_vidhrdw.c $(CORE_DIR)/drivers/deniam.c \
$(CORE_DIR)/machine/btime_machine.c $(CORE_DIR)/vidhrdw/btime_vidhrdw.c $(CORE_DIR)/drivers/btime.c \
$(CORE_DIR)/machine/decocass_machine.c $(CORE_DIR)/vidhrdw/decocass_vidhrdw.c $(CORE_DIR)/drivers/decocass.c \
@@ -817,6 +825,7 @@ SOURCES_C += \
$(CORE_DIR)/vidhrdw/raiden_vidhrdw.c $(CORE_DIR)/drivers/raiden.c $(CORE_DIR)/drivers/raiden2.c \
$(CORE_DIR)/vidhrdw/dcon_vidhrdw.c $(CORE_DIR)/drivers/dcon.c \
$(CORE_DIR)/vidhrdw/sengokmj_vidhrdw.c $(CORE_DIR)/drivers/sengokmj.c \
$(CORE_DIR)/machine/seibuspi_machine.c $(CORE_DIR)/vidhrdw/seibuspi_vidhrdw.c $(CORE_DIR)/drivers/seibuspi.c \
$(CORE_DIR)/sndhrdw/t5182.c \
$(CORE_DIR)/vidhrdw/mustache_vidhrdw.c $(CORE_DIR)/drivers/mustache.c \
$(CORE_DIR)/vidhrdw/darkmist_vidhrdw.c $(CORE_DIR)/drivers/darkmist.c \
@@ -1056,11 +1065,15 @@ SOURCES_C += \
$(CORE_DIR)/machine/model1_machine.c $(CORE_DIR)/vidhrdw/model1_vidhrdw.c $(CORE_DIR)/drivers/model1.c \
$(CORE_DIR)/machine/model2_machine.c $(CORE_DIR)/vidhrdw/model2_vidhrdw.c $(CORE_DIR)/drivers/model2.c \
$(CORE_DIR)/sndhrdw/segadsb.c $(CORE_DIR)/sound/mpeg_audio.c \
$(CORE_DIR)/drivers/cv1k.c $(CORE_DIR)/vidhrdw/cv1k_vidhrdw.c $(CORE_DIR)/sound/ymz770.c \
$(CORE_DIR)/machine/sega315_5881.c $(CORE_DIR)/machine/sega315_5838.c \
$(CORE_DIR)/drivers/calorie.c \
$(CORE_DIR)/drivers/hvyunit.c \
$(CORE_DIR)/drivers/akkaarrh.c \
$(CORE_DIR)/machine/mc8123.c \
$(CORE_DIR)/machine/namcoio_machine.c \
$(CORE_DIR)/drivers/tatsumi.c $(CORE_DIR)/vidhrdw/tatsumi.c $(CORE_DIR)/machine/tatsumi.c
$(CORE_DIR)/drivers/tatsumi.c $(CORE_DIR)/vidhrdw/tatsumi.c $(CORE_DIR)/machine/tatsumi.c \
$(CORE_DIR)/drivers/tx1.c $(CORE_DIR)/vidhrdw/tx1_vidhrdw.c $(CORE_DIR)/machine/tx1_machine.c $(CORE_DIR)/sndhrdw/tx1_sndhrdw.c
@@ -1371,6 +1384,15 @@ else
CPUDEFS += -DHAS_V33=0
endif
CPU=$(strip $(findstring V25@,$(CPUS)))
ifneq ($(CPU),)
OBJDIRS += $(CORE_DIR)/cpu/nec
CPUDEFS += -DHAS_V25=1
SOURCES_C += $(CORE_DIR)/cpu/nec/v25.c
else
CPUDEFS += -DHAS_V25=0
endif
ifeq ($(HAS_V30),1)
SOURCES_C += $(CORE_DIR)/cpu/nec/nec.c
ifeq ($(DEBUGGER),1)
@@ -1845,6 +1867,15 @@ else
CPUDEFS += -DHAS_TMS32010=0
endif
CPU=$(strip $(findstring NAMCOC71@,$(CPUS)))
ifneq ($(CPU),)
OBJDIRS += $(CORE_DIR)/cpu/namcoc71
CPUDEFS += -DHAS_NAMCOC71=1
SOURCES_C += $(CORE_DIR)/cpu/namcoc71/c71.c
else
CPUDEFS += -DHAS_NAMCOC71=0
endif
CPU=$(strip $(findstring TMS32025@,$(CPUS)))
ifneq ($(CPU),)
OBJDIRS += $(CORE_DIR)/cpu/tms32025
@@ -1939,6 +1970,15 @@ else
CPUDEFS += -DHAS_H83002=0
endif
CPU=$(strip $(findstring I386@,$(CPUS)))
ifneq ($(CPU),)
OBJDIRS += $(CORE_DIR)/cpu/i386
CPUDEFS += -DHAS_I386=1
SOURCES_C += $(CORE_DIR)/cpu/i386/i386.c
else
CPUDEFS += -DHAS_I386=0
endif
CPU=$(strip $(findstring MN10200@,$(CPUS)))
ifneq ($(CPU),)
OBJDIRS += $(CORE_DIR)/cpu/mn10200
@@ -2079,6 +2119,15 @@ else
CPUDEFS += -DHAS_SH2=0
endif
CPU=$(strip $(findstring SH3@,$(CPUS)))
ifneq ($(CPU),)
OBJDIRS += $(CORE_DIR)/cpu/sh3
CPUDEFS += -DHAS_SH3=1
SOURCES_C += $(CORE_DIR)/cpu/sh3/sh3.c
else
CPUDEFS += -DHAS_SH3=0
endif
CPU=$(strip $(findstring DSP32C@,$(CPUS)))
ifneq ($(CPU),)
OBJDIRS += $(CORE_DIR)/cpu/dsp32
@@ -2814,6 +2863,12 @@ SOURCES_C += \
# sljit: run-time code generator of the MIPS recompilers (empty where they are not supported)
SOURCES_C += $(CORE_DIR)/lib/sljit/sljit_mame.c
# threads (libretro-common rthreads, set by the platform: see Makefile): the ST-V threaded video option
ifeq ($(HAVE_THREADS),1)
COREDEFINES += -DHAVE_THREADS
SOURCES_C += $(LIBRETRO_COMM_DIR)/rthreads/rthreads.c
endif
ifeq ($(STATIC_LINKING),1)
else
SOURCES_C += \
Makefile.split
+19
View File
@@ -69,6 +69,7 @@ SOURCES_C += \
SOURCES_C += \
$(CORE_DIR)/machine/fd1089.c \
$(CORE_DIR)/machine/fd1094.c \
$(CORE_DIR)/machine/6522via.c \
$(CORE_DIR)/machine/6532riot.c \
$(CORE_DIR)/machine/6821pia.c \
@@ -1337,6 +1338,15 @@ else
CPUDEFS += -DHAS_V33=0
endif
CPU=$(strip $(findstring V25@,$(CPUS)))
ifneq ($(CPU),)
OBJDIRS += $(CORE_DIR)/cpu/nec
CPUDEFS += -DHAS_V25=1
SOURCES_C += $(CORE_DIR)/cpu/nec/v25.c
else
CPUDEFS += -DHAS_V25=0
endif
ifeq ($(HAS_V30),1)
SOURCES_C += $(CORE_DIR)/cpu/nec/nec.c
ifeq ($(DEBUGGER),1)
@@ -1811,6 +1821,15 @@ else
CPUDEFS += -DHAS_TMS32010=0
endif
CPU=$(strip $(findstring NAMCOC71@,$(CPUS)))
ifneq ($(CPU),)
OBJDIRS += $(CORE_DIR)/cpu/namcoc71
CPUDEFS += -DHAS_NAMCOC71=1
SOURCES_C += $(CORE_DIR)/cpu/namcoc71/c71.c
else
CPUDEFS += -DHAS_NAMCOC71=0
endif
CPU=$(strip $(findstring TMS32025@,$(CPUS)))
ifneq ($(CPU),)
OBJDIRS += $(CORE_DIR)/cpu/tms32025
docs/cave-cv1000.md
+119
View File
@@ -0,0 +1,119 @@
# Cave CV1000: how the driver works and where it differs from MAME
Sets (MAME's list without the touch screen mahjong game `mmmbanc`):
| Board | Sets |
|---|---|
| CV1000-B (8 MB RAM) | `mushisam`, `mushisama`, `mushisamb`, `ibara`, `ibarao`, `ibarablk`, `ibarablka`, `espgal2`, `espgal2a`, `espgal2b`, `mushitam`, `mushitama`, `pinkswts`, `pinkswtsa`, `pinkswtsb`, `pinkswtsx`, `pinkswtssc`, `futari15`, `futari15a`, `futari10`, `futaribl`, `futariblj`, `mmpork`, `deathsml` |
| CV1000-D (16 MB RAM) | `dsmbl`, `ddpdfk`, `ddpdfk10`, `dfkbl` |
`futaribl` is the World / English set; the others are Japanese.
Files:
- `src/cpu/sh3/sh3.c`: the SH-3 (SH7709S) CPU and its peripherals.
- `src/cpu/sh3/sh3jit.c`: the SH-3 recompiler, included by `sh3.c`.
- `src/drivers/cv1k.c`: memory maps, NAND flash, RTC9701, inputs, sets.
- `src/vidhrdw/cv1k_vidhrdw.c`: the blitter (Cave's EPIC12 FPGA).
- `src/sound/ymz770.c`: the Yamaha YMZ770 ("AMM"), on `src/sound/mpeg_audio.c`.
All are C89 ports of current MAME (`sh.cpp`, `sh3comn.cpp`, `sh4*.cpp`,
`cv1k.cpp`, `epic12*.cpp`, `ymz770.cpp`).
## The board
- Hitachi SH7709S, an SH-3 at 102.4 MHz, big-endian, no FPU. The boot code
copies the game from the NAND flash to work RAM and runs it from there.
- The blitter: copies sprites from an 8192 x 4096 VRAM to the screen with
flips, tint, transparency and 8 source and 8 destination blend modes, and
uploads graphics to VRAM. The games wait on it.
- The YMZ770: 16 channels of compressed audio from two 4 MB flash chips,
and a sequencer.
- 128 MB NAND flash with the graphics and data, a NOR flash with the boot
code, the RTC9701 with its EEPROM (settings and high scores).
## CPU
The interpreter follows current MAME's SH-3 instruction by instruction,
with the cycle counts of MAME's recompiler (MAME only runs the SH-3 with its
recompiler) and MAME's SH7709S cache and bus timing model: every data access
goes through a model of the 16 KB cache, the write-back, the burst fills and
the wait states of each bus area. The games' speed (and their slowdowns)
depends on it.
Peripherals: the interrupt controller, the three timers (TMU), the DMA
controller (the transfer at once, the end interrupt after the transfer
time, as MAME), the I/O ports (inputs, NAND control, RTC serial line), the
cache address array. The timers run on the machine time, as in MAME.
## Recompiler
Core option "SH-3 Dynarec" (enabled by default; offered for these games
only, on the hosts where it runs: x86, x86-64, ARMv7, AArch64, except the
systems that forbid run-time code generation). Big-endian hosts use the
interpreter.
It gives the same results as the interpreter, cycle for cycle: a saved
state is the same with and without it, so netplay, save states and RunAhead
don't depend on it.
- Straight runs of instructions, up to an unconditional branch and its
delay slot, become native code (sljit, as the MIPS and ADSP recompilers
of this core). Conditional branches leave the block or loop inside it.
- The timeslice is checked before every instruction, as the interpreter's
loop does; the cycles are taken in the interpreter's order around the
memory accesses and the bus timing.
- Loads and stores compute their address natively and call the
interpreter's accessors (memory handlers, cache and bus timing). The
instructions without native code call the interpreter for that
instruction.
- The block leaves when an interrupt becomes pending or a write touches
translated code. Writes over translated code (CPU stores, DMA) and state
loads flush the translations.
## Speedups
As in MAME, each game has an idle loop speedup: the read of the variable the
game polls in its wait loop skips 10 us of CPU time. The loop reads it in
the delay slot of its branch; MAME's recompiler reports there the PC it
stored two bytes after the loop start, so it skips on every pass; this
driver does the same with the delay slot's own PC.
MAME suspends the CPU for those 10 us. This core's scheduler doesn't give
the time back to a CPU resumed in the timeslice that suspended it, so the
CPU would fall further behind on every pass: the 10 us are eaten from the
timeslice instead (1024 cycles), with the same effect.
## Video
The VRAM is kept as 16-bit pixels (the 5-5-5 colour and the transparency
bit), 64 MB instead of MAME's 128 MB of 32-bit pixels; the blits work on
the same values as MAME's. The blitter runs at once when started, and is
busy for the time MAME computes for that blit (the games read the busy
flag). MAME can run it in a separate thread; this core doesn't.
## Sound
The YMZ770 decodes MAME's AMM variant of MPEG audio, added to
`mpeg_audio.c` next to layers I and II (used by the Sega DSB), which are
unchanged.
## NAND flash, RTC, NVRAM
- The NAND is read with its spare area and bad block table through the
flash interface and port E (busy for 25 us after a page read).
- The RTC9701 is set from the host clock at start, as MAME does.
- NVRAM: the RTC EEPROM, and the NAND blocks the game erased or programmed
(only those, not the 128 MB).
## Save states
Every part has its state saved (CPU, peripherals, cache model, blitter
and VRAM, YMZ770, NAND, RTC). A state is about 77 MB with the VRAM (85 MB on
CV1000-D). Tested: a save and load on every frame (RunAhead-like) gives the
same frames, audio and state as a run without them.
## Not done
- `mmmbanc` (Medal Mahjong Moukari Bancho), a touch screen game.
- Akai Katana and DoDonPachi SaiDaiOuJou: commented out in MAME too.
docs/sega-model2.md
+16
View File
@@ -153,6 +153,22 @@ in ROM, so the interrupt was lost and the main loop waited for the timer
forever (black screen after "STAND ALONE"). With 32 bytes the commands fit
and the game plays.
**The MIDI interrupt.** The sound program reads one byte from the queue per
MIDI interrupt (level 3 on these boards). The interrupt is now dropped when
the program reads the byte, and raised again only while the queue still has
bytes, as in current MAME. Before, it could stay raised on an empty queue:
the sound program then took it again and read a stale byte as part of a
command. This corrupted the music commands of Dead or Alive (61 extra reads
in the attract mode) and Manx TT (189), whose music then played wrong or
stopped. The SCSP timers are now real timers, as in MAME, and each interrupt
source has its own level, which stays raised until the program acknowledges
it.
**How it was checked.** Each sound command the i960 sends is read once, with
no extra reads, in `doa`, `fvipers`, `hotd`, `manxtt`, `rchase2`, `srallyc`
and `vf2`. In Dead or Alive the sound commands and every slot register write
between 15 and 25 s of the attract mode are the same as in MAME 0.264.
## Rail Chase 2: mirrored sample ROMs
Sets: `rchase2`.
jni/Android.mk
+3
View File
@@ -3,6 +3,9 @@ LOCAL_PATH := $(call my-dir)
ROOT_DIR := $(LOCAL_PATH)/..
CORE_DIR := $(ROOT_DIR)/src
# threads: in bionic's C library
HAVE_THREADS := 1
include $(ROOT_DIR)/Makefile.common
COREFLAGS := $(DEFS) $(COREDEFINES) $(CPUDEFS) $(SOUNDDEFS) $(ASMDEFS) $(DBGDEFS) -ffast-math -funroll-loops -DANDROID -DHAVE_ZLIB $(INCFLAGS)
metadata/catver.ini
+110 -8
View File
@@ -34,6 +34,34 @@
3stooges=Shooter / Field
3wonders=MultiGame / Compilation
3wonderu=MultiGame / Compilation
ddpdfk=Shooter / Flying Vertical
ddpdfk10=Shooter / Flying Vertical
deathsml=Shooter / Flying Horizontal
dfkbl=Shooter / Flying Vertical
dsmbl=Shooter / Flying Horizontal
espgal2=Shooter / Flying Vertical
espgal2a=Shooter / Flying Vertical
espgal2b=Shooter / Flying Vertical
futari10=Shooter / Flying Vertical
futari15=Shooter / Flying Vertical
futari15a=Shooter / Flying Vertical
futaribl=Shooter / Flying Vertical
futariblj=Shooter / Flying Vertical
ibara=Shooter / Flying Vertical
ibarablk=Shooter / Flying Vertical
ibarablka=Shooter / Flying Vertical
ibarao=Shooter / Flying Vertical
mmpork=Shooter / Flying Vertical
mushisam=Shooter / Flying Vertical
mushisama=Shooter / Flying Vertical
mushisamb=Shooter / Flying Vertical
mushitam=Puzzle / Drop
mushitama=Puzzle / Drop
pinkswts=Shooter / Flying Vertical
pinkswtsa=Shooter / Flying Vertical
pinkswtsb=Shooter / Flying Vertical
pinkswtssc=Shooter / Flying Vertical
pinkswtsx=Shooter / Flying Vertical
wonder3=MultiGame / Compilation
40love=Sports / Tennis
4dwarrio=Shooter / Flying Horizontal
@@ -231,7 +259,12 @@ asteroib=Shooter / Field
astinvad=Shooter / Gallery
kamikaze=Shooter / Gallery
astorm=Platform / Shooter Scrolling
astorm2p=Platform / Shooter Scrolling
astorm3=Platform / Shooter Scrolling
astorm3d=Platform / Shooter Scrolling
astormj=Platform / Shooter Scrolling
astormjd=Platform / Shooter Scrolling
astormu=Platform / Shooter Scrolling
astormud=Platform / Shooter Scrolling
astormbl=Platform / Shooter Scrolling
astrass=Fighter / Versus
astrob=Shooter / Gallery
@@ -246,6 +279,9 @@ lordofk=Platform / Fighter Scrolling
asuka=Shooter / Flying Vertical
asurabld=Fighter / Versus
asurabus=Fighter / Versus
asurabusj=Fighter / Versus
asurabusja=Fighter / Versus
asurabusjr=Fighter / Versus
asylum=Shooter / Walking
atarifb=Sports / Football
atarifb1=Sports / Football
@@ -329,7 +365,10 @@ batrider=Shooter / Flying Vertical
batridra=Shooter / Flying Vertical
batridrk=Shooter / Flying Vertical
batsugun=Shooter / Flying Vertical
batugnsp=Shooter / Flying Vertical
batsuguna=Shooter / Flying Vertical
batsugunc=Shooter / Flying Vertical
batsugunb=Shooter / Flying Vertical
batsugunsp=Shooter / Flying Vertical
battlane=Shooter / Driving Vertical
battlan2=Shooter / Driving Vertical
battlan3=Shooter / Driving Vertical
@@ -453,6 +492,8 @@ bloods21=Fighter / Versus
bloods22=Fighter / Versus
bloodwar=Fighter / Versus
bloxeed=Puzzle / Drop
bloxeeda=Puzzle / Drop
bloxeedd=Puzzle / Drop
bloxeedc=Puzzle / Drop
blstroid=Shooter / Field
blsthead=Shooter / Field
@@ -576,6 +617,9 @@ buckrog=Shooter / Flying (chase view)
buckrogn=Shooter / Flying (chase view)
bucky=Shooter / Walking
buckyua=Shooter / Walking
buggyboy=Driving / Race (chase view)
buggyboyb=Driving / Race (chase view)
buggyboyjr=Driving / Race (chase view)
buggychl=Driving / Race (chase view)
buggycht=Driving / Race (chase view)
bulletd=Shooter / Walking
@@ -779,6 +823,9 @@ clowns=Ball & Paddle / Jump and Touch
clowns1=Ball & Paddle / Jump and Touch
clshroad=Driving / Race Bike
cltchitr=Sports / Baseball
cltchitrd=Sports / Baseball
cltchitrj=Sports / Baseball
cltchitrjd=Sports / Baseball
club90s=Tabletop / Mahjong * Mature *
club90sa=Tabletop / Mahjong * Mature *
cluckypo=Casino / Cards
@@ -852,10 +899,15 @@ cosmogng=Shooter / Gallery
cosmognj=Shooter / Gallery
cosmos=Shooter / Gallery
cotton=Shooter / Flying Horizontal
cottona=Shooter / Flying Horizontal
cotton2=Shooter / Flying Horizontal
cottonbm=Shooter / Flying Horizontal
cottond=Shooter / Flying Horizontal
cottonj=Shooter / Flying Horizontal
cottonja=Shooter / Flying Horizontal
cottonjad=Shooter / Flying Horizontal
cottonjd=Shooter / Flying Horizontal
cottonu=Shooter / Flying Horizontal
cottonud=Shooter / Flying Horizontal
countrun=Maze / Driving
countrunb3=Maze / Driving
countrb2=Maze / Driving
@@ -1031,6 +1083,21 @@ dcon=Shooter / Command
dday=Shooter / Gallery
ddayc=Shooter / Gallery
ddcrew=Fighter / 2.5D
ddcrew1=Fighter / 2.5D
ddcrew1d=Fighter / 2.5D
ddcrew2=Fighter / 2.5D
ddcrew2d=Fighter / 2.5D
ddcrewd=Fighter / 2.5D
ddcrewj=Fighter / 2.5D
ddcrewj2=Fighter / 2.5D
ddcrewj2d=Fighter / 2.5D
ddcrewjd=Fighter / 2.5D
ddcrewu=Fighter / 2.5D
ddcrewud=Fighter / 2.5D
desertbr=Shooter / Walking
desertbrd=Shooter / Walking
desertbrj=Shooter / Walking
desertbrjd=Shooter / Walking
ddenlovr=Tabletop / Othello - Reversi * Mature *
ddonpach=Shooter / Flying Vertical
ddonpacha=Shooter / Flying Vertical
@@ -1191,6 +1258,9 @@ dogfgtj=Shooter / Flying
dogfight=Shooter / Flying
dogpatch=Shooter / Versus
dogyuun=Shooter / Flying Vertical
dogyuuna=Shooter / Flying Vertical
dogyuunb=Shooter / Flying Vertical
dogyuunt=Shooter / Flying Vertical
dogyuunto=Shooter / Flying Vertical
dokaben=Sports / Cards
dokidoki=Platform / Run Jump
@@ -1471,7 +1541,20 @@ countryc=Sports / Golf
fitegol2=Sports / Golf
fitfight=Fighter / Versus
fixeight=Shooter / Walking
fixeighb=Shooter / Walking
fixeightk=Shooter / Walking
fixeighth=Shooter / Walking
fixeighttw=Shooter / Walking
fixeighta=Shooter / Walking
fixeightu=Shooter / Walking
fixeightj=Shooter / Walking
fixeightt=Shooter / Walking
fixeightkt=Shooter / Walking
fixeightht=Shooter / Walking
fixeighttwt=Shooter / Walking
fixeightat=Shooter / Walking
fixeightut=Shooter / Walking
fixeightjt=Shooter / Walking
fixeightbl=Shooter / Walking
flagrall=Maze / Driving
flashgal=Fighter / 2D
flicky=Platform / Run Jump
@@ -2195,6 +2278,8 @@ karnovj=Platform / Shooter Scrolling
karnovr=Fighter / Versus
kazan=Platform / Fighter Scrolling
kbash=Fighter / Versus Co-op
kbashk=Fighter / Versus Co-op
kbashp=Fighter / Versus Co-op
kbash2=Fighter / Versus Co-op
kchamp=Fighter / Versus
karatedo=Fighter / Versus
@@ -2394,6 +2479,10 @@ lethalth=Shooter / Flying Vertical
thndblst=Shooter / Flying Vertical
levers=Platform / Run Jump
lghost=Shooter / Gun
lghostd=Shooter / Gun
lghostj=Shooter / Gun
lghostu=Shooter / Gun
lghostud=Shooter / Gun
lgtnfght=Shooter / Flying Vertical
trigon=Shooter / Flying Vertical
liberate=Shooter / Flying
@@ -2523,6 +2612,7 @@ marineb=Shooter / Flying
marinedt=Maze / Escape
mariner=Shooter / Misc. Horizontal
800fath=Shooter / Misc. Horizontal
800fatha=Shooter / Misc. Horizontal
mario=Platform / Run Jump
marioe=Platform / Run Jump
mariof=Platform / Run Jump
@@ -2766,11 +2856,12 @@ mouserc=Platform / Run Jump
mp_bio=Shooter / Flying Horizontal
mp_col3=Puzzle / Drop
mp_gaxe2=Fighter / 2.5D
mp_gaxe2a=Fighter / 2.5D
mp_shnb3=Platform / Shooter Scrolling
mp_soni2=Platform / Run, Jump & Scrolling
mp_sonic=Platform / Run, Jump & Scrolling
mp_sor2=Fighter / 2.5D
mp_twc=Sports / Soccer
mp_twcup=Sports / Soccer
mpang=Shooter / 3rd Person
mpanga=Shooter / 3rd Person
mpangj=Shooter / 3rd Person
@@ -4104,9 +4195,9 @@ shanhigw=Puzzle / Match
sharkatt=Shooter / Underwater
sharrier=Shooter / Flying (chase view)
shdancer=Platform / Fighter Scrolling
shdancer1=Platform / Fighter Scrolling
shdancerj=Platform / Fighter Scrolling
shdancbl=Platform / Fighter Scrolling
shdancrb=Platform / Fighter Scrolling
shdancrj=Platform / Fighter Scrolling
sheriff=Shooter / Field
bandido=Shooter / Field
shienryu=Shooter / Flying Vertical
@@ -4892,7 +4983,10 @@ labyrunk=Shooter / Walking
labyrunr=Shooter / Walking
triothep=Platform / Fighter Scrolling
triplep=Maze / Outline
triplepa=Maze / Outline
knockout=Maze / Outline
knockoutb=Maze / Outline
knockoutc=Maze / Outline
triplew1=Tabletop / Mahjong * Mature *
triplew2=Tabletop / Mahjong * Mature *
triplhnt=Shooter / Gun
@@ -4979,6 +5073,9 @@ twinspri=Shooter / Flying Vertical
twotiger=Shooter / Field
twotigra=Shooter / Field
tws96=Sports / Soccer
tx1=Driving / Race (chase view)
tx1jb=Driving / Race (chase view)
tx1jc=Driving / Race (chase view)
tylz=Maze / Change Surface
uballoon=Platform / Run Jump
uccops=Fighter / 2.5D
@@ -5058,7 +5155,7 @@ venture2=Maze / Shooter Small
venture4=Maze / Shooter Small
vf=Fighter / Versus
vfive=Shooter / Flying Vertical
grindsta=Shooter / Flying Vertical
grindstma=Shooter / Flying Vertical
grindstm=Shooter / Flying Vertical
vfkids=Fighter / Versus
vfremix=Fighter / Versus
@@ -5254,6 +5351,11 @@ wschampa=Shooter / Gun
wseries=Sports / Baseball
wsf=Sports / Soccer
wtennis=Sports / Tennis
wwallyj=Puzzle / Find the Objects
wwallyja=Puzzle / Find the Objects
wwallyja3p=Puzzle / Find the Objects
wwallyjad=Puzzle / Find the Objects
wwallyjd=Puzzle / Find the Objects
wwestern=Shooter / Misc. Vertical
wwester1=Shooter / Misc. Vertical
wwfmania=Sports / Wrestling
metadata/cheat.dat
+234 -176
View File
@@ -5721,7 +5721,26 @@ astinvad:0:1F9D:99:000:Infinite Credits
astinvad:0:1D01:08:000:Infinite Lives
astinvad:0:1CD8:00:000:Invincibility
; [ Alien Storm ]
; [ Alien Storm (Japan, 2 Players) ]
astormj:0:000000:00:999:[Invincibility only works ]
astormj:0:000000:00:999:[for the following missions ]
astormj:0:000000:00:999:[ 1-1, 2-1, 2-3, 3-1, 3-5, ]
astormj:0:000000:00:999:[ 3-7, 4-1, 4-5, 5-1, 5-2, ]
astormj:0:000000:00:999:[ 5-4, 6-1, 6-2, 6-4, 6-5. ]
astormj:0:FFE00D:30:000:Infinite Life PL1
astormj:0:FFE00E:80:000:Infinite Energy PL1
astormj:0:FFC061:78:000:Invincibility PL1
astormj:0:FFE031:00:000:No delay for extra weapon PL1
astormj:0:FFE08D:30:000:Infinite Life PL2
astormj:0:FFE08E:80:000:Infinite Energy PL2
astormj:0:FFC461:78:000:Invincibility PL2
astormj:0:FFE0B1:00:000:No delay for extra weapon PL2
astormj:0:FFE10D:30:000:Infinite Life PL3
astormj:0:FFE10E:80:000:Infinite Energy PL3
astormj:0:FFC861:78:000:Invincibility PL3
astormj:0:FFE131:00:000:No delay for extra weapon PL3
; [ Alien Storm (World, 2 Players) ]
astorm:0:000000:00:999:[Invincibility only works ]
astorm:0:000000:00:999:[for the following missions ]
astorm:0:000000:00:999:[ 1-1, 2-1, 2-3, 3-1, 3-5, ]
@@ -5735,25 +5754,6 @@ astorm:0:FFE08D:30:000:Infinite Life PL2
astorm:0:FFE08E:80:000:Infinite Energy PL2
astorm:0:FFC461:78:000:Invincibility PL2
astorm:0:FFE0B1:00:000:No delay for extra weapon PL2
astorm:0:FFE10D:30:000:Infinite Life PL3
astorm:0:FFE10E:80:000:Infinite Energy PL3
astorm:0:FFC861:78:000:Invincibility PL3
astorm:0:FFE131:00:000:No delay for extra weapon PL3
; [ Alien Storm (2 Player) ]
astorm2p:0:000000:00:999:[Invincibility only works ]
astorm2p:0:000000:00:999:[for the following missions ]
astorm2p:0:000000:00:999:[ 1-1, 2-1, 2-3, 3-1, 3-5, ]
astorm2p:0:000000:00:999:[ 3-7, 4-1, 4-5, 5-1, 5-2, ]
astorm2p:0:000000:00:999:[ 5-4, 6-1, 6-2, 6-4, 6-5. ]
astorm2p:0:FFE00D:30:000:Infinite Life PL1
astorm2p:0:FFE00E:80:000:Infinite Energy PL1
astorm2p:0:FFC061:78:000:Invincibility PL1
astorm2p:0:FFE031:00:000:No delay for extra weapon PL1
astorm2p:0:FFE08D:30:000:Infinite Life PL2
astorm2p:0:FFE08E:80:000:Infinite Energy PL2
astorm2p:0:FFC461:78:000:Invincibility PL2
astorm2p:0:FFE0B1:00:000:No delay for extra weapon PL2
; [ Alien Storm (bootleg) ]
astormbl:0:000000:00:999:[Invincibility only works ]
@@ -7780,6 +7780,34 @@ batsugun:0:1013EB:09:000:Next 'P' always=10000 pts PL2:Get maximum fire power
batsugun:0:1013EB:09:001:Next 'P' = 10000 pts Now! PL2:Get maximum fire power
batsugun:0:101456:03:001:Up fire level Now! PL2
batsugun:0:101457:00:501:Up fire level Now! PL2 (2/2)
batsuguna:0:10139B:09:000:Infinite Lives PL1
batsuguna:0:101415:07:000:Infinite Bombs PL1
batsuguna:0:10141E:01:000:Invincibility PL1
batsuguna:0:000000:00:999:[See the Dip Switch Menu to ]
batsuguna:0:000000:00:999:[enable an alternate ]
batsuguna:0:000000:00:999:[Invincibility PL1 cheat. ]
batsuguna:0:000000:00:999:[But the cheat is better as ]
batsuguna:0:000000:00:999:[the dipswitch causes a game]
batsuguna:0:000000:00:999:[crash when PL2 is selected.]
batsuguna:0:101411:02:000:Always have Max Weapon PL1
batsuguna:0:101413:04:000:Always have Max Shot PowerPL1
batsuguna:0:101411:02:001:Get Max Weapon Now! PL1
batsuguna:0:101413:04:001:Get Max Shot Power Now! PL1
batsuguna:0:1013E7:09:000:Next 'P' always=10000 pts PL1:Get maximum fire power
batsuguna:0:1013E7:09:001:Next 'P' = 10000 pts Now! PL1:Get maximum fire power
batsuguna:0:101416:03:001:Up fire level Now! PL1
batsuguna:0:101417:00:501:Up fire level Now! PL1 (2/2)
batsuguna:0:10139D:09:000:Infinite Lives PL2
batsuguna:0:101455:07:000:Infinite Bombs PL2
batsuguna:0:10145E:01:000:Invincibility PL2
batsuguna:0:101451:02:000:Always have Max Weapon PL2
batsuguna:0:101453:04:000:Always have Max Shot PowerPL2
batsuguna:0:101451:02:001:Get Max Weapon Now! PL2
batsuguna:0:101453:04:001:Get Max Shot Power Now! PL2
batsuguna:0:1013EB:09:000:Next 'P' always=10000 pts PL2:Get maximum fire power
batsuguna:0:1013EB:09:001:Next 'P' = 10000 pts Now! PL2:Get maximum fire power
batsuguna:0:101456:03:001:Up fire level Now! PL2
batsuguna:0:101457:00:501:Up fire level Now! PL2 (2/2)
; [ Battle Lane! Vol. 5 (set 2) ]
battlan2:0:0CDA:03:000:Infinite Lives PL1
@@ -7986,34 +8014,34 @@ battroad:0:0000:00:999:[enable an alternate ]
battroad:0:0000:00:999:[Invincibility cheat. ]
; [ Batsugun (Special Ver.) ]
batugnsp:0:10139B:09:000:Infinite Lives PL1
batugnsp:0:101415:07:000:Infinite Bombs PL1
batugnsp:0:10141E:01:000:Invincibility PL1
batugnsp:0:000000:00:999:[See the Dip Switch Menu to ]
batugnsp:0:000000:00:999:[enable an alternate ]
batugnsp:0:000000:00:999:[Invincibility PL1 cheat. ]
batugnsp:0:000000:00:999:[But the cheat is better as ]
batugnsp:0:000000:00:999:[the dipswitch causes a game]
batugnsp:0:000000:00:999:[crash when PL2 is selected.]
batugnsp:0:101411:02:000:Always have Max Weapon PL1
batugnsp:0:101413:04:000:Always have Max Shot PowerPL1
batugnsp:0:101411:02:001:Get Max Weapon Now! PL1
batugnsp:0:101413:04:001:Get Max Shot Power Now! PL1
batugnsp:0:1013E7:09:000:Next 'P' always=10000 pts PL1:Get maximum fire power
batugnsp:0:1013E7:09:001:Next 'P' = 10000 pts Now! PL1:Get maximum fire power
batugnsp:0:101416:03:001:Up fire level Now! PL1
batugnsp:0:101417:00:501:Up fire level Now! PL1 (2/2)
batugnsp:0:10139D:09:000:Infinite Lives PL2
batugnsp:0:101455:07:000:Infinite Bombs PL2
batugnsp:0:10145E:01:000:Invincibility PL2
batugnsp:0:101451:02:000:Always have Max Weapon PL2
batugnsp:0:101453:04:000:Always have Max Shot PowerPL2
batugnsp:0:101451:02:001:Get Max Weapon Now! PL2
batugnsp:0:101453:04:001:Get Max Shot Power Now! PL2
batugnsp:0:1013EB:09:000:Next 'P' always=10000 pts PL2:Get maximum fire power
batugnsp:0:1013EB:09:001:Next 'P' = 10000 pts Now! PL2:Get maximum fire power
batugnsp:0:101456:03:001:Up fire level Now! PL2
batugnsp:0:101457:00:501:Up fire level Now! PL2 (2/2)
batsugunsp:0:10139B:09:000:Infinite Lives PL1
batsugunsp:0:101415:07:000:Infinite Bombs PL1
batsugunsp:0:10141E:01:000:Invincibility PL1
batsugunsp:0:000000:00:999:[See the Dip Switch Menu to ]
batsugunsp:0:000000:00:999:[enable an alternate ]
batsugunsp:0:000000:00:999:[Invincibility PL1 cheat. ]
batsugunsp:0:000000:00:999:[But the cheat is better as ]
batsugunsp:0:000000:00:999:[the dipswitch causes a game]
batsugunsp:0:000000:00:999:[crash when PL2 is selected.]
batsugunsp:0:101411:02:000:Always have Max Weapon PL1
batsugunsp:0:101413:04:000:Always have Max Shot PowerPL1
batsugunsp:0:101411:02:001:Get Max Weapon Now! PL1
batsugunsp:0:101413:04:001:Get Max Shot Power Now! PL1
batsugunsp:0:1013E7:09:000:Next 'P' always=10000 pts PL1:Get maximum fire power
batsugunsp:0:1013E7:09:001:Next 'P' = 10000 pts Now! PL1:Get maximum fire power
batsugunsp:0:101416:03:001:Up fire level Now! PL1
batsugunsp:0:101417:00:501:Up fire level Now! PL1 (2/2)
batsugunsp:0:10139D:09:000:Infinite Lives PL2
batsugunsp:0:101455:07:000:Infinite Bombs PL2
batsugunsp:0:10145E:01:000:Invincibility PL2
batsugunsp:0:101451:02:000:Always have Max Weapon PL2
batsugunsp:0:101453:04:000:Always have Max Shot PowerPL2
batsugunsp:0:101451:02:001:Get Max Weapon Now! PL2
batsugunsp:0:101453:04:001:Get Max Shot Power Now! PL2
batsugunsp:0:1013EB:09:000:Next 'P' always=10000 pts PL2:Get maximum fire power
batsugunsp:0:1013EB:09:001:Next 'P' = 10000 pts Now! PL2:Get maximum fire power
batsugunsp:0:101456:03:001:Up fire level Now! PL2
batsugunsp:0:101457:00:501:Up fire level Now! PL2 (2/2)
; [ Battle Wings (alt) ]
batwings:0:0084:0A:000:Infinite Lives
@@ -15490,16 +15518,6 @@ clshroad:0:81E7:00:500:Infinite Time (3/3)
clshroad:0:81FD:03:000:Infinite Energy
clshroad:0:81FE:0E:500:Infinite Energy (2/2)
; [ Clutch Hitter ]
cltchitr:0:0000:00:999:[ There are no cheats ]:REASON 1
cltchitr:0:0000:00:999:[ for this game as it ]:REASON 1
cltchitr:0:0000:00:999:[ didn't work the last ]:REASON 1
cltchitr:0:0000:00:999:[ time it was tested. ]:REASON 1
cltchitr:0:0000:00:999:[ If the game now works ]:REASON 1
cltchitr:0:0000:00:999:[ please request cheats ]:REASON 1
cltchitr:0:0000:00:999:[ for it on the cheat ]:REASON 1
cltchitr:0:0000:00:999:[ forums. ]:REASON 1
; [ Mahjong CLUB 90's (set 1) (Japan 900919) ]
club90s:0:F0EF:63:000:Infinite Money
club90s:0:0000:00:999:[ The winning hand cheat must be ]
@@ -16560,16 +16578,6 @@ cosmos:0:1D66:01:040:Invincibility:Turn OFF to dock!
cosmos:0:1CDD:05:000:Infinite Lives PL1
cosmos:0:1CDE:05:000:Infinite Lives PL2
; [ Cotton (Japan) ]
cotton:0:0000:00:999:[ There are no cheats ]:REASON 1
cotton:0:0000:00:999:[ for this game as it ]:REASON 1
cotton:0:0000:00:999:[ didn't work the last ]:REASON 1
cotton:0:0000:00:999:[ time it was tested. ]:REASON 1
cotton:0:0000:00:999:[ If the game now works ]:REASON 1
cotton:0:0000:00:999:[ please request cheats ]:REASON 1
cotton:0:0000:00:999:[ for it on the cheat ]:REASON 1
cotton:0:0000:00:999:[ forums. ]:REASON 1
; [ Cotton 2 ]
cotton2:0:060E518F:06:000:Invincibility PL1
cotton2:0:060E5DD3:21:000:Maximum Fire Power PL1
@@ -19867,16 +19875,6 @@ ddayjlc:0:0000:00:999:[ please request cheats ]:REASON 1
ddayjlc:0:0000:00:999:[ for it on the cheat ]:REASON 1
ddayjlc:0:0000:00:999:[ forums. ]:REASON 1
; [ DD Crew ]
ddcrew:0:0000:00:999:[ There are no cheats ]:REASON 1
ddcrew:0:0000:00:999:[ for this game as it ]:REASON 1
ddcrew:0:0000:00:999:[ didn't work the last ]:REASON 1
ddcrew:0:0000:00:999:[ time it was tested. ]:REASON 1
ddcrew:0:0000:00:999:[ If the game now works ]:REASON 1
ddcrew:0:0000:00:999:[ please request cheats ]:REASON 1
ddcrew:0:0000:00:999:[ for it on the cheat ]:REASON 1
ddcrew:0:0000:00:999:[ forums. ]:REASON 1
; [ Don Den Lover Vol. 1 (Hong Kong) ]
ddenlovr:0:FF9576:64:000:Infinite Time
ddenlovr:0:FF959E:03:000:Infinite Help
@@ -40404,27 +40402,27 @@ griffon:0:4BFF:00:000:Infinite Fuel
griffon:0:0CC4:C9:100:Invincibility
; [ Grind Stormer (older set) ]
grindsta:0:1003B3:09:000:Infinite Credits
grindsta:0:10063D:0F:000:Infinite Lives
grindsta:0:10065B:06:000:Infinite Bombs
grindsta:0:000000:00:999:[ See the Dip Switch Menu to enable ]
grindsta:0:000000:00:999:[ an Invincibility PL1 cheat. But ]
grindsta:0:000000:00:999:[ the dipswitch causes a game crash ]
grindsta:0:000000:00:999:[ when PL2 is selected. ]
grindsta:0:100607:02:000:Always have 4 Side Ships
grindsta:0:1005E7:B0:000:Always have Shot Side Ships
grindsta:0:100601:00:500:Always have Shot Side Ships (2/2)
grindsta:0:1005E7:B4:000:Always have Search Side Ships
grindsta:0:100601:01:500:Always have Search Side Ships (2/2)
grindsta:0:1005E7:C4:000:Always have Missile Side Ships
grindsta:0:100601:02:500:Always have Missile Side Ships (2/2)
grindsta:0:100607:02:001:Get 4 Side Ships Now!
grindsta:0:1005E7:B0:001:Get Shot Side Ships Now!
grindsta:0:100601:00:501:Get Shot Side Ships Now! (2/2)
grindsta:0:1005E7:B4:001:Get Search Side Ships Now!
grindsta:0:100601:01:501:Get Search Side Ships Now! (2/2)
grindsta:0:1005E7:C4:001:Get Missile Side Ships Now!
grindsta:0:100601:02:501:Get Missile Side Ships Now! (2/2)
grindstma:0:1003B3:09:000:Infinite Credits
grindstma:0:10063D:0F:000:Infinite Lives
grindstma:0:10065B:06:000:Infinite Bombs
grindstma:0:000000:00:999:[ See the Dip Switch Menu to enable ]
grindstma:0:000000:00:999:[ an Invincibility PL1 cheat. But ]
grindstma:0:000000:00:999:[ the dipswitch causes a game crash ]
grindstma:0:000000:00:999:[ when PL2 is selected. ]
grindstma:0:100607:02:000:Always have 4 Side Ships
grindstma:0:1005E7:B0:000:Always have Shot Side Ships
grindstma:0:100601:00:500:Always have Shot Side Ships (2/2)
grindstma:0:1005E7:B4:000:Always have Search Side Ships
grindstma:0:100601:01:500:Always have Search Side Ships (2/2)
grindstma:0:1005E7:C4:000:Always have Missile Side Ships
grindstma:0:100601:02:500:Always have Missile Side Ships (2/2)
grindstma:0:100607:02:001:Get 4 Side Ships Now!
grindstma:0:1005E7:B0:001:Get Shot Side Ships Now!
grindstma:0:100601:00:501:Get Shot Side Ships Now! (2/2)
grindstma:0:1005E7:B4:001:Get Search Side Ships Now!
grindstma:0:100601:01:501:Get Search Side Ships Now! (2/2)
grindstma:0:1005E7:C4:001:Get Missile Side Ships Now!
grindstma:0:100601:02:501:Get Missile Side Ships Now! (2/2)
; [ Grind Stormer ]
grindstm:0:1003B3:09:000:Infinite Credits
@@ -59636,16 +59634,6 @@ lethalth:0:E3ADE:03:001:Get Ball Shot Now! PL2
levers:0:4175:63:000:Infinite Lives PL1
levers:0:4176:63:000:Infinite Lives PL2
; [ Laser Ghost ]
lghost:0:0000:00:999:[ There are no cheats ]:REASON 1
lghost:0:0000:00:999:[ for this game as it ]:REASON 1
lghost:0:0000:00:999:[ didn't work the last ]:REASON 1
lghost:0:0000:00:999:[ time it was tested. ]:REASON 1
lghost:0:0000:00:999:[ If the game now works ]:REASON 1
lghost:0:0000:00:999:[ please request cheats ]:REASON 1
lghost:0:0000:00:999:[ for it on the cheat ]:REASON 1
lghost:0:0000:00:999:[ forums. ]:REASON 1
; [ Lightning Fighters (US) ]
lgtnfght:0:000000:00:999:[Enable invincibility during]
lgtnfght:0:000000:00:999:[game play ONLY!! ]
@@ -67333,25 +67321,125 @@ mooncrsu:0:823C:00:001:Finish this Round Now!:Use this with an activation key fo
; [ Moon Quasar ]
moonqsr:0:8087:F8:000:Infinite Fuel
; [ Michael Jackson's Moonwalker (Set 1) ]
moonwalk:0:FFDA58:03:000:Infinite Lives PL1
moonwalk:0:FFC01C:40:000:Infinite Energy PL1
moonwalk:0:FFDA79:01:000:Infinite Magic PL1
moonwalk:0:FFDA7D:45:000:Invincibility PL1
moonwalk:0:FFC04C:04:000:Always Robot PL1:Best enabled on title screen
moonwalk:0:FFC04C:04:001:Become Robot Now! PL1:Buggy
moonwalk:0:FFDA98:03:000:Infinite Lives PL2
moonwalk:0:FFC0DC:40:000:Infinite Energy PL2
moonwalk:0:FFDAB9:01:000:Infinite Magic PL2
moonwalk:0:FFDABD:45:000:Invincibility PL2
moonwalk:0:FFC10C:04:000:Always Robot PL2:Best enabled on title screen
moonwalk:0:FFC10C:04:001:Become Robot Now! PL2:Buggy
moonwalk:0:FFDAD8:03:000:Infinite Lives PL3
moonwalk:0:FFC19C:28:000:Infinite Energy PL3
moonwalk:0:FFDAF9:01:000:Infinite Magic PL3
moonwalk:0:FFDAFD:45:000:Invincibility PL3
moonwalk:0:FFC1CC:04:000:Always Robot PL3:Best enabled on title screen
moonwalk:0:FFC1CC:04:001:Become Robot Now! PL3:Buggy
; [ Michael Jackson's Moonwalker (World) ]
mwalk:0:FFDA58:03:000:Infinite Lives PL1
mwalk:0:FFC01C:40:000:Infinite Energy PL1
mwalk:0:FFDA79:01:000:Infinite Magic PL1
mwalk:0:FFDA7D:45:000:Invincibility PL1
mwalk:0:FFC04C:04:000:Always Robot PL1:Best enabled on title screen
mwalk:0:FFC04C:04:001:Become Robot Now! PL1:Buggy
mwalk:0:FFDA98:03:000:Infinite Lives PL2
mwalk:0:FFC0DC:40:000:Infinite Energy PL2
mwalk:0:FFDAB9:01:000:Infinite Magic PL2
mwalk:0:FFDABD:45:000:Invincibility PL2
mwalk:0:FFC10C:04:000:Always Robot PL2:Best enabled on title screen
mwalk:0:FFC10C:04:001:Become Robot Now! PL2:Buggy
mwalk:0:FFDAD8:03:000:Infinite Lives PL3
mwalk:0:FFC19C:28:000:Infinite Energy PL3
mwalk:0:FFDAF9:01:000:Infinite Magic PL3
mwalk:0:FFDAFD:45:000:Invincibility PL3
mwalk:0:FFC1CC:04:000:Always Robot PL3:Best enabled on title screen
mwalk:0:FFC1CC:04:001:Become Robot Now! PL3:Buggy
; [ Michael Jackson's Moonwalker (US) ]
mwalku:0:FFDA58:03:000:Infinite Lives PL1
mwalku:0:FFC01C:40:000:Infinite Energy PL1
mwalku:0:FFDA79:01:000:Infinite Magic PL1
mwalku:0:FFDA7D:45:000:Invincibility PL1
mwalku:0:FFC04C:04:000:Always Robot PL1:Best enabled on title screen
mwalku:0:FFC04C:04:001:Become Robot Now! PL1:Buggy
mwalku:0:FFDA98:03:000:Infinite Lives PL2
mwalku:0:FFC0DC:40:000:Infinite Energy PL2
mwalku:0:FFDAB9:01:000:Infinite Magic PL2
mwalku:0:FFDABD:45:000:Invincibility PL2
mwalku:0:FFC10C:04:000:Always Robot PL2:Best enabled on title screen
mwalku:0:FFC10C:04:001:Become Robot Now! PL2:Buggy
mwalku:0:FFDAD8:03:000:Infinite Lives PL3
mwalku:0:FFC19C:28:000:Infinite Energy PL3
mwalku:0:FFDAF9:01:000:Infinite Magic PL3
mwalku:0:FFDAFD:45:000:Invincibility PL3
mwalku:0:FFC1CC:04:000:Always Robot PL3:Best enabled on title screen
mwalku:0:FFC1CC:04:001:Become Robot Now! PL3:Buggy
; [ Michael Jackson's Moonwalker (Japan) ]
mwalkj:0:FFDA58:03:000:Infinite Lives PL1
mwalkj:0:FFC01C:40:000:Infinite Energy PL1
mwalkj:0:FFDA79:01:000:Infinite Magic PL1
mwalkj:0:FFDA7D:45:000:Invincibility PL1
mwalkj:0:FFC04C:04:000:Always Robot PL1:Best enabled on title screen
mwalkj:0:FFC04C:04:001:Become Robot Now! PL1:Buggy
mwalkj:0:FFDA98:03:000:Infinite Lives PL2
mwalkj:0:FFC0DC:40:000:Infinite Energy PL2
mwalkj:0:FFDAB9:01:000:Infinite Magic PL2
mwalkj:0:FFDABD:45:000:Invincibility PL2
mwalkj:0:FFC10C:04:000:Always Robot PL2:Best enabled on title screen
mwalkj:0:FFC10C:04:001:Become Robot Now! PL2:Buggy
mwalkj:0:FFDAD8:03:000:Infinite Lives PL3
mwalkj:0:FFC19C:28:000:Infinite Energy PL3
mwalkj:0:FFDAF9:01:000:Infinite Magic PL3
mwalkj:0:FFDAFD:45:000:Invincibility PL3
mwalkj:0:FFC1CC:04:000:Always Robot PL3:Best enabled on title screen
mwalkj:0:FFC1CC:04:001:Become Robot Now! PL3:Buggy
; [ Michael Jackson's Moonwalker (World, bootleg of FD1094/8751 317-0159 set) ]
mwalkd:0:FFDA58:03:000:Infinite Lives PL1
mwalkd:0:FFC01C:40:000:Infinite Energy PL1
mwalkd:0:FFDA79:01:000:Infinite Magic PL1
mwalkd:0:FFDA7D:45:000:Invincibility PL1
mwalkd:0:FFC04C:04:000:Always Robot PL1:Best enabled on title screen
mwalkd:0:FFC04C:04:001:Become Robot Now! PL1:Buggy
mwalkd:0:FFDA98:03:000:Infinite Lives PL2
mwalkd:0:FFC0DC:40:000:Infinite Energy PL2
mwalkd:0:FFDAB9:01:000:Infinite Magic PL2
mwalkd:0:FFDABD:45:000:Invincibility PL2
mwalkd:0:FFC10C:04:000:Always Robot PL2:Best enabled on title screen
mwalkd:0:FFC10C:04:001:Become Robot Now! PL2:Buggy
mwalkd:0:FFDAD8:03:000:Infinite Lives PL3
mwalkd:0:FFC19C:28:000:Infinite Energy PL3
mwalkd:0:FFDAF9:01:000:Infinite Magic PL3
mwalkd:0:FFDAFD:45:000:Invincibility PL3
mwalkd:0:FFC1CC:04:000:Always Robot PL3:Best enabled on title screen
mwalkd:0:FFC1CC:04:001:Become Robot Now! PL3:Buggy
; [ Michael Jackson's Moonwalker (US, bootleg of FD1094/8751 317-0158 set) ]
mwalkud:0:FFDA58:03:000:Infinite Lives PL1
mwalkud:0:FFC01C:40:000:Infinite Energy PL1
mwalkud:0:FFDA79:01:000:Infinite Magic PL1
mwalkud:0:FFDA7D:45:000:Invincibility PL1
mwalkud:0:FFC04C:04:000:Always Robot PL1:Best enabled on title screen
mwalkud:0:FFC04C:04:001:Become Robot Now! PL1:Buggy
mwalkud:0:FFDA98:03:000:Infinite Lives PL2
mwalkud:0:FFC0DC:40:000:Infinite Energy PL2
mwalkud:0:FFDAB9:01:000:Infinite Magic PL2
mwalkud:0:FFDABD:45:000:Invincibility PL2
mwalkud:0:FFC10C:04:000:Always Robot PL2:Best enabled on title screen
mwalkud:0:FFC10C:04:001:Become Robot Now! PL2:Buggy
mwalkud:0:FFDAD8:03:000:Infinite Lives PL3
mwalkud:0:FFC19C:28:000:Infinite Energy PL3
mwalkud:0:FFDAF9:01:000:Infinite Magic PL3
mwalkud:0:FFDAFD:45:000:Invincibility PL3
mwalkud:0:FFC1CC:04:000:Always Robot PL3:Best enabled on title screen
mwalkud:0:FFC1CC:04:001:Become Robot Now! PL3:Buggy
; [ Michael Jackson's Moonwalker (Japan, bootleg of FD1094/8751 317-0157 set) ]
mwalkjd:0:FFDA58:03:000:Infinite Lives PL1
mwalkjd:0:FFC01C:40:000:Infinite Energy PL1
mwalkjd:0:FFDA79:01:000:Infinite Magic PL1
mwalkjd:0:FFDA7D:45:000:Invincibility PL1
mwalkjd:0:FFC04C:04:000:Always Robot PL1:Best enabled on title screen
mwalkjd:0:FFC04C:04:001:Become Robot Now! PL1:Buggy
mwalkjd:0:FFDA98:03:000:Infinite Lives PL2
mwalkjd:0:FFC0DC:40:000:Infinite Energy PL2
mwalkjd:0:FFDAB9:01:000:Infinite Magic PL2
mwalkjd:0:FFDABD:45:000:Invincibility PL2
mwalkjd:0:FFC10C:04:000:Always Robot PL2:Best enabled on title screen
mwalkjd:0:FFC10C:04:001:Become Robot Now! PL2:Buggy
mwalkjd:0:FFDAD8:03:000:Infinite Lives PL3
mwalkjd:0:FFC19C:28:000:Infinite Energy PL3
mwalkjd:0:FFDAF9:01:000:Infinite Magic PL3
mwalkjd:0:FFDAFD:45:000:Invincibility PL3
mwalkjd:0:FFC1CC:04:000:Always Robot PL3:Best enabled on title screen
mwalkjd:0:FFC1CC:04:001:Become Robot Now! PL3:Buggy
; [ Moonwar ]
moonwar:0:8744:09:000:Infinite Lives
@@ -67363,26 +67451,6 @@ moonwara:0:8744:09:000:Infinite Lives
moonwara:0:8758:99:000:Infinite Fuel
moonwara:0:875A:99:000:Infinite Shields
; [ Michael Jackson's Moonwalker (Set 2) ]
moonwlka:0:FFDA58:03:000:Infinite Lives PL1
moonwlka:0:FFC01C:40:000:Infinite Energy PL1
moonwlka:0:FFDA79:01:000:Infinite Magic PL1
moonwlka:0:FFDA7D:45:000:Invincibility PL1
moonwlka:0:FFC04C:04:000:Always Robot PL1:Best enabled on title screen
moonwlka:0:FFC04C:04:001:Become Robot Now! PL1:Buggy
moonwlka:0:FFDA98:03:000:Infinite Lives PL2
moonwlka:0:FFC0DC:40:000:Infinite Energy PL2
moonwlka:0:FFDAB9:01:000:Infinite Magic PL2
moonwlka:0:FFDABD:45:000:Invincibility PL2
moonwlka:0:FFC10C:04:000:Always Robot PL2:Best enabled on title screen
moonwlka:0:FFC10C:04:001:Become Robot Now! PL2:Buggy
moonwlka:0:FFDAD8:03:000:Infinite Lives PL3
moonwlka:0:FFC19C:28:000:Infinite Energy PL3
moonwlka:0:FFDAF9:01:000:Infinite Magic PL3
moonwlka:0:FFDAFD:45:000:Invincibility PL3
moonwlka:0:FFC1CC:04:000:Always Robot PL3:Best enabled on title screen
moonwlka:0:FFC1CC:04:001:Become Robot Now! PL3:Buggy
; [ Michael Jackson's Moonwalker (bootleg) ]
moonwlkb:0:FFDA58:03:000:Infinite Lives PL1
moonwlkb:0:FFC01C:40:000:Infinite Energy PL1
@@ -113936,7 +114004,7 @@ shdancbl:0:FFC490:01:001:Get the Power-up gun Now!
shdancbl:0:FFEB0A:9A:000:Infinite Lives PL1
shdancbl:0:FFEB8A:9A:000:Infinite Lives PL2
; [ Shadow Dancer (US) ]
; [ Shadow Dancer (World) ]
shdancer:0:FFC407:59:000:Infinite Time
shdancer:0:FFC41F:09:000:Infinite Magic
shdancer:0:FFC490:00:000:Always have the Normal gun
@@ -113946,25 +114014,25 @@ shdancer:0:FFC490:01:001:Get the Power-up gun Now!
shdancer:0:FFEB0A:9A:000:Infinite Lives PL1
shdancer:0:FFEB8A:9A:000:Infinite Lives PL2
; [ Shadow Dancer (Rev.B) ]
shdancrb:0:FFC407:59:000:Infinite Time
shdancrb:0:FFC41F:09:000:Infinite Magic
shdancrb:0:FFC490:00:000:Always have the Normal gun
shdancrb:0:FFC490:01:000:Always have the Power-up gun
shdancrb:0:FFC490:00:001:Get the Normal gun Now!
shdancrb:0:FFC490:01:001:Get the Power-up gun Now!
shdancrb:0:FFEB0A:9A:000:Infinite Lives PL1
shdancrb:0:FFEB8A:9A:000:Infinite Lives PL2
; [ Shadow Dancer (US) ]
shdancer1:0:FFC407:59:000:Infinite Time
shdancer1:0:FFC41F:09:000:Infinite Magic
shdancer1:0:FFC490:00:000:Always have the Normal gun
shdancer1:0:FFC490:01:000:Always have the Power-up gun
shdancer1:0:FFC490:00:001:Get the Normal gun Now!
shdancer1:0:FFC490:01:001:Get the Power-up gun Now!
shdancer1:0:FFEB0A:9A:000:Infinite Lives PL1
shdancer1:0:FFEB8A:9A:000:Infinite Lives PL2
; [ Shadow Dancer (Japan) ]
shdancrj:0:FFC407:59:000:Infinite Time
shdancrj:0:FFC41F:09:000:Infinite Magic
shdancrj:0:FFC490:00:000:Always have the Normal gun
shdancrj:0:FFC490:01:000:Always have the Power-up gun
shdancrj:0:FFC490:00:001:Get the Normal gun Now!
shdancrj:0:FFC490:01:001:Get the Power-up gun Now!
shdancrj:0:FFEB0A:9A:000:Infinite Lives PL1
shdancrj:0:FFEB8A:9A:000:Infinite Lives PL2
shdancerj:0:FFC407:59:000:Infinite Time
shdancerj:0:FFC41F:09:000:Infinite Magic
shdancerj:0:FFC490:00:000:Always have the Normal gun
shdancerj:0:FFC490:01:000:Always have the Power-up gun
shdancerj:0:FFC490:00:001:Get the Normal gun Now!
shdancerj:0:FFC490:01:001:Get the Power-up gun Now!
shdancerj:0:FFEB0A:9A:000:Infinite Lives PL1
shdancerj:0:FFEB8A:9A:000:Infinite Lives PL2
; [ Sheriff ]
sheriff:0:6035:FF:000:Invincibility
@@ -138565,16 +138633,6 @@ wtennis:0:00C1:00:001:Set 'HER' to 0 Now! PL2
wtennis:0:00C2:03:001:Set 'HIS' to 3 Now! PL2
wtennis:0:00C1:03:001:Set 'HER' to 3 Now! PL2
; [ Where's Wally? ]
wwally:0:0000:00:999:[ There are no cheats ]:REASON 1
wwally:0:0000:00:999:[ for this game as it ]:REASON 1
wwally:0:0000:00:999:[ didn't work the last ]:REASON 1
wwally:0:0000:00:999:[ time it was tested. ]:REASON 1
wwally:0:0000:00:999:[ If the game now works ]:REASON 1
wwally:0:0000:00:999:[ please request cheats ]:REASON 1
wwally:0:0000:00:999:[ for it on the cheat ]:REASON 1
wwally:0:0000:00:999:[ forums. ]:REASON 1
; [ Wild Western (set 2) ]
wwester1:0:8620:03:000:Infinite Lives
wwester1:0:0000:00:999:[See the Dip Switch Menu to ]
metadata/hiscore.dat
+3 -1
View File
@@ -2777,7 +2777,9 @@ chinhero3:
0:e12a:1:03:03
asurabus:
asurabusa:
asurabusj:
asurabusja:
asurabusjr:
0:40326d:132:05:14
dynabomb:
metadata/history.dat
+7 -7
View File
@@ -18291,7 +18291,7 @@ F.A.Q. by Kevin Butler A.K.A. War Doc
$end
$info=batsugun,batugnsp,batsugna,
$info=batsugun,batsuguna,batsugunc,batsugunb,batsugunsp,
$bio
Batsugun (c) 02/1993 Toaplan.
@@ -57433,7 +57433,7 @@ Nintendo Famicom (1988, "Ikari 2 - Dogosoken")
$end
$info=dogyuun,
$info=dogyuun,dogyuuna,dogyuunb,dogyuunt,
$bio
Dogyuun (c) 10/1992 Toaplan.
@@ -74054,7 +74054,7 @@ This game is also known as "Round-Up".
$end
$info=fixeight,fixeighb,
$info=fixeight,fixeightk,fixeighth,fixeighttw,fixeighta,fixeightu,fixeightj,fixeightt,fixeightkt,fixeightht,fixeighttwt,fixeightat,fixeightut,fixeightjt,fixeightbl,
$bio
Fixeight (c) 1992 Toaplan.
@@ -84877,7 +84877,7 @@ The US version has the "Recycle It, Don't Trash It!" screen.
$end
$info=mp_gaxe2,
$info=mp_gaxe2,mp_gaxe2a,
$bio
Golden Axe II (c) 1993 Sega.
@@ -89643,7 +89643,7 @@ F.A.Q. by Kevin Butler A.K.A. War Doc
$end
$info=grindstm,grindsta,
$info=grindstm,grindstma,
$bio
Grind Stormer (c) 1992 Toaplan.
@@ -115022,7 +115022,7 @@ You can also get points by punching out enemies. If you can punch out an enemy w
$end
$info=kbash,
$info=kbash,kbashk,kbashp,
$bio
Knuckle Bash (c) 1993 Toaplan.
@@ -242217,7 +242217,7 @@ Directed by : Strong Shima
$end
$info=mp_twc,
$info=mp_twcup,
$bio
Tecmo World Cup (c) 1993 Sega.
metadata/mame2003-plus.xml
+21937 -3345
View File
File diff suppressed because it is too large. Load diff
src/artwork.c
+119 -32
View File
@@ -377,6 +377,7 @@ struct artwork_piece
struct mame_bitmap * yrgbbitmap;
UINT32 * scanlinehint;
UINT8 blendflags;
const struct overlay_piece *overlay_data; /* a driver's overlay: drawn again on a resize */
/* derived/dynamic data */
int intersects_game;
@@ -408,6 +409,9 @@ static int gamescale;
static struct mame_bitmap *uioverlay;
static UINT32 *uioverlayhint;
static struct rectangle uibounds, last_uibounds;
static struct rectangle ui_changed_bounds;
static int ui_changed;
static int full_render_pending; /* after a resize: draw the whole game, not the vector dirty pixels */
static UINT32 *palette_lookup;
@@ -446,6 +450,7 @@ static void alpha_blend_intersecting_rect(struct mame_bitmap *dstbitmap, const s
static void add_intersecting_rect(struct mame_bitmap *dstbitmap, const struct rectangle *dstbounds, struct mame_bitmap *srcbitmap, const struct rectangle *srcbounds);
static void cmy_blend_intersecting_rect(struct mame_bitmap *dstbitmap, struct mame_bitmap *dstyrgbbitmap, const struct rectangle *dstbounds, struct mame_bitmap *srcbitmap, struct mame_bitmap *srcyrgbbitmap, const struct rectangle *srcbounds, UINT8 blendflags);
static int generate_overlay(const struct overlay_piece *list, int width, int height);
static int generate_overlay_bitmap(struct artwork_piece *piece, int width, int height);
static void add_range_to_hint(UINT32 *hintbase, int scanline, int startx, int endx);
@@ -596,7 +601,89 @@ static INLINE UINT32 blend_over(UINT32 game, UINT32 pre, UINT32 yrgb)
to osd_create_display
-------------------------------------------------*/
static int artwork_setup_display(struct osd_create_params *params, UINT32 *rgb_components);
int artwork_create_display(struct osd_create_params *params, UINT32 *rgb_components, const struct artwork_callbacks *callbacks)
{
/* reset UI */
uioverlay = NULL;
uioverlayhint = NULL;
palette_lookup = NULL;
/* first load the artwork; if none, quit now */
artwork_list = NULL;
if (!artwork_load(Machine->gamedrv, params->width, params->height, callbacks))
return 1;
if (!artwork_list && (!callbacks->activate_artwork || !callbacks->activate_artwork(params)))
return osd_create_display(params, rgb_components);
return artwork_setup_display(params, rgb_components);
}
/*-------------------------------------------------
artwork_resize_display - the game's display
changes size while it runs (the vector
resolution): the loaded artwork is kept, the
bitmaps that depend on the size are made again
-------------------------------------------------*/
int artwork_resize_display(struct osd_create_params *params, UINT32 *rgb_components)
{
struct artwork_piece *piece;
if (!artwork_list && !uioverlay)
{
osd_close_display();
return osd_create_display(params, rgb_components);
}
/* free what was made for the old size */
auto_bitmap_free(underlay);
auto_bitmap_free(overlay);
auto_bitmap_free(overlay_yrgb);
auto_bitmap_free(bezel);
auto_bitmap_free(final);
auto_bitmap_free(uioverlay);
auto_free_ptr(uioverlayhint);
underlay = overlay = overlay_yrgb = bezel = final = uioverlay = NULL;
uioverlayhint = NULL;
for (piece = artwork_list; piece; piece = piece->next)
{
auto_bitmap_free(piece->prebitmap);
auto_bitmap_free(piece->yrgbbitmap);
auto_free_ptr(piece->scanlinehint);
piece->prebitmap = piece->yrgbbitmap = NULL;
piece->scanlinehint = NULL;
/* a driver's overlay is drawn at the game's size: draw it again */
if (piece->overlay_data)
{
auto_bitmap_free(piece->rawbitmap);
piece->rawbitmap = NULL;
if (!generate_overlay_bitmap(piece, params->width, params->height))
return 1;
}
}
/* the UI areas were on the old size */
memset(&uibounds, 0, sizeof(uibounds));
memset(&last_uibounds, 0, sizeof(last_uibounds));
memset(&ui_changed_bounds, 0, sizeof(ui_changed_bounds));
ui_changed = 0;
full_render_pending = 1;
osd_close_display();
return artwork_setup_display(params, rgb_components);
}
/*-------------------------------------------------
artwork_setup_display - size the artwork
bitmaps for the display and create it
-------------------------------------------------*/
static int artwork_setup_display(struct osd_create_params *params, UINT32 *rgb_components)
{
int original_width = params->width;
int original_height = params->height;
@@ -605,17 +692,6 @@ int artwork_create_display(struct osd_create_params *params, UINT32 *rgb_compone
UINT32 rgb32_components[3];
struct artwork_piece *piece;
/* reset UI */
uioverlay = NULL;
uioverlayhint = NULL;
/* first load the artwork; if none, quit now */
artwork_list = NULL;
if (!artwork_load(Machine->gamedrv, original_width, original_height, callbacks))
return 1;
if (!artwork_list && (!callbacks->activate_artwork || !callbacks->activate_artwork(params)))
return osd_create_display(params, rgb_components);
/* determine the game bitmap scale factor */
gamescale = options.artwork_res;
if (gamescale < 1 || (params->video_attributes & VIDEO_TYPE_VECTOR))
@@ -798,8 +874,6 @@ void artwork_update_visible_area(struct mame_display *display)
void artwork_update_video_and_audio(struct mame_display *display)
{
static struct rectangle ui_changed_bounds;
static int ui_changed;
int artwork_changed = 0, ui_visible = 0;
/* do nothing if no artwork */
@@ -824,6 +898,13 @@ void artwork_update_video_and_audio(struct mame_display *display)
/* process the artwork and UI only if we're not frameskipping */
if (display->changed_flags & GAME_BITMAP_CHANGED)
{
if (full_render_pending)
{
display->changed_flags &= ~VECTOR_PIXELS_CHANGED;
display->vector_dirty_pixels = NULL;
full_render_pending = 0;
}
/* see if there's any UI to display this frame */
ui_visible = (uibounds.max_x != 0);
@@ -3349,6 +3430,25 @@ static int generate_right_triangle_piece(struct artwork_piece *piece, const stru
the given pieces
-------------------------------------------------*/
static int generate_overlay_bitmap(struct artwork_piece *piece, int width, int height)
{
const struct overlay_piece *list = piece->overlay_data;
/* switch off the type */
switch (list->type & ~OVERLAY_FLAG_MASK)
{
case OVERLAY_TYPE_RECTANGLE:
return generate_rect_piece(piece, list, width, height);
case OVERLAY_TYPE_DISK:
return generate_disk_piece(piece, list, width, height);
case OVERLAY_TYPE_RIGHT_TRIANGLE:
return generate_right_triangle_piece(piece, list, width, height);
}
return 1;
}
static int generate_overlay(const struct overlay_piece *list, int width, int height)
{
struct artwork_piece *piece;
@@ -3368,24 +3468,10 @@ static int generate_overlay(const struct overlay_piece *list, int width, int hei
piece->priority = priority++;
piece->blendflags = list->type & OVERLAY_FLAG_MASK;
piece->tag = list->tag; /* Handle someone using a different tag, for example, cocktail mode */
piece->overlay_data = list;
/* switch off the type */
switch (list->type & ~OVERLAY_FLAG_MASK)
{
case OVERLAY_TYPE_RECTANGLE:
if (!generate_rect_piece(piece, list, width, height))
return 0;
break;
case OVERLAY_TYPE_DISK:
if (!generate_disk_piece(piece, list, width, height))
return 0;
break;
case OVERLAY_TYPE_RIGHT_TRIANGLE:
if (!generate_right_triangle_piece(piece, list, width, height))
return 0;
break;
}
if (!generate_overlay_bitmap(piece, width, height))
return 0;
/* next */
list++;
@@ -3582,8 +3668,9 @@ static int compute_rgb_components(int depth, UINT32 rgb_components[3], UINT32 rg
/* compute a transparent color; this is in the premultiplied space, so alpha is inverted */
transparent_color = ASSEMBLE_ARGB(0xff,0x00,0x00,0x00);
/* allocate a palette lookup */
palette_lookup = auto_malloc(65536 * sizeof(palette_lookup[0]));
/* allocate a palette lookup (once per game: a resize keeps it, as the depth and palette stay) */
if (!palette_lookup)
palette_lookup = auto_malloc(65536 * sizeof(palette_lookup[0]));
/* switch off the depth */
src/artwork.h
+1
View File
@@ -163,6 +163,7 @@ struct overlay_piece
***************************************************************************/
int artwork_create_display(struct osd_create_params *params, UINT32 *rgb_components, const struct artwork_callbacks *callbacks);
int artwork_resize_display(struct osd_create_params *params, UINT32 *rgb_components);
void artwork_update_video_and_audio(struct mame_display *display);
void artwork_override_screenshot_params(struct mame_bitmap **bitmap, struct rectangle *rect, UINT32 *rgb_components);
src/common.c
+42 -1
View File
@@ -971,6 +971,47 @@ void auto_free(void)
}
/*-------------------------------------------------
auto_free_ptr - free one auto_malloc block
before its tag ends, and stop tracking it
(for the buffers that are reallocated while
a game runs, as the vector bitmap)
-------------------------------------------------*/
void auto_free_ptr(void *ptr)
{
int i;
if (!ptr)
return;
for (i = malloc_list_index - 1; i >= 0; i--)
if (malloc_list[i].ptr == ptr)
{
free(ptr);
memmove(&malloc_list[i], &malloc_list[i + 1], (malloc_list_index - i - 1) * sizeof(malloc_list[0]));
malloc_list_index--;
return;
}
}
/*-------------------------------------------------
auto_bitmap_free - free an auto_bitmap_alloc
bitmap before its tag ends
-------------------------------------------------*/
void auto_bitmap_free(struct mame_bitmap *bitmap)
{
if (!bitmap)
return;
/* the line array was allocated before the safety rows were skipped */
auto_free_ptr(bitmap->line - BITMAP_SAFETY);
auto_free_ptr(bitmap);
}
/*-------------------------------------------------
bitmap_alloc - allocate a bitmap at the
current screen depth
@@ -1186,7 +1227,7 @@ static int count_roms(const struct RomModule *romp)
static void fill_random(UINT8 *base, UINT32 length)
{
while (length--)
*base++ = rand();
*base++ = mame_rand_int();
}
src/common.h
+4
View File
@@ -452,6 +452,10 @@ static INLINE int get_resource_tag(void)
/* automatically-freeing memory */
void *auto_malloc(size_t size);
/* free one auto_malloc block (or auto bitmap) before its tag ends */
void auto_free_ptr(void *ptr);
void auto_bitmap_free(struct mame_bitmap *bitmap);
char *auto_strdup(const char *str);
struct mame_bitmap *auto_bitmap_alloc(int width,int height);
struct mame_bitmap *auto_bitmap_alloc_depth(int width,int height,int depth);
src/cpu/h6280/h6280.c
+26
View File
@@ -60,6 +60,7 @@
#include "memory.h"
#include "cpuintrf.h"
#include "state.h"
#include "mamedbg.h"
#include "h6280.h"
@@ -138,6 +139,31 @@ UINT8 H6280_debug_mmr[8];
/*****************************************************************************/
void h6280_init(void)
{
int cpu = cpu_getactivecpu();
state_save_register_UINT32("h6280", cpu, "PPC", &h6280.ppc.d, 1);
state_save_register_UINT32("h6280", cpu, "PC", &h6280.pc.d, 1);
state_save_register_UINT32("h6280", cpu, "SP", &h6280.sp.d, 1);
state_save_register_UINT32("h6280", cpu, "ZP", &h6280.zp.d, 1);
state_save_register_UINT32("h6280", cpu, "EA", &h6280.ea.d, 1);
state_save_register_UINT8("h6280", cpu, "A", &h6280.a, 1);
state_save_register_UINT8("h6280", cpu, "X", &h6280.x, 1);
state_save_register_UINT8("h6280", cpu, "Y", &h6280.y, 1);
state_save_register_UINT8("h6280", cpu, "P", &h6280.p, 1);
state_save_register_UINT8("h6280", cpu, "MMR", h6280.mmr, 8);
state_save_register_UINT8("h6280", cpu, "IRQ_MASK", &h6280.irq_mask, 1);
state_save_register_UINT8("h6280", cpu, "TIMER_STATUS", &h6280.timer_status, 1);
state_save_register_UINT8("h6280", cpu, "TIMER_ACK", &h6280.timer_ack, 1);
state_save_register_int("h6280", cpu, "TIMER_VALUE", &h6280.timer_value);
state_save_register_int("h6280", cpu, "TIMER_LOAD", &h6280.timer_load);
state_save_register_int("h6280", cpu, "EXTRA_CYCLES", &h6280.extra_cycles);
state_save_register_int("h6280", cpu, "NMI_STATE", &h6280.nmi_state);
state_save_register_int("h6280", cpu, "IRQ1_STATE", &h6280.irq_state[0]);
state_save_register_int("h6280", cpu, "IRQ2_STATE", &h6280.irq_state[1]);
state_save_register_int("h6280", cpu, "IRQT_STATE", &h6280.irq_state[2]);
#if LAZY_FLAGS
state_save_register_int("h6280", cpu, "NZ", &h6280.NZ);
#endif
}
void h6280_reset(void *param)
src/cpu/hd6309/hd6309.c
+3
View File
@@ -587,6 +587,8 @@ void hd6309_init(void)
state_save_register_UINT16("hd6309", cpu, "X", &X, 1);
state_save_register_UINT16("hd6309", cpu, "Y", &Y, 1);
state_save_register_UINT16("hd6309", cpu, "V", &V, 1);
state_save_register_UINT16("hd6309", cpu, "D", &D, 1); /* the accumulators A and B */
state_save_register_UINT16("hd6309", cpu, "W", &W, 1); /* the accumulators E and F */
state_save_register_UINT8("hd6309", cpu, "DP", &DP, 1);
state_save_register_UINT8("hd6309", cpu, "CC", &CC, 1);
state_save_register_UINT8("hd6309", cpu, "MD", &MD, 1);
@@ -595,6 +597,7 @@ void hd6309_init(void)
state_save_register_UINT8("hd6309", cpu, "NMI", &hd6309.nmi_state, 1);
state_save_register_UINT8("hd6309", cpu, "IRQ", &hd6309.irq_state[0], 1);
state_save_register_UINT8("hd6309", cpu, "FIRQ", &hd6309.irq_state[1], 1);
state_save_register_int("hd6309", cpu, "extra_cycles", &hd6309.extra_cycles); /* the cycles of an interrupt taken outside the execute loop */
}
/****************************************************************************/
src/cpu/i386/cycles.h
+674
View File
@@ -0,0 +1,674 @@
#pragma once
#ifndef __CYCLES_H__
#define __CYCLES_H__
typedef enum
{
CYCLES_MOV_REG_REG,
CYCLES_MOV_REG_MEM,
CYCLES_MOV_MEM_REG,
CYCLES_MOV_IMM_REG,
CYCLES_MOV_IMM_MEM,
CYCLES_MOV_ACC_MEM,
CYCLES_MOV_MEM_ACC,
CYCLES_MOV_REG_SREG,
CYCLES_MOV_MEM_SREG,
CYCLES_MOV_SREG_REG,
CYCLES_MOV_SREG_MEM,
CYCLES_MOVSX_REG_REG,
CYCLES_MOVSX_MEM_REG,
CYCLES_MOVZX_REG_REG,
CYCLES_MOVZX_MEM_REG,
CYCLES_PUSH_RM,
CYCLES_PUSH_REG_SHORT,
CYCLES_PUSH_SREG,
CYCLES_PUSH_IMM,
CYCLES_PUSHA,
CYCLES_POP_RM,
CYCLES_POP_REG_SHORT,
CYCLES_POP_SREG,
CYCLES_POPA,
CYCLES_XCHG_REG_REG,
CYCLES_XCHG_REG_MEM,
CYCLES_IN,
CYCLES_IN_VAR,
CYCLES_OUT,
CYCLES_OUT_VAR,
CYCLES_LEA,
CYCLES_LDS,
CYCLES_LES,
CYCLES_LFS,
CYCLES_LGS,
CYCLES_LSS,
CYCLES_CLC,
CYCLES_CLD,
CYCLES_CLI,
CYCLES_CLTS,
CYCLES_CMC,
CYCLES_LAHF,
CYCLES_POPF,
CYCLES_PUSHF,
CYCLES_SAHF,
CYCLES_STC,
CYCLES_STD,
CYCLES_STI,
CYCLES_ALU_REG_REG,
CYCLES_ALU_REG_MEM,
CYCLES_ALU_MEM_REG,
CYCLES_ALU_IMM_REG,
CYCLES_ALU_IMM_MEM,
CYCLES_ALU_IMM_ACC,
CYCLES_INC_REG,
CYCLES_INC_MEM,
CYCLES_DEC_REG,
CYCLES_DEC_MEM,
CYCLES_CMP_REG_REG,
CYCLES_CMP_REG_MEM,
CYCLES_CMP_MEM_REG,
CYCLES_CMP_IMM_REG,
CYCLES_CMP_IMM_MEM,
CYCLES_CMP_IMM_ACC,
CYCLES_TEST_REG_REG,
CYCLES_TEST_REG_MEM,
CYCLES_TEST_IMM_REG,
CYCLES_TEST_IMM_MEM,
CYCLES_TEST_IMM_ACC,
CYCLES_NEG_REG,
CYCLES_NEG_MEM,
CYCLES_AAA,
CYCLES_AAS,
CYCLES_DAA,
CYCLES_DAS,
CYCLES_MUL8_ACC_REG,
CYCLES_MUL8_ACC_MEM,
CYCLES_MUL16_ACC_REG,
CYCLES_MUL16_ACC_MEM,
CYCLES_MUL32_ACC_REG,
CYCLES_MUL32_ACC_MEM,
CYCLES_IMUL8_ACC_REG,
CYCLES_IMUL8_ACC_MEM,
CYCLES_IMUL16_ACC_REG,
CYCLES_IMUL16_ACC_MEM,
CYCLES_IMUL32_ACC_REG,
CYCLES_IMUL32_ACC_MEM,
CYCLES_IMUL8_REG_REG,
CYCLES_IMUL8_REG_MEM,
CYCLES_IMUL16_REG_REG,
CYCLES_IMUL16_REG_MEM,
CYCLES_IMUL32_REG_REG,
CYCLES_IMUL32_REG_MEM,
CYCLES_IMUL16_REG_IMM_REG,
CYCLES_IMUL16_MEM_IMM_REG,
CYCLES_IMUL32_REG_IMM_REG,
CYCLES_IMUL32_MEM_IMM_REG,
CYCLES_DIV8_ACC_REG,
CYCLES_DIV8_ACC_MEM,
CYCLES_DIV16_ACC_REG,
CYCLES_DIV16_ACC_MEM,
CYCLES_DIV32_ACC_REG,
CYCLES_DIV32_ACC_MEM,
CYCLES_IDIV8_ACC_REG,
CYCLES_IDIV8_ACC_MEM,
CYCLES_IDIV16_ACC_REG,
CYCLES_IDIV16_ACC_MEM,
CYCLES_IDIV32_ACC_REG,
CYCLES_IDIV32_ACC_MEM,
CYCLES_AAD,
CYCLES_AAM,
CYCLES_CBW,
CYCLES_CWD,
CYCLES_ROTATE_REG,
CYCLES_ROTATE_MEM,
CYCLES_ROTATE_CARRY_REG,
CYCLES_ROTATE_CARRY_MEM,
CYCLES_SHLD_REG,
CYCLES_SHLD_MEM,
CYCLES_SHRD_REG,
CYCLES_SHRD_MEM,
CYCLES_NOT_REG,
CYCLES_NOT_MEM,
CYCLES_CMPS,
CYCLES_INS,
CYCLES_LODS,
CYCLES_MOVS,
CYCLES_OUTS,
CYCLES_SCAS,
CYCLES_STOS,
CYCLES_XLAT,
CYCLES_REP_CMPS_BASE,
CYCLES_REP_INS_BASE,
CYCLES_REP_LODS_BASE,
CYCLES_REP_MOVS_BASE,
CYCLES_REP_OUTS_BASE,
CYCLES_REP_SCAS_BASE,
CYCLES_REP_STOS_BASE,
CYCLES_REP_CMPS,
CYCLES_REP_INS,
CYCLES_REP_LODS,
CYCLES_REP_MOVS,
CYCLES_REP_OUTS,
CYCLES_REP_SCAS,
CYCLES_REP_STOS,
CYCLES_BSF_BASE,
CYCLES_BSF,
CYCLES_BSR_BASE,
CYCLES_BSR,
CYCLES_BT_IMM_REG,
CYCLES_BT_IMM_MEM,
CYCLES_BT_REG_REG,
CYCLES_BT_REG_MEM,
CYCLES_BTC_IMM_REG,
CYCLES_BTC_IMM_MEM,
CYCLES_BTC_REG_REG,
CYCLES_BTC_REG_MEM,
CYCLES_BTR_IMM_REG,
CYCLES_BTR_IMM_MEM,
CYCLES_BTR_REG_REG,
CYCLES_BTR_REG_MEM,
CYCLES_BTS_IMM_REG,
CYCLES_BTS_IMM_MEM,
CYCLES_BTS_REG_REG,
CYCLES_BTS_REG_MEM,
CYCLES_CALL, /* E8 */
CYCLES_CALL_REG, /* FF /2 */
CYCLES_CALL_MEM, /* FF /2 */
CYCLES_CALL_INTERSEG, /* 9A */
CYCLES_CALL_REG_INTERSEG, /* FF /3 */
CYCLES_CALL_MEM_INTERSEG, /* FF /3 */
CYCLES_JMP_SHORT, /* EB */
CYCLES_JMP, /* E9 */
CYCLES_JMP_REG, /* FF /4 */
CYCLES_JMP_MEM, /* FF /4 */
CYCLES_JMP_INTERSEG, /* EA */
CYCLES_JMP_REG_INTERSEG, /* FF /5 */
CYCLES_JMP_MEM_INTERSEG, /* FF /5 */
CYCLES_RET, /* C3 */
CYCLES_RET_IMM, /* C2 */
CYCLES_RET_INTERSEG, /* CB */
CYCLES_RET_IMM_INTERSEG, /* CA */
CYCLES_JCC_DISP8,
CYCLES_JCC_FULL_DISP,
CYCLES_JCC_DISP8_NOBRANCH,
CYCLES_JCC_FULL_DISP_NOBRANCH,
CYCLES_JCXZ,
CYCLES_JCXZ_NOBRANCH,
CYCLES_LOOP,
CYCLES_LOOPZ,
CYCLES_LOOPNZ,
CYCLES_SETCC_REG,
CYCLES_SETCC_MEM,
CYCLES_ENTER,
CYCLES_LEAVE,
CYCLES_INT,
CYCLES_INT3,
CYCLES_INTO_OF1,
CYCLES_INTO_OF0,
CYCLES_BOUND_IN_RANGE,
CYCLES_BOUND_OUT_RANGE,
CYCLES_IRET,
CYCLES_HLT,
CYCLES_MOV_REG_CR0,
CYCLES_MOV_REG_CR2,
CYCLES_MOV_REG_CR3,
CYCLES_MOV_CR_REG,
CYCLES_MOV_REG_DR0_3,
CYCLES_MOV_REG_DR6_7,
CYCLES_MOV_DR6_7_REG,
CYCLES_MOV_DR0_3_REG,
CYCLES_MOV_REG_TR6_7,
CYCLES_MOV_TR6_7_REG,
CYCLES_NOP,
CYCLES_WAIT,
CYCLES_ARPL_REG,
CYCLES_ARPL_MEM,
CYCLES_LAR_REG,
CYCLES_LAR_MEM,
CYCLES_LGDT,
CYCLES_LIDT,
CYCLES_LLDT_REG,
CYCLES_LLDT_MEM,
CYCLES_LMSW_REG,
CYCLES_LMSW_MEM,
CYCLES_LSL_REG,
CYCLES_LSL_MEM,
CYCLES_LTR_REG,
CYCLES_LTR_MEM,
CYCLES_SGDT,
CYCLES_SIDT,
CYCLES_SLDT_REG,
CYCLES_SLDT_MEM,
CYCLES_SMSW_REG,
CYCLES_SMSW_MEM,
CYCLES_STR_REG,
CYCLES_STR_MEM,
CYCLES_VERR_REG,
CYCLES_VERR_MEM,
CYCLES_VERW_REG,
CYCLES_VERW_MEM,
CYCLES_LOCK,
CYCLES_BSWAP,
CYCLES_CMPXCHG8B,
CYCLES_CMPXCHG,
CYCLES_CPUID,
CYCLES_CPUID_EAX1,
CYCLES_INVD,
CYCLES_XADD,
CYCLES_RDTSC,
CYCLES_RSM,
CYCLES_RDMSR,
CYCLES_FABS,
CYCLES_FADD,
CYCLES_FBLD,
CYCLES_FBSTP,
CYCLES_FCHS,
CYCLES_FCLEX,
CYCLES_FCOM,
CYCLES_FCOS,
CYCLES_FDECSTP,
CYCLES_FDISI,
CYCLES_FDIV,
CYCLES_FDIVR,
CYCLES_FENI,
CYCLES_FFREE,
CYCLES_FIADD,
CYCLES_FICOM,
CYCLES_FIDIV,
CYCLES_FILD,
CYCLES_FIMUL,
CYCLES_FINCSTP,
CYCLES_FINIT,
CYCLES_FIST,
CYCLES_FISUB,
CYCLES_FLD,
CYCLES_FLDZ,
CYCLES_FLD1,
CYCLES_FLDL2E,
CYCLES_FLDL2T,
CYCLES_FLDLG2,
CYCLES_FLDLN2,
CYCLES_FLDPI,
CYCLES_FLDCW,
CYCLES_FLDENV,
CYCLES_FMUL,
CYCLES_FNOP,
CYCLES_FPATAN,
CYCLES_FPREM,
CYCLES_FPREM1,
CYCLES_FPTAN,
CYCLES_FRNDINT,
CYCLES_FRSTOR,
CYCLES_FSAVE,
CYCLES_FSCALE,
CYCLES_FSETPM,
CYCLES_FSIN,
CYCLES_FSINCOS,
CYCLES_FSQRT,
CYCLES_FST,
CYCLES_FSTCW,
CYCLES_FSTENV,
CYCLES_FSTSW,
CYCLES_FSUB,
CYCLES_FSUBR,
CYCLES_FTST,
CYCLES_FUCOM,
CYCLES_FXAM,
CYCLES_FXCH,
CYCLES_FXTRACT,
CYCLES_FYL2X,
CYCLES_FYL2XPI,
CYCLES_CMPXCHG_REG_REG_T,
CYCLES_CMPXCHG_REG_REG_F,
CYCLES_CMPXCHG_REG_MEM_T,
CYCLES_CMPXCHG_REG_MEM_F,
CYCLES_XADD_REG_REG,
CYCLES_XADD_REG_MEM,
CYCLES_NUM_OPCODES
} X86_CYCLES;
#define X86_NUM_CPUS 4
#define CPU_CYCLES_I386 0
#define CPU_CYCLES_I486 1
#define CPU_CYCLES_PENTIUM 2
#define CPU_CYCLES_MEDIAGX 3
typedef struct
{
X86_CYCLES op;
UINT8 cpu_cycles[X86_NUM_CPUS][2];
} X86_CYCLE_TABLE;
static const X86_CYCLE_TABLE x86_cycle_table[] =
{
/* opcode rm/pmode */
/* i386 i486 pentium mediagx */
{ CYCLES_MOV_REG_REG, { { 2, 2 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_MOV_REG_MEM, { { 2, 2 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_MOV_MEM_REG, { { 4, 4 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_MOV_IMM_REG, { { 2, 2 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_MOV_IMM_MEM, { { 2, 2 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_MOV_ACC_MEM, { { 2, 2 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_MOV_MEM_ACC, { { 4, 4 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_MOV_REG_SREG, { { 2, 18 }, { 3, 3 }, { 2, 2 }, { 1, 6 } } },
{ CYCLES_MOV_MEM_SREG, { { 5, 19 }, { 9, 9 }, { 3, 3 }, { 1, 6 } } },
{ CYCLES_MOV_SREG_REG, { { 2, 2 }, { 3, 3 }, { 1, 1 }, { 1, 6 } } },
{ CYCLES_MOV_SREG_MEM, { { 2, 2 }, { 3, 3 }, { 1, 1 }, { 1, 6 } } },
{ CYCLES_MOVSX_REG_REG, { { 3, 3 }, { 3, 3 }, { 3, 3 }, { 1, 1 } } },
{ CYCLES_MOVSX_MEM_REG, { { 6, 6 }, { 3, 3 }, { 3, 3 }, { 1, 1 } } },
{ CYCLES_MOVZX_REG_REG, { { 3, 3 }, { 3, 3 }, { 3, 3 }, { 1, 1 } } },
{ CYCLES_MOVZX_MEM_REG, { { 6, 6 }, { 3, 3 }, { 3, 3 }, { 1, 1 } } },
{ CYCLES_PUSH_RM, { { 5, 5 }, { 4, 4 }, { 2, 2 }, { 3, 3 } } },
{ CYCLES_PUSH_REG_SHORT, { { 2, 2 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_PUSH_SREG, { { 2, 2 }, { 3, 3 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_PUSH_IMM, { { 2, 2 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_PUSHA, { { 18, 18 }, { 11, 11 }, { 5, 5 }, { 11, 11 } } },
{ CYCLES_POP_RM, { { 5, 5 }, { 4, 4 }, { 3, 3 }, { 4, 4 } } },
{ CYCLES_POP_REG_SHORT, { { 4, 4 }, { 4, 4 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_POP_SREG, { { 7, 21 }, { 3, 3 }, { 3, 3 }, { 1, 6 } } },
{ CYCLES_POPA, { { 24, 24 }, { 9, 9 }, { 5, 5 }, { 9, 9 } } },
{ CYCLES_XCHG_REG_REG, { { 3, 3 }, { 3, 3 }, { 3, 3 }, { 1, 1 } } },
{ CYCLES_XCHG_REG_MEM, { { 5, 5 }, { 5, 5 }, { 3, 3 }, { 1, 1 } } },
{ CYCLES_IN, { { 12, 26 }, { 14, 27 }, { 7, 19 }, { 8, 8 } } },
{ CYCLES_IN_VAR, { { 13, 27 }, { 14, 27 }, { 7, 19 }, { 8, 8 } } },
{ CYCLES_OUT, { { 10, 24 }, { 16, 29 }, { 12, 24 }, { 14, 14 } } },
{ CYCLES_OUT_VAR, { { 11, 25 }, { 16, 29 }, { 12, 24 }, { 14, 14 } } },
{ CYCLES_LEA, { { 2, 2 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_LDS, { { 7, 22 }, { 6, 12 }, { 4, 4 }, { 4, 9 } } },
{ CYCLES_LES, { { 7, 22 }, { 6, 12 }, { 4, 4 }, { 4, 9 } } },
{ CYCLES_LFS, { { 7, 22 }, { 6, 12 }, { 4, 4 }, { 4, 9 } } },
{ CYCLES_LGS, { { 7, 22 }, { 6, 12 }, { 4, 4 }, { 4, 9 } } },
{ CYCLES_LSS, { { 7, 22 }, { 6, 12 }, { 4, 4 }, { 4, 10 } } },
{ CYCLES_CLC, { { 2, 2 }, { 2, 2 }, { 2, 2 }, { 1, 1 } } },
{ CYCLES_CLD, { { 2, 2 }, { 2, 2 }, { 2, 2 }, { 4, 4 } } },
{ CYCLES_CLI, { { 8, 8 }, { 5, 5 }, { 7, 7 }, { 6, 6 } } },
{ CYCLES_CLTS, { { 6, 6 }, { 7, 7 }, { 10, 10 }, { 7, 7 } } },
{ CYCLES_CMC, { { 2, 2 }, { 2, 2 }, { 2, 2 }, { 3, 3 } } },
{ CYCLES_LAHF, { { 2, 2 }, { 3, 3 }, { 2, 2 }, { 2, 2 } } },
{ CYCLES_POPF, { { 5, 5 }, { 9, 9 }, { 6, 6 }, { 8, 8 } } },
{ CYCLES_PUSHF, { { 4, 4 }, { 4, 4 }, { 9, 9 }, { 2, 2 } } },
{ CYCLES_SAHF, { { 3, 3 }, { 2, 2 }, { 2, 2 }, { 1, 1 } } },
{ CYCLES_STC, { { 2, 2 }, { 2, 2 }, { 2, 2 }, { 1, 1 } } },
{ CYCLES_STD, { { 2, 2 }, { 2, 2 }, { 2, 2 }, { 4, 4 } } },
{ CYCLES_STI, { { 8, 8 }, { 5, 5 }, { 7, 7 }, { 6, 6 } } },
{ CYCLES_ALU_REG_REG, { { 2, 2 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_ALU_REG_MEM, { { 7, 7 }, { 3, 3 }, { 3, 3 }, { 1, 1 } } },
{ CYCLES_ALU_MEM_REG, { { 6, 6 }, { 2, 2 }, { 2, 2 }, { 1, 1 } } },
{ CYCLES_ALU_IMM_REG, { { 2, 2 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_ALU_IMM_MEM, { { 7, 7 }, { 3, 3 }, { 3, 3 }, { 1, 1 } } },
{ CYCLES_ALU_IMM_ACC, { { 2, 2 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_INC_REG, { { 2, 2 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_INC_MEM, { { 6, 6 }, { 3, 3 }, { 3, 3 }, { 1, 1 } } },
{ CYCLES_DEC_REG, { { 2, 2 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_DEC_MEM, { { 6, 6 }, { 3, 3 }, { 3, 3 }, { 1, 1 } } },
{ CYCLES_CMP_REG_REG, { { 2, 2 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_CMP_REG_MEM, { { 5, 5 }, { 2, 2 }, { 2, 2 }, { 1, 1 } } },
{ CYCLES_CMP_MEM_REG, { { 6, 6 }, { 2, 2 }, { 2, 2 }, { 1, 1 } } },
{ CYCLES_CMP_IMM_REG, { { 2, 2 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_CMP_IMM_MEM, { { 5, 5 }, { 2, 2 }, { 2, 2 }, { 1, 1 } } },
{ CYCLES_CMP_IMM_ACC, { { 2, 2 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_TEST_REG_REG, { { 2, 2 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_TEST_REG_MEM, { { 5, 5 }, { 2, 2 }, { 2, 2 }, { 1, 1 } } },
{ CYCLES_TEST_IMM_REG, { { 2, 2 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_TEST_IMM_MEM, { { 5, 5 }, { 2, 2 }, { 2, 2 }, { 1, 1 } } },
{ CYCLES_TEST_IMM_ACC, { { 2, 2 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_NEG_REG, { { 2, 2 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_NEG_MEM, { { 6, 6 }, { 3, 3 }, { 3, 3 }, { 1, 1 } } },
{ CYCLES_AAA, { { 4, 4 }, { 3, 3 }, { 3, 3 }, { 3, 3 } } },
{ CYCLES_AAS, { { 4, 4 }, { 3, 3 }, { 3, 3 }, { 3, 3 } } },
{ CYCLES_DAA, { { 4, 4 }, { 2, 2 }, { 3, 3 }, { 2, 2 } } },
{ CYCLES_DAS, { { 4, 4 }, { 2, 2 }, { 3, 3 }, { 2, 2 } } },
{ CYCLES_MUL8_ACC_REG, { { 17, 17 }, { 13, 13 }, { 11, 11 }, { 4, 4 } } },
{ CYCLES_MUL8_ACC_MEM, { { 20, 20 }, { 13, 13 }, { 11, 11 }, { 4, 4 } } },
{ CYCLES_MUL16_ACC_REG, { { 25, 25 }, { 13, 13 }, { 11, 11 }, { 5, 5 } } },
{ CYCLES_MUL16_ACC_MEM, { { 28, 28 }, { 13, 13 }, { 11, 11 }, { 5, 5 } } },
{ CYCLES_MUL32_ACC_REG, { { 41, 41 }, { 13, 13 }, { 10, 10 }, { 15, 15 } } },
{ CYCLES_MUL32_ACC_MEM, { { 44, 44 }, { 13, 13 }, { 10, 10 }, { 15, 15 } } },
{ CYCLES_IMUL8_ACC_REG, { { 17, 17 }, { 18, 18 }, { 11, 11 }, { 4, 4 } } },
{ CYCLES_IMUL8_ACC_MEM, { { 20, 20 }, { 18, 18 }, { 11, 11 }, { 4, 4 } } },
{ CYCLES_IMUL16_ACC_REG, { { 25, 25 }, { 26, 26 }, { 11, 11 }, { 5, 5 } } },
{ CYCLES_IMUL16_ACC_MEM, { { 28, 28 }, { 26, 26 }, { 11, 11 }, { 5, 5 } } },
{ CYCLES_IMUL32_ACC_REG, { { 41, 41 }, { 42, 42 }, { 10, 10 }, { 15, 15 } } },
{ CYCLES_IMUL32_ACC_MEM, { { 44, 44 }, { 42, 42 }, { 10, 10 }, { 15, 15 } } },
{ CYCLES_IMUL8_REG_REG, { { 17, 17 }, { 13, 13 }, { 10, 10 }, { 4, 4 } } },
{ CYCLES_IMUL8_REG_MEM, { { 20, 20 }, { 13, 13 }, { 10, 10 }, { 4, 4 } } },
{ CYCLES_IMUL16_REG_REG, { { 25, 25 }, { 13, 13 }, { 10, 10 }, { 5, 5 } } },
{ CYCLES_IMUL16_REG_MEM, { { 28, 28 }, { 13, 13 }, { 10, 10 }, { 5, 5 } } },
{ CYCLES_IMUL32_REG_REG, { { 41, 41 }, { 13, 13 }, { 10, 10 }, { 15, 15 } } },
{ CYCLES_IMUL32_REG_MEM, { { 44, 44 }, { 13, 13 }, { 10, 10 }, { 15, 15 } } },
{ CYCLES_IMUL16_REG_IMM_REG,{ { 26, 26 }, { 26, 26 }, { 10, 10 }, { 6, 6 } } },
{ CYCLES_IMUL16_MEM_IMM_REG,{ { 27, 27 }, { 26, 26 }, { 10, 10 }, { 6, 6 } } },
{ CYCLES_IMUL32_REG_IMM_REG,{ { 42, 42 }, { 42, 42 }, { 10, 10 }, { 16, 16 } } },
{ CYCLES_IMUL32_MEM_IMM_REG,{ { 43, 43 }, { 42, 42 }, { 10, 10 }, { 16, 16 } } },
{ CYCLES_DIV8_ACC_REG, { { 14, 14 }, { 16, 16 }, { 17, 17 }, { 20, 20 } } },
{ CYCLES_DIV8_ACC_MEM, { { 17, 17 }, { 16, 16 }, { 17, 17 }, { 20, 20 } } },
{ CYCLES_DIV16_ACC_REG, { { 22, 22 }, { 24, 24 }, { 25, 25 }, { 29, 29 } } },
{ CYCLES_DIV16_ACC_MEM, { { 25, 25 }, { 24, 24 }, { 25, 25 }, { 29, 29 } } },
{ CYCLES_DIV32_ACC_REG, { { 38, 38 }, { 40, 40 }, { 41, 41 }, { 45, 45 } } },
{ CYCLES_DIV32_ACC_MEM, { { 41, 41 }, { 40, 40 }, { 41, 41 }, { 45, 45 } } },
{ CYCLES_IDIV8_ACC_REG, { { 19, 19 }, { 19, 19 }, { 22, 22 }, { 20, 20 } } },
{ CYCLES_IDIV8_ACC_MEM, { { 22, 22 }, { 20, 20 }, { 22, 22 }, { 20, 20 } } },
{ CYCLES_IDIV16_ACC_REG, { { 27, 27 }, { 27, 27 }, { 30, 30 }, { 29, 29 } } },
{ CYCLES_IDIV16_ACC_MEM, { { 30, 30 }, { 28, 28 }, { 30, 30 }, { 29, 29 } } },
{ CYCLES_IDIV32_ACC_REG, { { 43, 43 }, { 43, 43 }, { 46, 46 }, { 45, 45 } } },
{ CYCLES_IDIV32_ACC_MEM, { { 46, 46 }, { 44, 44 }, { 46, 46 }, { 45, 45 } } },
{ CYCLES_AAD, { { 19, 19 }, { 14, 14 }, { 10, 10 }, { 7, 7 } } },
{ CYCLES_AAM, { { 17, 17 }, { 15, 15 }, { 18, 18 }, { 19, 19 } } },
{ CYCLES_CBW, { { 3, 3 }, { 3, 3 }, { 3, 3 }, { 3, 3 } } },
{ CYCLES_CWD, { { 2, 2 }, { 3, 3 }, { 2, 2 }, { 2, 2 } } },
{ CYCLES_ROTATE_REG, { { 3, 3 }, { 3, 3 }, { 1, 1 }, { 2, 2 } } },
{ CYCLES_ROTATE_MEM, { { 7, 7 }, { 4, 4 }, { 3, 3 }, { 2, 2 } } },
{ CYCLES_ROTATE_CARRY_REG, { { 9, 9 }, { 8, 8 }, { 7, 7 }, { 8, 8 } } },
{ CYCLES_ROTATE_CARRY_MEM, { { 10, 10 }, { 9, 9 }, { 8, 8 }, { 8, 8 } } },
{ CYCLES_SHLD_REG, { { 3, 3 }, { 2, 2 }, { 4, 4 }, { 3, 3 } } },
{ CYCLES_SHLD_MEM, { { 7, 7 }, { 3, 3 }, { 4, 4 }, { 6, 6 } } },
{ CYCLES_SHRD_REG, { { 3, 3 }, { 2, 2 }, { 4, 4 }, { 3, 3 } } },
{ CYCLES_SHRD_MEM, { { 7, 7 }, { 3, 3 }, { 4, 4 }, { 6, 6 } } },
{ CYCLES_NOT_REG, { { 2, 2 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_NOT_MEM, { { 6, 6 }, { 3, 3 }, { 3, 3 }, { 1, 1 } } },
{ CYCLES_CMPS, { { 10, 10 }, { 8, 8 }, { 5, 5 }, { 6, 6 } } },
{ CYCLES_INS, { { 15, 29 }, { 17, 30 }, { 9, 22 }, { 11, 11 } } },
{ CYCLES_LODS, { { 5, 5 }, { 5, 5 }, { 2, 2 }, { 3, 3 } } },
{ CYCLES_MOVS, { { 8, 8 }, { 7, 7 }, { 4, 4 }, { 6, 6 } } },
{ CYCLES_OUTS, { { 14, 28 }, { 17, 30 }, { 13, 25 }, { 15, 15 } } },
{ CYCLES_SCAS, { { 8, 8 }, { 6, 6 }, { 4, 4 }, { 2, 2 } } },
{ CYCLES_STOS, { { 5, 5 }, { 5, 5 }, { 3, 3 }, { 2, 2 } } },
{ CYCLES_XLAT, { { 5, 5 }, { 4, 4 }, { 4, 4 }, { 5, 5 } } },
{ CYCLES_REP_CMPS_BASE, { { 5, 5 }, { 0, 0 }, { 0, 0 }, { 11, 11 } } },
{ CYCLES_REP_INS_BASE, { { 14, 8 }, { 0, 0 }, { 0, 0 }, { 17, 17 } } },
{ CYCLES_REP_LODS_BASE, { { 5, 5 }, { 0, 0 }, { 0, 0 }, { 9, 9 } } },
{ CYCLES_REP_MOVS_BASE, { { 8, 8 }, { 0, 0 }, { 0, 0 }, { 12, 12 } } },
{ CYCLES_REP_OUTS_BASE, { { 12, 6 }, { 0, 0 }, { 0, 0 }, { 24, 24 } } },
{ CYCLES_REP_SCAS_BASE, { { 5, 5 }, { 0, 0 }, { 0, 0 }, { 9, 9 } } },
{ CYCLES_REP_STOS_BASE, { { 5, 5 }, { 0, 0 }, { 0, 0 }, { 9, 9 } } },
{ CYCLES_REP_CMPS, { { 5, 5 }, { 8, 8 }, { 5, 5 }, { 4, 4 } } },
{ CYCLES_REP_INS, { { 14, 8 }, { 17, 30 }, { 9, 22 }, { 4, 4 } } },
{ CYCLES_REP_LODS, { { 5, 5 }, { 5, 5 }, { 2, 2 }, { 2, 2 } } },
{ CYCLES_REP_MOVS, { { 8, 8 }, { 7, 7 }, { 4, 4 }, { 2, 2 } } },
{ CYCLES_REP_OUTS, { { 12, 6 }, { 17, 30 }, { 13, 25 }, { 4, 4 } } },
{ CYCLES_REP_SCAS, { { 5, 5 }, { 6, 6 }, { 4, 4 }, { 3, 3 } } },
{ CYCLES_REP_STOS, { { 5, 5 }, { 5, 5 }, { 3, 3 }, { 2, 2 } } },
{ CYCLES_BSF_BASE, { { 11, 11 }, { 6, 6 }, { 6, 6 }, { 4, 4 } } },
{ CYCLES_BSF, { { 3, 3 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_BSR_BASE, { { 9, 9 }, { 6, 6 }, { 7, 7 }, { 4, 4 } } },
{ CYCLES_BSR, { { 3, 3 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_BT_IMM_REG, { { 3, 3 }, { 3, 3 }, { 4, 4 }, { 1, 1 } } },
{ CYCLES_BT_IMM_MEM, { { 6, 6 }, { 6, 6 }, { 4, 4 }, { 1, 1 } } },
{ CYCLES_BT_REG_REG, { { 3, 3 }, { 3, 3 }, { 4, 4 }, { 1, 1 } } },
{ CYCLES_BT_REG_MEM, { { 12, 12 }, { 12, 12 }, { 9, 9 }, { 7, 7 } } },
{ CYCLES_BTC_IMM_REG, { { 6, 6 }, { 6, 6 }, { 7, 7 }, { 2, 2 } } },
{ CYCLES_BTC_IMM_MEM, { { 8, 8 }, { 8, 8 }, { 8, 8 }, { 2, 2 } } },
{ CYCLES_BTC_REG_REG, { { 6, 6 }, { 6, 6 }, { 7, 7 }, { 2, 2 } } },
{ CYCLES_BTC_REG_MEM, { { 13, 13 }, { 13, 13 }, { 13, 13 }, { 8, 8 } } },
{ CYCLES_BTR_IMM_REG, { { 6, 6 }, { 6, 6 }, { 7, 7 }, { 2, 2 } } },
{ CYCLES_BTR_IMM_MEM, { { 8, 8 }, { 8, 8 }, { 8, 8 }, { 2, 2 } } },
{ CYCLES_BTR_REG_REG, { { 6, 6 }, { 6, 6 }, { 7, 7 }, { 2, 2 } } },
{ CYCLES_BTR_REG_MEM, { { 13, 13 }, { 13, 13 }, { 13, 13 }, { 8, 8 } } },
{ CYCLES_BTS_IMM_REG, { { 6, 6 }, { 6, 6 }, { 7, 7 }, { 2, 2 } } },
{ CYCLES_BTS_IMM_MEM, { { 8, 8 }, { 8, 8 }, { 8, 8 }, { 2, 2 } } },
{ CYCLES_BTS_REG_REG, { { 6, 6 }, { 6, 6 }, { 7, 7 }, { 2, 2 } } },
{ CYCLES_BTS_REG_MEM, { { 13, 13 }, { 13, 13 }, { 13, 13 }, { 8, 8 } } },
{ CYCLES_CALL, { { 7, 7 }, { 3, 3 }, { 1, 1 }, { 3, 3 } } },
{ CYCLES_CALL_REG, { { 7, 7 }, { 5, 5 }, { 2, 2 }, { 3, 3 } } },
{ CYCLES_CALL_MEM, { { 10, 10 }, { 5, 5 }, { 2, 2 }, { 4, 4 } } },
{ CYCLES_CALL_INTERSEG, { { 17, 34 }, { 18, 20 }, { 4, 13 }, { 9, 14 } } },
{ CYCLES_CALL_REG_INTERSEG, { { 22, 38 }, { 17, 20 }, { 4, 14 }, { 11, 15 } } },
{ CYCLES_CALL_MEM_INTERSEG, { { 22, 38 }, { 17, 20 }, { 4, 14 }, { 11, 15 } } },
{ CYCLES_JMP_SHORT, { { 7, 7 }, { 3, 3 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_JMP, { { 7, 7 }, { 3, 3 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_JMP_REG, { { 7, 7 }, { 5, 5 }, { 2, 2 }, { 1, 1 } } },
{ CYCLES_JMP_MEM, { { 10, 10 }, { 5, 5 }, { 2, 2 }, { 3, 3 } } },
{ CYCLES_JMP_INTERSEG, { { 12, 27 }, { 17, 19 }, { 3, 3 }, { 8, 12 } } },
{ CYCLES_JMP_REG_INTERSEG, { { 17, 31 }, { 13, 18 }, { 4, 4 }, { 10, 10 } } },
{ CYCLES_JMP_MEM_INTERSEG, { { 17, 31 }, { 13, 18 }, { 4, 4 }, { 10, 13 } } },
{ CYCLES_RET, { { 10, 10 }, { 5, 5 }, { 2, 2 }, { 3, 3 } } },
{ CYCLES_RET_IMM, { { 10, 10 }, { 5, 5 }, { 2, 2 }, { 3, 3 } } },
{ CYCLES_RET_INTERSEG, { { 18, 32 }, { 13, 13 }, { 4, 4 }, { 10, 13 } } },
{ CYCLES_RET_IMM_INTERSEG, { { 18, 32 }, { 14, 14 }, { 4, 4 }, { 10, 13 } } },
{ CYCLES_JCC_DISP8, { { 7, 7 }, { 3, 3 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_JCC_FULL_DISP, { { 7, 7 }, { 3, 3 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_JCC_DISP8_NOBRANCH,{ { 3, 3 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_JCC_FULL_DISP_NOBRANCH,{ { 3, 3 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_JCXZ, { { 9, 9 }, { 1, 1 }, { 1, 1 }, { 2, 2 } } },
{ CYCLES_JCXZ_NOBRANCH, { { 5, 5 }, { 1, 1 }, { 1, 1 }, { 2, 2 } } },
{ CYCLES_LOOP, { { 11, 11 }, { 6, 6 }, { 5, 5 }, { 2, 2 } } },
{ CYCLES_LOOPZ, { { 11, 11 }, { 9, 9 }, { 8, 8 }, { 2, 2 } } },
{ CYCLES_LOOPNZ, { { 11, 11 }, { 9, 9 }, { 8, 8 }, { 2, 2 } } },
{ CYCLES_SETCC_REG, { { 4, 4 }, { 3, 3 }, { 2, 2 }, { 1, 1 } } },
{ CYCLES_SETCC_MEM, { { 5, 5 }, { 4, 4 }, { 2, 2 }, { 1, 1 } } },
{ CYCLES_ENTER, { { 10, 10 }, { 14, 14 }, { 11, 11 }, { 13, 13 } } },
{ CYCLES_LEAVE, { { 4, 4 }, { 5, 5 }, { 3, 3 }, { 1, 1 } } },
{ CYCLES_INT, { { 37, 37 }, { 30, 30 }, { 16, 16 }, { 19, 19 } } },
{ CYCLES_INT3, { { 33, 33 }, { 26, 26 }, { 13, 13 }, { 19, 19 } } },
{ CYCLES_INTO_OF1, { { 35, 35 }, { 28, 28 }, { 13, 13 }, { 19, 19 } } },
{ CYCLES_INTO_OF0, { { 3, 3 }, { 3, 3 }, { 4, 4 }, { 4, 4 } } },
{ CYCLES_BOUND_IN_RANGE, { { 10, 10 }, { 7, 7 }, { 8, 8 }, { 7, 7 } } },
{ CYCLES_BOUND_OUT_RANGE, { { 44, 44 }, { 7, 7 }, { 8, 8 }, { 8, 8 } } },
{ CYCLES_IRET, { { 22, 22 }, { 15, 15 }, { 8, 8 }, { 13, 13 } } },
{ CYCLES_HLT, { { 5, 5 }, { 4, 4 }, { 4, 4 }, { 10, 10 } } },
{ CYCLES_MOV_REG_CR0, { { 11, 11 }, { 16, 16 }, { 16, 16 }, { 20, 18 } } },
{ CYCLES_MOV_REG_CR2, { { 4, 4 }, { 4, 4 }, { 4, 4 }, { 5, 5 } } },
{ CYCLES_MOV_REG_CR3, { { 5, 5 }, { 4, 4 }, { 4, 4 }, { 5, 6 } } },
{ CYCLES_MOV_CR_REG, { { 6, 6 }, { 4, 4 }, { 4, 4 }, { 6, 6 } } },
{ CYCLES_MOV_REG_DR0_3, { { 22, 22 }, { 10, 10 }, { 10, 10 }, { 10, 10 } } },
{ CYCLES_MOV_REG_DR6_7, { { 16, 16 }, { 10, 10 }, { 10, 10 }, { 10, 10 } } },
{ CYCLES_MOV_DR6_7_REG, { { 14, 14 }, { 11, 11 }, { 11, 11 }, { 9, 9 } } },
{ CYCLES_MOV_DR0_3_REG, { { 22, 22 }, { 11, 11 }, { 11, 11 }, { 9, 9 } } },
{ CYCLES_MOV_REG_TR6_7, { { 12, 12 }, { 4, 4 }, { 4, 4 }, { 11, 11 } } },
{ CYCLES_MOV_TR6_7_REG, { { 12, 12 }, { 3, 3 }, { 3, 3 }, { 3, 3 } } },
{ CYCLES_NOP, { { 3, 3 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_WAIT, { { 7, 7 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_ARPL_REG, { { 0, 20 }, { 0, 9 }, { 0, 7 }, { 0, 9 } } },
{ CYCLES_ARPL_MEM, { { 0, 21 }, { 0, 9 }, { 0, 7 }, { 0, 9 } } },
{ CYCLES_LAR_REG, { { 0, 15 }, { 11, 11 }, { 8, 8 }, { 0, 9 } } },
{ CYCLES_LAR_MEM, { { 0, 16 }, { 11, 11 }, { 8, 8 }, { 0, 9 } } },
{ CYCLES_LGDT, { { 11, 11 }, { 11, 11 }, { 6, 6 }, { 10, 10 } } },
{ CYCLES_LIDT, { { 11, 11 }, { 11, 11 }, { 6, 6 }, { 10, 10 } } },
{ CYCLES_LLDT_REG, { { 0, 20 }, { 11, 11 }, { 9, 9 }, { 0, 8 } } },
{ CYCLES_LLDT_MEM, { { 0, 24 }, { 11, 11 }, { 9, 9 }, { 0, 8 } } },
{ CYCLES_LMSW_REG, { { 11, 11 }, { 13, 13 }, { 8, 8 }, { 11, 11 } } },
{ CYCLES_LMSW_MEM, { { 14, 14 }, { 13, 13 }, { 8, 8 }, { 11, 11 } } },
{ CYCLES_LSL_REG, { { 0, 21 }, { 10, 10 }, { 8, 8 }, { 0, 9 } } },
{ CYCLES_LSL_MEM, { { 0, 22 }, { 10, 10 }, { 8, 8 }, { 0, 9 } } },
{ CYCLES_LTR_REG, { { 0, 23 }, { 20, 20 }, { 10, 10 }, { 0, 9 } } },
{ CYCLES_LTR_MEM, { { 0, 27 }, { 20, 20 }, { 10, 10 }, { 0, 9 } } },
{ CYCLES_SGDT, { { 9, 9 }, { 10, 10 }, { 4, 4 }, { 6, 6 } } },
{ CYCLES_SIDT, { { 9, 9 }, { 10, 10 }, { 4, 4 }, { 6, 6 } } },
{ CYCLES_SLDT_REG, { { 0, 2 }, { 2, 2 }, { 2, 2 }, { 0, 1 } } },
{ CYCLES_SLDT_MEM, { { 0, 2 }, { 3, 3 }, { 2, 2 }, { 0, 1 } } },
{ CYCLES_SMSW_REG, { { 2, 2 }, { 2, 2 }, { 4, 4 }, { 4, 4 } } },
{ CYCLES_SMSW_MEM, { { 2, 2 }, { 3, 3 }, { 4, 4 }, { 4, 4 } } },
{ CYCLES_STR_REG, { { 0, 2 }, { 2, 2 }, { 2, 2 }, { 0, 3 } } },
{ CYCLES_STR_MEM, { { 0, 2 }, { 3, 3 }, { 2, 2 }, { 0, 3 } } },
{ CYCLES_VERR_REG, { { 0, 10 }, { 11, 11 }, { 7, 7 }, { 0, 8 } } },
{ CYCLES_VERR_MEM, { { 0, 11 }, { 11, 11 }, { 7, 7 }, { 0, 8 } } },
{ CYCLES_VERW_REG, { { 0, 15 }, { 11, 11 }, { 7, 7 }, { 0, 8 } } },
{ CYCLES_VERW_MEM, { { 0, 16 }, { 11, 11 }, { 7, 7 }, { 0, 8 } } },
{ CYCLES_LOCK, { { 0, 0 }, { 1, 1 }, { 1, 1 }, { 1, 1 } } },
/* i486+ */
{ CYCLES_BSWAP, { { 0, 0 }, { 1, 1 }, { 1, 1 }, { 6, 6 } } },
{ CYCLES_CMPXCHG, { { 0, 0 }, { 6, 6 }, { 5, 5 }, { 6, 6 } } },
{ CYCLES_INVD, { { 0, 0 }, { 4, 4 }, { 15, 15 }, { 20, 20 } } },
{ CYCLES_XADD, { { 0, 0 }, { 4, 4 }, { 4, 4 }, { 2, 2 } } },
/* Pentium+ */
{ CYCLES_CMPXCHG8B, { { 0, 0 }, { 0, 0 }, { 10, 10 }, { 6, 6 } } },
{ CYCLES_CPUID, { { 0, 0 }, { 0, 0 }, { 14, 14 }, { 12, 12 } } },
{ CYCLES_CPUID_EAX1, { { 0, 0 }, { 0, 0 }, { 14, 14 }, { 12, 12 } } },
{ CYCLES_RDTSC, { { 0, 0 }, { 0, 0 }, { 20, 20 }, { 1, 1 } } },
{ CYCLES_RSM, { { 0, 0 }, { 0, 0 }, { 82, 82 }, { 57, 57 } } },
{ CYCLES_RDMSR, { { 0, 0 }, { 0, 0 }, { 20, 20 }, { 1, 1 } } },
/* FPU */
{ CYCLES_FABS, { { 0, 0 }, { 3, 3 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_FADD, { { 0, 0 }, { 8, 8 }, { 3, 3 }, { 1, 1 } } },
{ CYCLES_FBLD, { { 0, 0 }, { 70, 70 }, { 48, 48 }, { 1, 1 } } },
{ CYCLES_FBSTP, { { 0, 0 }, {172,172 }, {148,148 }, { 1, 1 } } },
{ CYCLES_FCHS, { { 0, 0 }, { 6, 6 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_FCLEX, { { 0, 0 }, { 7, 7 }, { 9, 9 }, { 1, 1 } } },
{ CYCLES_FCOM, { { 0, 0 }, { 4, 4 }, { 4, 4 }, { 1, 1 } } },
{ CYCLES_FCOS, { { 0, 0 }, {255,255 }, {124,124 }, { 1, 1 } } },
{ CYCLES_FDECSTP, { { 0, 0 }, { 3, 3 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_FDISI, { { 0, 0 }, { 3, 3 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_FDIV, { { 0, 0 }, { 73, 73 }, { 39, 39 }, { 1, 1 } } },
{ CYCLES_FDIVR, { { 0, 0 }, { 73, 73 }, { 39, 39 }, { 1, 1 } } },
{ CYCLES_FENI, { { 0, 0 }, { 3, 3 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_FFREE, { { 0, 0 }, { 3, 3 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_FIADD, { { 0, 0 }, { 20, 20 }, { 7, 7 }, { 1, 1 } } },
{ CYCLES_FICOM, { { 0, 0 }, { 16, 16 }, { 8, 8 }, { 1, 1 } } },
{ CYCLES_FIDIV, { { 0, 0 }, { 85, 85 }, { 42, 42 }, { 1, 1 } } },
{ CYCLES_FILD, { { 0, 0 }, { 13, 13 }, { 3, 3 }, { 1, 1 } } },
{ CYCLES_FIMUL, { { 0, 0 }, { 23, 23 }, { 7, 7 }, { 1, 1 } } },
{ CYCLES_FINCSTP, { { 0, 0 }, { 3, 3 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_FINIT, { { 0, 0 }, { 17, 17 }, { 16, 16 }, { 1, 1 } } },
{ CYCLES_FIST, { { 0, 0 }, { 29, 29 }, { 6, 6 }, { 1, 1 } } },
{ CYCLES_FISUB, { { 0, 0 }, { 20, 20 }, { 7, 7 }, { 1, 1 } } },
{ CYCLES_FLD, { { 0, 0 }, { 4, 4 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_FLDZ, { { 0, 0 }, { 4, 4 }, { 2, 2 }, { 1, 1 } } },
{ CYCLES_FLD1, { { 0, 0 }, { 4, 4 }, { 2, 2 }, { 1, 1 } } },
{ CYCLES_FLDL2E, { { 0, 0 }, { 8, 8 }, { 5, 5 }, { 1, 1 } } },
{ CYCLES_FLDL2T, { { 0, 0 }, { 8, 8 }, { 5, 5 }, { 1, 1 } } },
{ CYCLES_FLDLG2, { { 0, 0 }, { 8, 8 }, { 5, 5 }, { 1, 1 } } },
{ CYCLES_FLDLN2, { { 0, 0 }, { 8, 8 }, { 5, 5 }, { 1, 1 } } },
{ CYCLES_FLDPI, { { 0, 0 }, { 8, 8 }, { 5, 5 }, { 1, 1 } } },
{ CYCLES_FLDCW, { { 0, 0 }, { 4, 4 }, { 7, 7 }, { 1, 1 } } },
{ CYCLES_FLDENV, { { 0, 0 }, { 44, 44 }, { 37, 37 }, { 1, 1 } } },
{ CYCLES_FMUL, { { 0, 0 }, { 16, 16 }, { 3, 3 }, { 1, 1 } } },
{ CYCLES_FNOP, { { 0, 0 }, { 3, 3 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_FPATAN, { { 0, 0 }, {218,218 }, {173,173 }, { 1, 1 } } },
{ CYCLES_FPREM, { { 0, 0 }, { 70, 70 }, { 16, 16 }, { 1, 1 } } },
{ CYCLES_FPREM1, { { 0, 0 }, { 72, 72 }, { 20, 20 }, { 1, 1 } } },
{ CYCLES_FPTAN, { { 0, 0 }, {200,200 }, {173,173 }, { 1, 1 } } },
{ CYCLES_FRNDINT, { { 0, 0 }, { 21, 21 }, { 9, 9 }, { 1, 1 } } },
{ CYCLES_FRSTOR, { { 0, 0 }, {131,131 }, { 75, 75 }, { 1, 1 } } },
{ CYCLES_FSAVE, { { 0, 0 }, {154,154 }, {127,127 }, { 1, 1 } } },
{ CYCLES_FSCALE, { { 0, 0 }, { 30, 30 }, { 20, 20 }, { 1, 1 } } },
{ CYCLES_FSETPM, { { 0, 0 }, { 3, 3 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_FSIN, { { 0, 0 }, {255,255 }, {126,126 }, { 1, 1 } } },
{ CYCLES_FSINCOS, { { 0, 0 }, {255,255 }, {137,137 }, { 1, 1 } } },
{ CYCLES_FSQRT, { { 0, 0 }, { 83, 83 }, { 70, 70 }, { 1, 1 } } },
{ CYCLES_FST, { { 0, 0 }, { 3, 3 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_FSTCW, { { 0, 0 }, { 3, 3 }, { 2, 2 }, { 1, 1 } } },
{ CYCLES_FSTENV, { { 0, 0 }, { 67, 67 }, { 48, 48 }, { 1, 1 } } },
{ CYCLES_FSTSW, { { 0, 0 }, { 3, 3 }, { 2, 2 }, { 1, 1 } } },
{ CYCLES_FSUB, { { 0, 0 }, { 8, 8 }, { 3, 3 }, { 1, 1 } } },
{ CYCLES_FSUBR, { { 0, 0 }, { 8, 8 }, { 3, 3 }, { 1, 1 } } },
{ CYCLES_FTST, { { 0, 0 }, { 4, 4 }, { 4, 4 }, { 1, 1 } } },
{ CYCLES_FUCOM, { { 0, 0 }, { 4, 4 }, { 4, 4 }, { 1, 1 } } },
{ CYCLES_FXAM, { { 0, 0 }, { 8, 8 }, { 21, 21 }, { 1, 1 } } },
{ CYCLES_FXCH, { { 0, 0 }, { 4, 4 }, { 1, 1 }, { 1, 1 } } },
{ CYCLES_FXTRACT, { { 0, 0 }, { 16, 16 }, { 13, 13 }, { 1, 1 } } },
{ CYCLES_FYL2X, { { 0, 0 }, {196,196 }, {111,111 }, { 1, 1 } } },
{ CYCLES_FYL2XPI, { { 0, 0 }, {171,171 }, {103,103 }, { 1, 1 } } },
{ CYCLES_CMPXCHG_REG_REG_T, { { 0, 0 }, { 6, 6 }, { 6, 6 }, { 6, 6 } } },
{ CYCLES_CMPXCHG_REG_REG_F, { { 0, 0 }, { 9, 9 }, { 9, 9 }, { 9, 9 } } },
{ CYCLES_CMPXCHG_REG_MEM_T, { { 0, 0 }, { 7, 7 }, { 7, 7 }, { 7, 7 } } },
{ CYCLES_CMPXCHG_REG_MEM_F, { { 0, 0 }, { 10, 10 }, { 10, 10 }, { 10, 10 } } },
};
#endif /* __CYCLES_H__ */
src/cpu/i386/i386.c
+868
View File
@@ -0,0 +1,868 @@
/*
Intel 386 emulator
Written by Ville Linde
Currently supports:
Intel 386
Intel 486
Intel Pentium
Cyrix MediaGX
*/
#include <string.h>
#include "driver.h"
#include "state.h"
#include "i386priv.h"
#include "i386.h"
#include "mamedbg.h"
int i386_ICount;
/* the 0.139 core stops on what it does not implement; here it is logged once */
static void i386_fatal(const char *fmt, ...)
{
static int reported;
if (!reported)
{
char buf[256];
va_list va;
va_start(va, fmt);
vsprintf(buf, fmt, va);
va_end(va);
log_cb(RETRO_LOG_ERROR, LOGPRE "%s\n", buf);
reported = 1;
}
}
/* seems to be defined on mingw-gcc */
#undef i386
int i386_parity_table[256];
MODRM_TABLE i386_MODRM_table[256];
/*************************************************************************/
#define INT_DEBUG 1
static void i386_load_protected_mode_segment(i386_state *cpustate, I386_SREG *seg )
{
UINT32 v1,v2;
UINT32 base, limit;
int entry;
if ( seg->selector & 0x4 )
{
base = cpustate->ldtr.base;
limit = cpustate->ldtr.limit;
} else {
base = cpustate->gdtr.base;
limit = cpustate->gdtr.limit;
}
if (limit == 0 || seg->selector + 7 > limit)
return;
entry = seg->selector & ~0x7;
v1 = READ32(cpustate, base + entry );
v2 = READ32(cpustate, base + entry + 4 );
seg->flags = (v2 >> 8) & 0xf0ff;
seg->base = (v2 & 0xff000000) | ((v2 & 0xff) << 16) | ((v1 >> 16) & 0xffff);
seg->limit = (v2 & 0xf0000) | (v1 & 0xffff);
if (seg->flags & 0x8000)
seg->limit = (seg->limit << 12) | 0xfff;
seg->d = (seg->flags & 0x4000) ? 1 : 0;
}
static void i386_load_segment_descriptor(i386_state *cpustate, int segment )
{
if (PROTECTED_MODE)
{
if (!V8086_MODE)
i386_load_protected_mode_segment(cpustate, &cpustate->sreg[segment] );
else
{
cpustate->sreg[segment].base = cpustate->sreg[segment].selector << 4;
cpustate->sreg[segment].limit = 0xffff;
cpustate->sreg[segment].flags = (segment == CS) ? 0x009a : 0x0092;
}
}
else
{
cpustate->sreg[segment].base = cpustate->sreg[segment].selector << 4;
if( segment == CS && !cpustate->performed_intersegment_jump )
cpustate->sreg[segment].base |= 0xfff00000;
}
}
static UINT32 get_flags(i386_state *cpustate)
{
UINT32 f = 0x2;
f |= cpustate->CF;
f |= cpustate->PF << 2;
f |= cpustate->AF << 4;
f |= cpustate->ZF << 6;
f |= cpustate->SF << 7;
f |= cpustate->TF << 8;
f |= cpustate->IF << 9;
f |= cpustate->DF << 10;
f |= cpustate->OF << 11;
f |= cpustate->IOP1 << 12;
f |= cpustate->IOP2 << 13;
f |= cpustate->NT << 14;
return (cpustate->eflags & cpustate->eflags_mask) | (f & 0xffff);
}
static void set_flags(i386_state *cpustate, UINT32 f )
{
cpustate->CF = (f & 0x1) ? 1 : 0;
cpustate->PF = (f & 0x4) ? 1 : 0;
cpustate->AF = (f & 0x10) ? 1 : 0;
cpustate->ZF = (f & 0x40) ? 1 : 0;
cpustate->SF = (f & 0x80) ? 1 : 0;
cpustate->TF = (f & 0x100) ? 1 : 0;
cpustate->IF = (f & 0x200) ? 1 : 0;
cpustate->DF = (f & 0x400) ? 1 : 0;
cpustate->OF = (f & 0x800) ? 1 : 0;
cpustate->IOP1 = (f & 0x1000) ? 1 : 0;
cpustate->IOP2 = (f & 0x2000) ? 1 : 0;
cpustate->NT = (f & 0x4000) ? 1 : 0;
cpustate->eflags = f & cpustate->eflags_mask;
}
static void sib_byte(i386_state *cpustate,UINT8 mod, UINT32* out_ea, UINT8* out_segment)
{
UINT32 ea = 0;
UINT8 segment = 0;
UINT8 scale, i, base;
UINT8 sib = FETCH(cpustate);
scale = (sib >> 6) & 0x3;
i = (sib >> 3) & 0x7;
base = sib & 0x7;
switch( base )
{
case 0: ea = REG32(EAX); segment = DS; break;
case 1: ea = REG32(ECX); segment = DS; break;
case 2: ea = REG32(EDX); segment = DS; break;
case 3: ea = REG32(EBX); segment = DS; break;
case 4: ea = REG32(ESP); segment = SS; break;
case 5:
if( mod == 0 ) {
ea = FETCH32(cpustate);
segment = DS;
} else if( mod == 1 ) {
ea = REG32(EBP);
segment = SS;
} else if( mod == 2 ) {
ea = REG32(EBP);
segment = SS;
}
break;
case 6: ea = REG32(ESI); segment = DS; break;
case 7: ea = REG32(EDI); segment = DS; break;
}
switch( i )
{
case 0: ea += REG32(EAX) * (1 << scale); break;
case 1: ea += REG32(ECX) * (1 << scale); break;
case 2: ea += REG32(EDX) * (1 << scale); break;
case 3: ea += REG32(EBX) * (1 << scale); break;
case 4: break;
case 5: ea += REG32(EBP) * (1 << scale); break;
case 6: ea += REG32(ESI) * (1 << scale); break;
case 7: ea += REG32(EDI) * (1 << scale); break;
}
*out_ea = ea;
*out_segment = segment;
}
static void modrm_to_EA(i386_state *cpustate,UINT8 mod_rm, UINT32* out_ea, UINT8* out_segment)
{
INT8 disp8;
INT16 disp16;
INT32 disp32;
UINT8 mod = (mod_rm >> 6) & 0x3;
UINT8 rm = mod_rm & 0x7;
UINT32 ea;
UINT8 segment;
if( mod_rm >= 0xc0 )
i386_fatal("i386: Called modrm_to_EA with modrm value %02X !",mod_rm);
if( cpustate->address_size ) {
switch( rm )
{
default:
case 0: ea = REG32(EAX); segment = DS; break;
case 1: ea = REG32(ECX); segment = DS; break;
case 2: ea = REG32(EDX); segment = DS; break;
case 3: ea = REG32(EBX); segment = DS; break;
case 4: sib_byte(cpustate, mod, &ea, &segment ); break;
case 5:
if( mod == 0 ) {
ea = FETCH32(cpustate); segment = DS;
} else {
ea = REG32(EBP); segment = SS;
}
break;
case 6: ea = REG32(ESI); segment = DS; break;
case 7: ea = REG32(EDI); segment = DS; break;
}
if( mod == 1 ) {
disp8 = FETCH(cpustate);
ea += (INT32)disp8;
} else if( mod == 2 ) {
disp32 = FETCH32(cpustate);
ea += disp32;
}
if( cpustate->segment_prefix )
segment = cpustate->segment_override;
*out_ea = ea;
*out_segment = segment;
} else {
switch( rm )
{
default:
case 0: ea = REG16(BX) + REG16(SI); segment = DS; break;
case 1: ea = REG16(BX) + REG16(DI); segment = DS; break;
case 2: ea = REG16(BP) + REG16(SI); segment = SS; break;
case 3: ea = REG16(BP) + REG16(DI); segment = SS; break;
case 4: ea = REG16(SI); segment = DS; break;
case 5: ea = REG16(DI); segment = DS; break;
case 6:
if( mod == 0 ) {
ea = FETCH16(cpustate); segment = DS;
} else {
ea = REG16(BP); segment = SS;
}
break;
case 7: ea = REG16(BX); segment = DS; break;
}
if( mod == 1 ) {
disp8 = FETCH(cpustate);
ea += (INT32)disp8;
} else if( mod == 2 ) {
disp16 = FETCH16(cpustate);
ea += (INT32)disp16;
}
if( cpustate->segment_prefix )
segment = cpustate->segment_override;
*out_ea = ea & 0xffff;
*out_segment = segment;
}
}
static UINT32 GetNonTranslatedEA(i386_state *cpustate,UINT8 modrm)
{
UINT8 segment;
UINT32 ea;
modrm_to_EA(cpustate, modrm, &ea, &segment );
return ea;
}
static UINT32 GetEA(i386_state *cpustate,UINT8 modrm)
{
UINT8 segment;
UINT32 ea;
modrm_to_EA(cpustate, modrm, &ea, &segment );
return i386_translate(cpustate, segment, ea );
}
static void i386_trap(i386_state *cpustate,int irq, int irq_gate)
{
/* I386 Interrupts/Traps/Faults:
*
* 0x00 Divide by zero
* 0x01 Debug exception
* 0x02 NMI
* 0x03 Int3
* 0x04 Overflow
* 0x05 Array bounds check
* 0x06 Illegal Opcode
* 0x07 FPU not available
* 0x08 Double fault
* 0x09 Coprocessor segment overrun
* 0x0a Invalid task state
* 0x0b Segment not present
* 0x0c Stack exception
* 0x0d General Protection Fault
* 0x0e Page fault
* 0x0f Reserved
* 0x10 Coprocessor error
*/
UINT32 v1, v2;
UINT32 offset;
UINT16 segment;
int entry = irq * (PROTECTED_MODE ? 8 : 4);
/* Check if IRQ is out of IDTR's bounds */
if( entry > cpustate->idtr.limit ) {
i386_fatal("I386 Interrupt: IRQ out of IDTR bounds (IRQ: %d, IDTR Limit: %d)", irq, cpustate->idtr.limit);
}
if( !(PROTECTED_MODE) )
{
/* 16-bit */
PUSH16(cpustate, get_flags(cpustate) & 0xffff );
PUSH16(cpustate, cpustate->sreg[CS].selector );
PUSH16(cpustate, cpustate->eip );
cpustate->sreg[CS].selector = READ16(cpustate, cpustate->idtr.base + entry + 2 );
cpustate->eip = READ16(cpustate, cpustate->idtr.base + entry );
/* Interrupts that vector through either interrupt gates or trap gates cause TF */
/* (the trap flag) to be reset after the current value of TF is saved on the stack as part of EFLAGS. */
cpustate->TF = 0;
if (irq_gate)
{
cpustate->IF = 0;
}
}
else
{
int type;
/* 32-bit */
v1 = READ32(cpustate, cpustate->idtr.base + entry );
v2 = READ32(cpustate, cpustate->idtr.base + entry + 4 );
offset = (v2 & 0xffff0000) | (v1 & 0xffff);
segment = (v1 >> 16) & 0xffff;
type = (v2>>8) & 0x1F;
if(type != 0x0e && type != 0x0f) /* if not 386 interrupt or trap gate */
{
PUSH16(cpustate, get_flags(cpustate) & 0xffff );
PUSH16(cpustate, cpustate->sreg[CS].selector );
PUSH16(cpustate, cpustate->eip );
}
else
{
PUSH32(cpustate, get_flags(cpustate) & 0x00fcffff );
PUSH32(cpustate, cpustate->sreg[CS].selector );
PUSH32(cpustate, cpustate->eip );
}
cpustate->sreg[CS].selector = segment;
cpustate->eip = offset;
/* Interrupts that vector through either interrupt gates or trap gates cause TF */
/* (the trap flag) to be reset after the current value of TF is saved on the stack as part of EFLAGS. */
if ((type == 14) || (type==15))
cpustate->TF = 0;
if (type == 14)
{
cpustate->IF = 0;
}
}
i386_load_segment_descriptor(cpustate,CS);
CHANGE_PC(cpustate,cpustate->eip);
}
static void i386_check_irq_line(i386_state *cpustate)
{
/* Check if the interrupts are enabled */
if ( (cpustate->irq_state) && cpustate->IF )
{
i386_ICount -= 2;
i386_trap(cpustate,cpustate->irq_callback(0), 1);
}
}
#include "cycles.h"
static UINT8 *cycle_table_rm[X86_NUM_CPUS];
static UINT8 *cycle_table_pm[X86_NUM_CPUS];
#define CYCLES_NUM(x) (i386_ICount -= (x))
static INLINE void CYCLES(i386_state *cpustate,int x)
{
if (PROTECTED_MODE)
{
i386_ICount -= cpustate->cycle_table_pm[x];
}
else
{
i386_ICount -= cpustate->cycle_table_rm[x];
}
}
static INLINE void CYCLES_RM(i386_state *cpustate,int modrm, int r, int m)
{
if (modrm >= 0xc0)
{
if (PROTECTED_MODE)
{
i386_ICount -= cpustate->cycle_table_pm[r];
}
else
{
i386_ICount -= cpustate->cycle_table_rm[r];
}
}
else
{
if (PROTECTED_MODE)
{
i386_ICount -= cpustate->cycle_table_pm[m];
}
else
{
i386_ICount -= cpustate->cycle_table_rm[m];
}
}
}
static UINT8 cycle_tables[X86_NUM_CPUS][2][CYCLES_NUM_OPCODES];
static void build_cycle_table(void)
{
int i, j;
for (j=0; j < X86_NUM_CPUS; j++)
{
cycle_table_rm[j] = cycle_tables[j][0];
cycle_table_pm[j] = cycle_tables[j][1];
for (i=0; i < sizeof(x86_cycle_table)/sizeof(X86_CYCLE_TABLE); i++)
{
int opcode = x86_cycle_table[i].op;
cycle_table_rm[j][opcode] = x86_cycle_table[i].cpu_cycles[j][0];
cycle_table_pm[j][opcode] = x86_cycle_table[i].cpu_cycles[j][1];
}
}
}
/* Forward declarations */
static void I386OP(decode_opcode)(i386_state *cpustate);
static void I386OP(decode_two_byte)(i386_state *cpustate);
#include "i386ops.c"
#include "i386op16.c"
#include "i386op32.c"
#include "i486ops.c"
#include "pentops.c"
#include "x87ops.c"
#include "i386ops.h"
static void I386OP(decode_opcode)(i386_state *cpustate)
{
cpustate->opcode = FETCH(cpustate);
if( cpustate->operand_size )
cpustate->opcode_table1_32[cpustate->opcode](cpustate);
else
cpustate->opcode_table1_16[cpustate->opcode](cpustate);
}
/* Two-byte opcode prefix */
static void I386OP(decode_two_byte)(i386_state *cpustate)
{
cpustate->opcode = FETCH(cpustate);
if( cpustate->operand_size )
cpustate->opcode_table2_32[cpustate->opcode](cpustate);
else
cpustate->opcode_table2_16[cpustate->opcode](cpustate);
}
/*************************************************************************/
static void build_opcode_table(i386_state *cpustate, UINT32 features)
{
int i;
for (i=0; i < 256; i++)
{
cpustate->opcode_table1_16[i] = I386OP(invalid);
cpustate->opcode_table1_32[i] = I386OP(invalid);
cpustate->opcode_table2_16[i] = I386OP(invalid);
cpustate->opcode_table2_32[i] = I386OP(invalid);
}
for (i=0; i < sizeof(x86_opcode_table)/sizeof(X86_OPCODE); i++)
{
const X86_OPCODE *op = &x86_opcode_table[i];
if ((op->flags & features))
{
if (op->flags & OP_2BYTE)
{
cpustate->opcode_table2_32[op->opcode] = op->handler32;
cpustate->opcode_table2_16[op->opcode] = op->handler16;
}
else
{
cpustate->opcode_table1_32[op->opcode] = op->handler32;
cpustate->opcode_table1_16[op->opcode] = op->handler16;
}
}
}
}
/*************************************************************************
The interface of the CPU core (MAME 0.78 style): one context, copied
in and out by the CPU switch
*************************************************************************/
static i386_state I;
static void i386_postload(void)
{
i386_state *cpustate = &I;
int i;
for (i = 0; i < 6; i++)
i386_load_segment_descriptor(cpustate,i);
CHANGE_PC(cpustate,cpustate->eip);
}
/* the fast memory regions of the driver */
static struct
{
UINT32 start, end;
UINT8 *base;
int flags;
} i386_fastmem[I386_FASTMEM_MAX];
static int i386_fastmem_count;
void i386_set_fastmem(UINT32 start, UINT32 end, UINT8 *base, int flags)
{
if (i386_fastmem_count < I386_FASTMEM_MAX)
{
i386_fastmem[i386_fastmem_count].start = start;
i386_fastmem[i386_fastmem_count].end = end;
i386_fastmem[i386_fastmem_count].base = base;
i386_fastmem[i386_fastmem_count].flags = flags;
i386_fastmem_count++;
}
/* empty the caches */
memset(I.fast_size, 0, sizeof(I.fast_size));
}
/* a miss of the cache: the region of the address, cached; NULL if none */
static UINT8 *i386_fast_lookup(i386_state *cpustate, UINT32 address, UINT32 len, int kind)
{
int i;
for (i = 0; i < i386_fastmem_count; i++)
{
if ((i386_fastmem[i].flags & (1 << kind)) && address >= i386_fastmem[i].start &&
address <= i386_fastmem[i].end && i386_fastmem[i].end - address >= len - 1)
{
cpustate->fast_start[kind] = i386_fastmem[i].start;
cpustate->fast_size[kind] = i386_fastmem[i].end - i386_fastmem[i].start + 1;
cpustate->fast_base[kind] = i386_fastmem[i].base;
return i386_fastmem[i].base + (address - i386_fastmem[i].start);
}
}
return NULL;
}
void i386_init(void)
{
int i, j;
static const int regs8[8] = {AL,CL,DL,BL,AH,CH,DH,BH};
static const int regs16[8] = {AX,CX,DX,BX,SP,BP,SI,DI};
static const int regs32[8] = {EAX,ECX,EDX,EBX,ESP,EBP,ESI,EDI};
int cpu = cpu_getactivecpu();
i386_state *cpustate = &I;
static const char *const sregname[6] = { "es", "cs", "ss", "ds", "fs", "gs" };
i386_fastmem_count = 0;
memset(I.fast_size, 0, sizeof(I.fast_size));
build_cycle_table();
for( i=0; i < 256; i++ ) {
int c=0;
for( j=0; j < 8; j++ ) {
if( i & (1 << j) )
c++;
}
i386_parity_table[i] = ~(c & 0x1) & 0x1;
}
for( i=0; i < 256; i++ ) {
i386_MODRM_table[i].reg.b = regs8[(i >> 3) & 0x7];
i386_MODRM_table[i].reg.w = regs16[(i >> 3) & 0x7];
i386_MODRM_table[i].reg.d = regs32[(i >> 3) & 0x7];
i386_MODRM_table[i].rm.b = regs8[i & 0x7];
i386_MODRM_table[i].rm.w = regs16[i & 0x7];
i386_MODRM_table[i].rm.d = regs32[i & 0x7];
}
state_save_register_UINT32("i386", cpu, "reg", cpustate->reg.d, 8);
for (i = 0; i < 6; i++)
{
char name[16];
sprintf(name, "%s_sel", sregname[i]);
state_save_register_UINT16("i386", cpu, name, &cpustate->sreg[i].selector, 1);
sprintf(name, "%s_flags", sregname[i]);
state_save_register_UINT16("i386", cpu, name, &cpustate->sreg[i].flags, 1);
sprintf(name, "%s_base", sregname[i]);
state_save_register_UINT32("i386", cpu, name, &cpustate->sreg[i].base, 1);
sprintf(name, "%s_limit", sregname[i]);
state_save_register_UINT32("i386", cpu, name, &cpustate->sreg[i].limit, 1);
sprintf(name, "%s_d", sregname[i]);
state_save_register_int("i386", cpu, name, &cpustate->sreg[i].d);
}
state_save_register_UINT32("i386", cpu, "eip", &cpustate->eip, 1);
state_save_register_UINT32("i386", cpu, "pc", &cpustate->pc, 1);
state_save_register_UINT32("i386", cpu, "prev_eip", &cpustate->prev_eip, 1);
state_save_register_UINT32("i386", cpu, "eflags", &cpustate->eflags, 1);
state_save_register_UINT32("i386", cpu, "eflags_mask", &cpustate->eflags_mask, 1);
state_save_register_UINT8("i386", cpu, "CF", &cpustate->CF, 1);
state_save_register_UINT8("i386", cpu, "DF", &cpustate->DF, 1);
state_save_register_UINT8("i386", cpu, "SF", &cpustate->SF, 1);
state_save_register_UINT8("i386", cpu, "OF", &cpustate->OF, 1);
state_save_register_UINT8("i386", cpu, "ZF", &cpustate->ZF, 1);
state_save_register_UINT8("i386", cpu, "PF", &cpustate->PF, 1);
state_save_register_UINT8("i386", cpu, "AF", &cpustate->AF, 1);
state_save_register_UINT8("i386", cpu, "IF", &cpustate->IF, 1);
state_save_register_UINT8("i386", cpu, "TF", &cpustate->TF, 1);
state_save_register_UINT8("i386", cpu, "IOP1", &cpustate->IOP1, 1);
state_save_register_UINT8("i386", cpu, "IOP2", &cpustate->IOP2, 1);
state_save_register_UINT8("i386", cpu, "NT", &cpustate->NT, 1);
state_save_register_UINT32("i386", cpu, "cr", cpustate->cr, 5);
state_save_register_UINT32("i386", cpu, "dr", cpustate->dr, 8);
state_save_register_UINT32("i386", cpu, "tr", cpustate->tr, 8);
state_save_register_UINT32("i386", cpu, "idtr_base", &cpustate->idtr.base, 1);
state_save_register_UINT16("i386", cpu, "idtr_limit", &cpustate->idtr.limit, 1);
state_save_register_UINT32("i386", cpu, "gdtr_base", &cpustate->gdtr.base, 1);
state_save_register_UINT16("i386", cpu, "gdtr_limit", &cpustate->gdtr.limit, 1);
state_save_register_UINT32("i386", cpu, "task_base", &cpustate->task.base, 1);
state_save_register_UINT16("i386", cpu, "task_segment", &cpustate->task.segment, 1);
state_save_register_UINT32("i386", cpu, "task_limit", &cpustate->task.limit, 1);
state_save_register_UINT16("i386", cpu, "task_flags", &cpustate->task.flags, 1);
state_save_register_UINT32("i386", cpu, "ldtr_base", &cpustate->ldtr.base, 1);
state_save_register_UINT16("i386", cpu, "ldtr_segment", &cpustate->ldtr.segment, 1);
state_save_register_UINT32("i386", cpu, "ldtr_limit", &cpustate->ldtr.limit, 1);
state_save_register_UINT16("i386", cpu, "ldtr_flags", &cpustate->ldtr.flags, 1);
state_save_register_int("i386", cpu, "halted", &cpustate->halted);
state_save_register_UINT8("i386", cpu, "irq_state", &cpustate->irq_state, 1);
state_save_register_UINT8("i386", cpu, "performed_intersegment_jump", &cpustate->performed_intersegment_jump, 1);
state_save_register_UINT32("i386", cpu, "a20_mask", &cpustate->a20_mask, 1);
state_save_register_func_postload(i386_postload);
}
void i386_reset(void *param)
{
i386_state *cpustate = &I;
int (*save_irqcallback)(int);
save_irqcallback = cpustate->irq_callback;
memset( cpustate, 0, sizeof(*cpustate) );
cpustate->irq_callback = save_irqcallback;
cpustate->sreg[CS].selector = 0xf000;
cpustate->sreg[CS].base = 0xffff0000;
cpustate->sreg[CS].limit = 0xffff;
cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
cpustate->idtr.base = 0;
cpustate->idtr.limit = 0x3ff;
cpustate->a20_mask = ~0;
cpustate->cr[0] = 0x7ffffff0; /* reserved bits set to 1 */
cpustate->eflags = 0;
cpustate->eflags_mask = 0x00030000;
cpustate->eip = 0xfff0;
/* Family 3 (386), Model 0 (DX), Stepping 8 (D1) */
REG32(EAX) = 0;
REG32(EDX) = (3 << 8) | (0 << 4) | (8);
build_opcode_table(cpustate, OP_I386);
cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_I386];
cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_I386];
CHANGE_PC(cpustate,cpustate->eip);
}
void i386_exit(void)
{
}
int i386_execute(int cycles)
{
i386_state *cpustate = &I;
i386_ICount = cycles;
cpustate->base_cycles = cycles;
CHANGE_PC(cpustate,cpustate->eip);
if (cpustate->halted)
{
cpustate->tsc += cycles;
i386_ICount = 0;
return cycles;
}
while( i386_ICount > 0 )
{
cpustate->operand_size = cpustate->sreg[CS].d;
cpustate->address_size = cpustate->sreg[CS].d;
cpustate->segment_prefix = 0;
cpustate->prev_eip = cpustate->eip;
CALL_MAME_DEBUG;
i386_check_irq_line(cpustate);
I386OP(decode_opcode)(cpustate);
}
cpustate->tsc += (cycles - i386_ICount);
return cycles - i386_ICount;
}
unsigned i386_get_context(void *dst)
{
if (dst)
*(i386_state *)dst = I;
return sizeof(i386_state);
}
void i386_set_context(void *src)
{
if (src)
I = *(i386_state *)src;
}
unsigned i386_get_reg(int regnum)
{
i386_state *cpustate = &I;
switch (regnum)
{
case REG_PC: return cpustate->pc;
case REG_PREVIOUSPC: return cpustate->sreg[CS].base + cpustate->prev_eip;
case REG_SP: return cpustate->sreg[SS].base + REG32(ESP);
case I386_EIP: return cpustate->eip;
case I386_EAX: return REG32(EAX);
case I386_EBX: return REG32(EBX);
case I386_ECX: return REG32(ECX);
case I386_EDX: return REG32(EDX);
case I386_ESI: return REG32(ESI);
case I386_EDI: return REG32(EDI);
case I386_EBP: return REG32(EBP);
case I386_ESP: return REG32(ESP);
case I386_EFLAGS: return get_flags(cpustate);
case I386_CS: return cpustate->sreg[CS].selector;
case I386_SS: return cpustate->sreg[SS].selector;
case I386_DS: return cpustate->sreg[DS].selector;
case I386_ES: return cpustate->sreg[ES].selector;
case I386_FS: return cpustate->sreg[FS].selector;
case I386_GS: return cpustate->sreg[GS].selector;
case I386_CR0: return cpustate->cr[0];
}
return 0;
}
void i386_set_reg(int regnum, unsigned val)
{
i386_state *cpustate = &I;
switch (regnum)
{
case REG_PC:
cpustate->eip = val - cpustate->sreg[CS].base;
CHANGE_PC(cpustate,cpustate->eip);
break;
case REG_SP: REG32(ESP) = val - cpustate->sreg[SS].base; break;
case I386_EIP: cpustate->eip = val; CHANGE_PC(cpustate,cpustate->eip); break;
case I386_EAX: REG32(EAX) = val; break;
case I386_EBX: REG32(EBX) = val; break;
case I386_ECX: REG32(ECX) = val; break;
case I386_EDX: REG32(EDX) = val; break;
case I386_ESI: REG32(ESI) = val; break;
case I386_EDI: REG32(EDI) = val; break;
case I386_EBP: REG32(EBP) = val; break;
case I386_ESP: REG32(ESP) = val; break;
case I386_EFLAGS: set_flags(cpustate, val); break;
}
}
void i386_set_irq_line(int irqline, int state)
{
i386_state *cpustate = &I;
if (state != CLEAR_LINE && cpustate->halted)
{
cpustate->halted = 0;
}
if ( irqline == IRQ_LINE_NMI )
{
/* NMI (I do not think that this is 100% right) */
if ( state )
i386_trap(cpustate,2, 1);
}
else if ( irqline == I386_INPUT_LINE_A20 )
{
cpustate->a20_mask = state ? ~0 : ~(1 << 20);
}
else
{
cpustate->irq_state = state;
}
}
void i386_set_irq_callback(int (*callback)(int irqline))
{
I.irq_callback = callback;
}
const char *i386_info(void *context, int regnum)
{
static char buffer[16][47+1];
static int which = 0;
i386_state *r = context ? (i386_state *)context : &I;
which = (which + 1) % 16;
buffer[which][0] = '\0';
switch( regnum )
{
case CPU_INFO_REG+I386_EIP: sprintf(buffer[which], "EIP:%08X", r->eip); break;
case CPU_INFO_REG+I386_EAX: sprintf(buffer[which], "EAX:%08X", r->reg.d[EAX]); break;
case CPU_INFO_REG+I386_EBX: sprintf(buffer[which], "EBX:%08X", r->reg.d[EBX]); break;
case CPU_INFO_REG+I386_ECX: sprintf(buffer[which], "ECX:%08X", r->reg.d[ECX]); break;
case CPU_INFO_REG+I386_EDX: sprintf(buffer[which], "EDX:%08X", r->reg.d[EDX]); break;
case CPU_INFO_REG+I386_ESI: sprintf(buffer[which], "ESI:%08X", r->reg.d[ESI]); break;
case CPU_INFO_REG+I386_EDI: sprintf(buffer[which], "EDI:%08X", r->reg.d[EDI]); break;
case CPU_INFO_REG+I386_EBP: sprintf(buffer[which], "EBP:%08X", r->reg.d[EBP]); break;
case CPU_INFO_REG+I386_ESP: sprintf(buffer[which], "ESP:%08X", r->reg.d[ESP]); break;
case CPU_INFO_FLAGS: sprintf(buffer[which], "%08X", r->eflags); break;
case CPU_INFO_NAME: return "I386";
case CPU_INFO_FAMILY: return "Intel 386";
case CPU_INFO_VERSION: return "1.0";
case CPU_INFO_FILE: return __FILE__;
case CPU_INFO_CREDITS: return "Copyright Ville Linde";
}
return buffer[which];
}
unsigned i386_dasm(char *buffer, unsigned pc)
{
sprintf(buffer, "$%02X", cpu_readmem32ledw(pc));
return 1;
}
src/cpu/i386/i386.h
+39
View File
@@ -0,0 +1,39 @@
/***************************************************************************
Intel 386 emulator (Ville Linde), from MAME 0.139
***************************************************************************/
#ifndef I386INTF_H
#define I386INTF_H
#include "cpuintrf.h"
/* the A20 gate, as an input line */
#define I386_INPUT_LINE_A20 1
extern int i386_ICount;
/* the fast memory: a range of plain RAM or ROM at base, which the CPU */
/* fetches, reads or writes directly (flags), without the memory handlers; */
/* set from DRIVER_INIT, emptied at the CPU init. Little endian hosts only */
#define I386_FASTMEM_MAX 8
#define I386_FASTMEM_FETCH 1
#define I386_FASTMEM_READ 2
#define I386_FASTMEM_WRITE 4
void i386_set_fastmem(UINT32 start, UINT32 end, UINT8 *base, int flags);
void i386_init(void);
void i386_reset(void *param);
void i386_exit(void);
int i386_execute(int cycles);
unsigned i386_get_context(void *dst);
void i386_set_context(void *src);
unsigned i386_get_reg(int regnum);
void i386_set_reg(int regnum, unsigned val);
void i386_set_irq_line(int irqline, int state);
void i386_set_irq_callback(int (*callback)(int irqline));
const char *i386_info(void *context, int regnum);
unsigned i386_dasm(char *buffer, unsigned pc);
#endif
src/cpu/i386/i386op16.c
+3257
View File
File diff suppressed because it is too large. Load diff
src/cpu/i386/i386op32.c
+3066
View File
File diff suppressed because it is too large. Load diff
src/cpu/i386/i386ops.c
+2367
View File
File diff suppressed because it is too large. Load diff
src/cpu/i386/i386ops.h
+377
View File
@@ -0,0 +1,377 @@
typedef struct {
UINT8 opcode;
UINT32 flags;
void (*handler16)(i386_state *cpustate);
void (*handler32)(i386_state *cpustate);
} X86_OPCODE;
#define OP_I386 0x1
#define OP_FPU 0x2
#define OP_I486 0x4
#define OP_PENTIUM 0x8
#define OP_MMX 0x10
#define OP_PPRO 0x20
#define OP_SSE 0x40
#define OP_SSE2 0x80
#define OP_SSE3 0x100
#define OP_CYRIX 0x8000
#define OP_2BYTE 0x80000000
static const X86_OPCODE x86_opcode_table[] =
{
/* Opcode Flags 16-bit handler 32-bit handler */
{ 0x00, OP_I386, I386OP(add_rm8_r8), I386OP(add_rm8_r8), },
{ 0x01, OP_I386, I386OP(add_rm16_r16), I386OP(add_rm32_r32), },
{ 0x02, OP_I386, I386OP(add_r8_rm8), I386OP(add_r8_rm8), },
{ 0x03, OP_I386, I386OP(add_r16_rm16), I386OP(add_r32_rm32), },
{ 0x04, OP_I386, I386OP(add_al_i8), I386OP(add_al_i8), },
{ 0x05, OP_I386, I386OP(add_ax_i16), I386OP(add_eax_i32), },
{ 0x06, OP_I386, I386OP(push_es16), I386OP(push_es32), },
{ 0x07, OP_I386, I386OP(pop_es16), I386OP(pop_es32), },
{ 0x08, OP_I386, I386OP(or_rm8_r8), I386OP(or_rm8_r8), },
{ 0x09, OP_I386, I386OP(or_rm16_r16), I386OP(or_rm32_r32), },
{ 0x0A, OP_I386, I386OP(or_r8_rm8), I386OP(or_r8_rm8), },
{ 0x0B, OP_I386, I386OP(or_r16_rm16), I386OP(or_r32_rm32), },
{ 0x0C, OP_I386, I386OP(or_al_i8), I386OP(or_al_i8), },
{ 0x0D, OP_I386, I386OP(or_ax_i16), I386OP(or_eax_i32), },
{ 0x0E, OP_I386, I386OP(push_cs16), I386OP(push_cs32), },
{ 0x0F, OP_I386, I386OP(decode_two_byte), I386OP(decode_two_byte), },
{ 0x10, OP_I386, I386OP(adc_rm8_r8), I386OP(adc_rm8_r8), },
{ 0x11, OP_I386, I386OP(adc_rm16_r16), I386OP(adc_rm32_r32), },
{ 0x12, OP_I386, I386OP(adc_r8_rm8), I386OP(adc_r8_rm8), },
{ 0x13, OP_I386, I386OP(adc_r16_rm16), I386OP(adc_r32_rm32), },
{ 0x14, OP_I386, I386OP(adc_al_i8), I386OP(adc_al_i8), },
{ 0x15, OP_I386, I386OP(adc_ax_i16), I386OP(adc_eax_i32), },
{ 0x16, OP_I386, I386OP(push_ss16), I386OP(push_ss32), },
{ 0x17, OP_I386, I386OP(pop_ss16), I386OP(pop_ss32), },
{ 0x18, OP_I386, I386OP(sbb_rm8_r8), I386OP(sbb_rm8_r8), },
{ 0x19, OP_I386, I386OP(sbb_rm16_r16), I386OP(sbb_rm32_r32), },
{ 0x1A, OP_I386, I386OP(sbb_r8_rm8), I386OP(sbb_r8_rm8), },
{ 0x1B, OP_I386, I386OP(sbb_r16_rm16), I386OP(sbb_r32_rm32), },
{ 0x1C, OP_I386, I386OP(sbb_al_i8), I386OP(sbb_al_i8), },
{ 0x1D, OP_I386, I386OP(sbb_ax_i16), I386OP(sbb_eax_i32), },
{ 0x1E, OP_I386, I386OP(push_ds16), I386OP(push_ds32), },
{ 0x1F, OP_I386, I386OP(pop_ds16), I386OP(pop_ds32), },
{ 0x20, OP_I386, I386OP(and_rm8_r8), I386OP(and_rm8_r8), },
{ 0x21, OP_I386, I386OP(and_rm16_r16), I386OP(and_rm32_r32), },
{ 0x22, OP_I386, I386OP(and_r8_rm8), I386OP(and_r8_rm8), },
{ 0x23, OP_I386, I386OP(and_r16_rm16), I386OP(and_r32_rm32), },
{ 0x24, OP_I386, I386OP(and_al_i8), I386OP(and_al_i8), },
{ 0x25, OP_I386, I386OP(and_ax_i16), I386OP(and_eax_i32), },
{ 0x26, OP_I386, I386OP(segment_ES), I386OP(segment_ES), },
{ 0x27, OP_I386, I386OP(daa), I386OP(daa), },
{ 0x28, OP_I386, I386OP(sub_rm8_r8), I386OP(sub_rm8_r8), },
{ 0x29, OP_I386, I386OP(sub_rm16_r16), I386OP(sub_rm32_r32), },
{ 0x2A, OP_I386, I386OP(sub_r8_rm8), I386OP(sub_r8_rm8), },
{ 0x2B, OP_I386, I386OP(sub_r16_rm16), I386OP(sub_r32_rm32), },
{ 0x2C, OP_I386, I386OP(sub_al_i8), I386OP(sub_al_i8), },
{ 0x2D, OP_I386, I386OP(sub_ax_i16), I386OP(sub_eax_i32), },
{ 0x2E, OP_I386, I386OP(segment_CS), I386OP(segment_CS), },
{ 0x2F, OP_I386, I386OP(das), I386OP(das), },
{ 0x30, OP_I386, I386OP(xor_rm8_r8), I386OP(xor_rm8_r8), },
{ 0x31, OP_I386, I386OP(xor_rm16_r16), I386OP(xor_rm32_r32), },
{ 0x32, OP_I386, I386OP(xor_r8_rm8), I386OP(xor_r8_rm8), },
{ 0x33, OP_I386, I386OP(xor_r16_rm16), I386OP(xor_r32_rm32), },
{ 0x34, OP_I386, I386OP(xor_al_i8), I386OP(xor_al_i8), },
{ 0x35, OP_I386, I386OP(xor_ax_i16), I386OP(xor_eax_i32), },
{ 0x36, OP_I386, I386OP(segment_SS), I386OP(segment_SS), },
{ 0x37, OP_I386, I386OP(aaa), I386OP(aaa), },
{ 0x38, OP_I386, I386OP(cmp_rm8_r8), I386OP(cmp_rm8_r8), },
{ 0x39, OP_I386, I386OP(cmp_rm16_r16), I386OP(cmp_rm32_r32), },
{ 0x3A, OP_I386, I386OP(cmp_r8_rm8), I386OP(cmp_r8_rm8), },
{ 0x3B, OP_I386, I386OP(cmp_r16_rm16), I386OP(cmp_r32_rm32), },
{ 0x3C, OP_I386, I386OP(cmp_al_i8), I386OP(cmp_al_i8), },
{ 0x3D, OP_I386, I386OP(cmp_ax_i16), I386OP(cmp_eax_i32), },
{ 0x3E, OP_I386, I386OP(segment_DS), I386OP(segment_DS), },
{ 0x3F, OP_I386, I386OP(aas), I386OP(aas), },
{ 0x40, OP_I386, I386OP(inc_ax), I386OP(inc_eax), },
{ 0x41, OP_I386, I386OP(inc_cx), I386OP(inc_ecx), },
{ 0x42, OP_I386, I386OP(inc_dx), I386OP(inc_edx), },
{ 0x43, OP_I386, I386OP(inc_bx), I386OP(inc_ebx), },
{ 0x44, OP_I386, I386OP(inc_sp), I386OP(inc_esp), },
{ 0x45, OP_I386, I386OP(inc_bp), I386OP(inc_ebp), },
{ 0x46, OP_I386, I386OP(inc_si), I386OP(inc_esi), },
{ 0x47, OP_I386, I386OP(inc_di), I386OP(inc_edi), },
{ 0x48, OP_I386, I386OP(dec_ax), I386OP(dec_eax), },
{ 0x49, OP_I386, I386OP(dec_cx), I386OP(dec_ecx), },
{ 0x4A, OP_I386, I386OP(dec_dx), I386OP(dec_edx), },
{ 0x4B, OP_I386, I386OP(dec_bx), I386OP(dec_ebx), },
{ 0x4C, OP_I386, I386OP(dec_sp), I386OP(dec_esp), },
{ 0x4D, OP_I386, I386OP(dec_bp), I386OP(dec_ebp), },
{ 0x4E, OP_I386, I386OP(dec_si), I386OP(dec_esi), },
{ 0x4F, OP_I386, I386OP(dec_di), I386OP(dec_edi), },
{ 0x50, OP_I386, I386OP(push_ax), I386OP(push_eax), },
{ 0x51, OP_I386, I386OP(push_cx), I386OP(push_ecx), },
{ 0x52, OP_I386, I386OP(push_dx), I386OP(push_edx), },
{ 0x53, OP_I386, I386OP(push_bx), I386OP(push_ebx), },
{ 0x54, OP_I386, I386OP(push_sp), I386OP(push_esp), },
{ 0x55, OP_I386, I386OP(push_bp), I386OP(push_ebp), },
{ 0x56, OP_I386, I386OP(push_si), I386OP(push_esi), },
{ 0x57, OP_I386, I386OP(push_di), I386OP(push_edi), },
{ 0x58, OP_I386, I386OP(pop_ax), I386OP(pop_eax), },
{ 0x59, OP_I386, I386OP(pop_cx), I386OP(pop_ecx), },
{ 0x5A, OP_I386, I386OP(pop_dx), I386OP(pop_edx), },
{ 0x5B, OP_I386, I386OP(pop_bx), I386OP(pop_ebx), },
{ 0x5C, OP_I386, I386OP(pop_sp), I386OP(pop_esp), },
{ 0x5D, OP_I386, I386OP(pop_bp), I386OP(pop_ebp), },
{ 0x5E, OP_I386, I386OP(pop_si), I386OP(pop_esi), },
{ 0x5F, OP_I386, I386OP(pop_di), I386OP(pop_edi), },
{ 0x60, OP_I386, I386OP(pusha), I386OP(pushad), },
{ 0x61, OP_I386, I386OP(popa), I386OP(popad), },
{ 0x62, OP_I386, I386OP(bound_r16_m16_m16), I386OP(bound_r32_m32_m32), },
{ 0x63, OP_I386, I386OP(arpl), I386OP(arpl), },
{ 0x64, OP_I386, I386OP(segment_FS), I386OP(segment_FS), },
{ 0x65, OP_I386, I386OP(segment_GS), I386OP(segment_GS), },
{ 0x66, OP_I386, I386OP(operand_size), I386OP(operand_size), },
{ 0x67, OP_I386, I386OP(address_size), I386OP(address_size), },
{ 0x68, OP_I386, I386OP(push_i16), I386OP(push_i32), },
{ 0x69, OP_I386, I386OP(imul_r16_rm16_i16), I386OP(imul_r32_rm32_i32), },
{ 0x6A, OP_I386, I386OP(push_i8), I386OP(push_i8), },
{ 0x6B, OP_I386, I386OP(imul_r16_rm16_i8), I386OP(imul_r32_rm32_i8), },
{ 0x6C, OP_I386, I386OP(insb), I386OP(insb), },
{ 0x6D, OP_I386, I386OP(insw), I386OP(insd), },
{ 0x6E, OP_I386, I386OP(outsb), I386OP(outsb), },
{ 0x6F, OP_I386, I386OP(outsw), I386OP(outsd), },
{ 0x70, OP_I386, I386OP(jo_rel8), I386OP(jo_rel8), },
{ 0x71, OP_I386, I386OP(jno_rel8), I386OP(jno_rel8), },
{ 0x72, OP_I386, I386OP(jc_rel8), I386OP(jc_rel8), },
{ 0x73, OP_I386, I386OP(jnc_rel8), I386OP(jnc_rel8), },
{ 0x74, OP_I386, I386OP(jz_rel8), I386OP(jz_rel8), },
{ 0x75, OP_I386, I386OP(jnz_rel8), I386OP(jnz_rel8), },
{ 0x76, OP_I386, I386OP(jbe_rel8), I386OP(jbe_rel8), },
{ 0x77, OP_I386, I386OP(ja_rel8), I386OP(ja_rel8), },
{ 0x78, OP_I386, I386OP(js_rel8), I386OP(js_rel8), },
{ 0x79, OP_I386, I386OP(jns_rel8), I386OP(jns_rel8), },
{ 0x7A, OP_I386, I386OP(jp_rel8), I386OP(jp_rel8), },
{ 0x7B, OP_I386, I386OP(jnp_rel8), I386OP(jnp_rel8), },
{ 0x7C, OP_I386, I386OP(jl_rel8), I386OP(jl_rel8), },
{ 0x7D, OP_I386, I386OP(jge_rel8), I386OP(jge_rel8), },
{ 0x7E, OP_I386, I386OP(jle_rel8), I386OP(jle_rel8), },
{ 0x7F, OP_I386, I386OP(jg_rel8), I386OP(jg_rel8), },
{ 0x80, OP_I386, I386OP(group80_8), I386OP(group80_8), },
{ 0x81, OP_I386, I386OP(group81_16), I386OP(group81_32), },
{ 0x82, OP_I386, I386OP(group80_8), I386OP(group80_8), },
{ 0x83, OP_I386, I386OP(group83_16), I386OP(group83_32), },
{ 0x84, OP_I386, I386OP(test_rm8_r8), I386OP(test_rm8_r8), },
{ 0x85, OP_I386, I386OP(test_rm16_r16), I386OP(test_rm32_r32), },
{ 0x86, OP_I386, I386OP(xchg_r8_rm8), I386OP(xchg_r8_rm8), },
{ 0x87, OP_I386, I386OP(xchg_r16_rm16), I386OP(xchg_r32_rm32), },
{ 0x88, OP_I386, I386OP(mov_rm8_r8), I386OP(mov_rm8_r8), },
{ 0x89, OP_I386, I386OP(mov_rm16_r16), I386OP(mov_rm32_r32), },
{ 0x8A, OP_I386, I386OP(mov_r8_rm8), I386OP(mov_r8_rm8), },
{ 0x8B, OP_I386, I386OP(mov_r16_rm16), I386OP(mov_r32_rm32), },
{ 0x8C, OP_I386, I386OP(mov_rm16_sreg), I386OP(mov_rm16_sreg), },
{ 0x8D, OP_I386, I386OP(lea16), I386OP(lea32), },
{ 0x8E, OP_I386, I386OP(mov_sreg_rm16), I386OP(mov_sreg_rm16), },
{ 0x8F, OP_I386, I386OP(pop_rm16), I386OP(pop_rm32), },
{ 0x90, OP_I386, I386OP(nop), I386OP(nop), },
{ 0x91, OP_I386, I386OP(xchg_ax_cx), I386OP(xchg_eax_ecx), },
{ 0x92, OP_I386, I386OP(xchg_ax_dx), I386OP(xchg_eax_edx), },
{ 0x93, OP_I386, I386OP(xchg_ax_bx), I386OP(xchg_eax_ebx), },
{ 0x94, OP_I386, I386OP(xchg_ax_sp), I386OP(xchg_eax_esp), },
{ 0x95, OP_I386, I386OP(xchg_ax_bp), I386OP(xchg_eax_ebp), },
{ 0x96, OP_I386, I386OP(xchg_ax_si), I386OP(xchg_eax_esi), },
{ 0x97, OP_I386, I386OP(xchg_ax_di), I386OP(xchg_eax_edi), },
{ 0x98, OP_I386, I386OP(cbw), I386OP(cwde), },
{ 0x99, OP_I386, I386OP(cwd), I386OP(cdq), },
{ 0x9A, OP_I386, I386OP(call_abs16), I386OP(call_abs32), },
{ 0x9B, OP_I386, I386OP(wait), I386OP(wait), },
{ 0x9C, OP_I386, I386OP(pushf), I386OP(pushfd), },
{ 0x9D, OP_I386, I386OP(popf), I386OP(popfd), },
{ 0x9E, OP_I386, I386OP(sahf), I386OP(sahf), },
{ 0x9F, OP_I386, I386OP(lahf), I386OP(lahf), },
{ 0xA0, OP_I386, I386OP(mov_al_m8), I386OP(mov_al_m8), },
{ 0xA1, OP_I386, I386OP(mov_ax_m16), I386OP(mov_eax_m32), },
{ 0xA2, OP_I386, I386OP(mov_m8_al), I386OP(mov_m8_al), },
{ 0xA3, OP_I386, I386OP(mov_m16_ax), I386OP(mov_m32_eax), },
{ 0xA4, OP_I386, I386OP(movsb), I386OP(movsb), },
{ 0xA5, OP_I386, I386OP(movsw), I386OP(movsd), },
{ 0xA6, OP_I386, I386OP(cmpsb), I386OP(cmpsb), },
{ 0xA7, OP_I386, I386OP(cmpsw), I386OP(cmpsd), },
{ 0xA8, OP_I386, I386OP(test_al_i8), I386OP(test_al_i8), },
{ 0xA9, OP_I386, I386OP(test_ax_i16), I386OP(test_eax_i32), },
{ 0xAA, OP_I386, I386OP(stosb), I386OP(stosb), },
{ 0xAB, OP_I386, I386OP(stosw), I386OP(stosd), },
{ 0xAC, OP_I386, I386OP(lodsb), I386OP(lodsb), },
{ 0xAD, OP_I386, I386OP(lodsw), I386OP(lodsd), },
{ 0xAE, OP_I386, I386OP(scasb), I386OP(scasb), },
{ 0xAF, OP_I386, I386OP(scasw), I386OP(scasd), },
{ 0xB0, OP_I386, I386OP(mov_al_i8), I386OP(mov_al_i8), },
{ 0xB1, OP_I386, I386OP(mov_cl_i8), I386OP(mov_cl_i8), },
{ 0xB2, OP_I386, I386OP(mov_dl_i8), I386OP(mov_dl_i8), },
{ 0xB3, OP_I386, I386OP(mov_bl_i8), I386OP(mov_bl_i8), },
{ 0xB4, OP_I386, I386OP(mov_ah_i8), I386OP(mov_ah_i8), },
{ 0xB5, OP_I386, I386OP(mov_ch_i8), I386OP(mov_ch_i8), },
{ 0xB6, OP_I386, I386OP(mov_dh_i8), I386OP(mov_dh_i8), },
{ 0xB7, OP_I386, I386OP(mov_bh_i8), I386OP(mov_bh_i8), },
{ 0xB8, OP_I386, I386OP(mov_ax_i16), I386OP(mov_eax_i32), },
{ 0xB9, OP_I386, I386OP(mov_cx_i16), I386OP(mov_ecx_i32), },
{ 0xBA, OP_I386, I386OP(mov_dx_i16), I386OP(mov_edx_i32), },
{ 0xBB, OP_I386, I386OP(mov_bx_i16), I386OP(mov_ebx_i32), },
{ 0xBC, OP_I386, I386OP(mov_sp_i16), I386OP(mov_esp_i32), },
{ 0xBD, OP_I386, I386OP(mov_bp_i16), I386OP(mov_ebp_i32), },
{ 0xBE, OP_I386, I386OP(mov_si_i16), I386OP(mov_esi_i32), },
{ 0xBF, OP_I386, I386OP(mov_di_i16), I386OP(mov_edi_i32), },
{ 0xC0, OP_I386, I386OP(groupC0_8), I386OP(groupC0_8), },
{ 0xC1, OP_I386, I386OP(groupC1_16), I386OP(groupC1_32), },
{ 0xC2, OP_I386, I386OP(ret_near16_i16), I386OP(ret_near32_i16), },
{ 0xC3, OP_I386, I386OP(ret_near16), I386OP(ret_near32), },
{ 0xC4, OP_I386, I386OP(les16), I386OP(les32), },
{ 0xC5, OP_I386, I386OP(lds16), I386OP(lds32), },
{ 0xC6, OP_I386, I386OP(mov_rm8_i8), I386OP(mov_rm8_i8), },
{ 0xC7, OP_I386, I386OP(mov_rm16_i16), I386OP(mov_rm32_i32), },
{ 0xC8, OP_I386, I386OP(enter16), I386OP(enter32), },
{ 0xC9, OP_I386, I386OP(leave16), I386OP(leave32), },
{ 0xCA, OP_I386, I386OP(retf_i16), I386OP(retf_i32), },
{ 0xCB, OP_I386, I386OP(retf16), I386OP(retf32), },
{ 0xCC, OP_I386, I386OP(int3), I386OP(int3), },
{ 0xCD, OP_I386, I386OP(int), I386OP(int), },
{ 0xCE, OP_I386, I386OP(into), I386OP(into), },
{ 0xCF, OP_I386, I386OP(iret16), I386OP(iret32), },
{ 0xD0, OP_I386, I386OP(groupD0_8), I386OP(groupD0_8), },
{ 0xD1, OP_I386, I386OP(groupD1_16), I386OP(groupD1_32), },
{ 0xD2, OP_I386, I386OP(groupD2_8), I386OP(groupD2_8), },
{ 0xD3, OP_I386, I386OP(groupD3_16), I386OP(groupD3_32), },
{ 0xD4, OP_I386, I386OP(aam), I386OP(aam), },
{ 0xD5, OP_I386, I386OP(aad), I386OP(aad), },
{ 0xD6, OP_I386, I386OP(setalc), I386OP(setalc), },
{ 0xD7, OP_I386, I386OP(xlat16), I386OP(xlat32), },
{ 0xD8, OP_I386, I386OP(escape), I386OP(escape), },
{ 0xD9, OP_I386, I386OP(escape), I386OP(escape), },
{ 0xDA, OP_I386, I386OP(escape), I386OP(escape), },
{ 0xDB, OP_I386, I386OP(escape), I386OP(escape), },
{ 0xDC, OP_I386, I386OP(escape), I386OP(escape), },
{ 0xDD, OP_I386, I386OP(escape), I386OP(escape), },
{ 0xDE, OP_I386, I386OP(escape), I386OP(escape), },
{ 0xDF, OP_I386, I386OP(escape), I386OP(escape), },
{ 0xD8, OP_FPU, I386OP(fpu_group_d8), I386OP(fpu_group_d8), },
{ 0xD9, OP_FPU, I386OP(fpu_group_d9), I386OP(fpu_group_d9), },
{ 0xDA, OP_FPU, I386OP(fpu_group_da), I386OP(fpu_group_da), },
{ 0xDB, OP_FPU, I386OP(fpu_group_db), I386OP(fpu_group_db), },
{ 0xDC, OP_FPU, I386OP(fpu_group_dc), I386OP(fpu_group_dc), },
{ 0xDD, OP_FPU, I386OP(fpu_group_dd), I386OP(fpu_group_dd), },
{ 0xDE, OP_FPU, I386OP(fpu_group_de), I386OP(fpu_group_de), },
{ 0xDF, OP_FPU, I386OP(fpu_group_df), I386OP(fpu_group_df), },
{ 0xE0, OP_I386, I386OP(loopne16), I386OP(loopne32), },
{ 0xE1, OP_I386, I386OP(loopz16), I386OP(loopz32), },
{ 0xE2, OP_I386, I386OP(loop16), I386OP(loop32), },
{ 0xE3, OP_I386, I386OP(jcxz16), I386OP(jcxz32), },
{ 0xE4, OP_I386, I386OP(in_al_i8), I386OP(in_al_i8), },
{ 0xE5, OP_I386, I386OP(in_ax_i8), I386OP(in_eax_i8), },
{ 0xE6, OP_I386, I386OP(out_al_i8), I386OP(out_al_i8), },
{ 0xE7, OP_I386, I386OP(out_ax_i8), I386OP(out_eax_i8), },
{ 0xE8, OP_I386, I386OP(call_rel16), I386OP(call_rel32), },
{ 0xE9, OP_I386, I386OP(jmp_rel16), I386OP(jmp_rel32), },
{ 0xEA, OP_I386, I386OP(jmp_abs16), I386OP(jmp_abs32), },
{ 0xEB, OP_I386, I386OP(jmp_rel8), I386OP(jmp_rel8), },
{ 0xEC, OP_I386, I386OP(in_al_dx), I386OP(in_al_dx), },
{ 0xED, OP_I386, I386OP(in_ax_dx), I386OP(in_eax_dx), },
{ 0xEE, OP_I386, I386OP(out_al_dx), I386OP(out_al_dx), },
{ 0xEF, OP_I386, I386OP(out_ax_dx), I386OP(out_eax_dx), },
{ 0xF0, OP_I386, I386OP(lock), I386OP(lock), },
{ 0xF1, OP_I386, I386OP(invalid), I386OP(invalid), },
{ 0xF2, OP_I386, I386OP(repne), I386OP(repne), },
{ 0xF3, OP_I386, I386OP(rep), I386OP(rep), },
{ 0xF4, OP_I386, I386OP(hlt), I386OP(hlt), },
{ 0xF5, OP_I386, I386OP(cmc), I386OP(cmc), },
{ 0xF6, OP_I386, I386OP(groupF6_8), I386OP(groupF6_8), },
{ 0xF7, OP_I386, I386OP(groupF7_16), I386OP(groupF7_32), },
{ 0xF8, OP_I386, I386OP(clc), I386OP(clc), },
{ 0xF9, OP_I386, I386OP(stc), I386OP(stc), },
{ 0xFA, OP_I386, I386OP(cli), I386OP(cli), },
{ 0xFB, OP_I386, I386OP(sti), I386OP(sti), },
{ 0xFC, OP_I386, I386OP(cld), I386OP(cld), },
{ 0xFD, OP_I386, I386OP(std), I386OP(std), },
{ 0xFE, OP_I386, I386OP(groupFE_8), I386OP(groupFE_8), },
{ 0xFF, OP_I386, I386OP(groupFF_16), I386OP(groupFF_32), },
{ 0x00, OP_2BYTE|OP_I386, I386OP(group0F00_16), I386OP(group0F00_32), },
{ 0x01, OP_2BYTE|OP_I386, I386OP(group0F01_16), I386OP(group0F01_32), },
{ 0x01, OP_2BYTE|OP_I486, I486OP(group0F01_16), I486OP(group0F01_32), },
{ 0x02, OP_2BYTE|OP_I386, I386OP(unimplemented), I386OP(unimplemented), },
{ 0x03, OP_2BYTE|OP_I386, I386OP(lsl_r16_rm16), I386OP(lsl_r32_rm32), },
{ 0x06, OP_2BYTE|OP_I386, I386OP(clts), I386OP(clts), },
{ 0x08, OP_2BYTE|OP_I486, I486OP(invd), I486OP(invd), },
{ 0x09, OP_2BYTE|OP_I486, I486OP(wbinvd), I486OP(wbinvd), },
{ 0x0B, OP_2BYTE|OP_I386, I386OP(unimplemented), I386OP(unimplemented), },
{ 0x20, OP_2BYTE|OP_I386, I386OP(mov_r32_cr), I386OP(mov_r32_cr), },
{ 0x21, OP_2BYTE|OP_I386, I386OP(mov_r32_dr), I386OP(mov_r32_dr), },
{ 0x22, OP_2BYTE|OP_I386, I386OP(mov_cr_r32), I386OP(mov_cr_r32), },
{ 0x23, OP_2BYTE|OP_I386, I386OP(mov_dr_r32), I386OP(mov_dr_r32), },
{ 0x24, OP_2BYTE|OP_I386, I386OP(mov_r32_tr), I386OP(mov_r32_tr), },
{ 0x26, OP_2BYTE|OP_I386, I386OP(mov_tr_r32), I386OP(mov_tr_r32), },
{ 0x30, OP_2BYTE|OP_PENTIUM, PENTIUMOP(wrmsr), PENTIUMOP(wrmsr), },
{ 0x31, OP_2BYTE|OP_PENTIUM, PENTIUMOP(rdtsc), PENTIUMOP(rdtsc), },
{ 0x32, OP_2BYTE|OP_PENTIUM, PENTIUMOP(rdmsr), PENTIUMOP(rdmsr), },
{ 0x74, OP_2BYTE|OP_CYRIX, I386OP(cyrix_unknown), I386OP(cyrix_unknown), },
{ 0x80, OP_2BYTE|OP_I386, I386OP(jo_rel16), I386OP(jo_rel32), },
{ 0x81, OP_2BYTE|OP_I386, I386OP(jno_rel16), I386OP(jno_rel32), },
{ 0x82, OP_2BYTE|OP_I386, I386OP(jc_rel16), I386OP(jc_rel32), },
{ 0x83, OP_2BYTE|OP_I386, I386OP(jnc_rel16), I386OP(jnc_rel32), },
{ 0x84, OP_2BYTE|OP_I386, I386OP(jz_rel16), I386OP(jz_rel32), },
{ 0x85, OP_2BYTE|OP_I386, I386OP(jnz_rel16), I386OP(jnz_rel32), },
{ 0x86, OP_2BYTE|OP_I386, I386OP(jbe_rel16), I386OP(jbe_rel32), },
{ 0x87, OP_2BYTE|OP_I386, I386OP(ja_rel16), I386OP(ja_rel32), },
{ 0x88, OP_2BYTE|OP_I386, I386OP(js_rel16), I386OP(js_rel32), },
{ 0x89, OP_2BYTE|OP_I386, I386OP(jns_rel16), I386OP(jns_rel32), },
{ 0x8A, OP_2BYTE|OP_I386, I386OP(jp_rel16), I386OP(jp_rel32), },
{ 0x8B, OP_2BYTE|OP_I386, I386OP(jnp_rel16), I386OP(jnp_rel32), },
{ 0x8C, OP_2BYTE|OP_I386, I386OP(jl_rel16), I386OP(jl_rel32), },
{ 0x8D, OP_2BYTE|OP_I386, I386OP(jge_rel16), I386OP(jge_rel32), },
{ 0x8E, OP_2BYTE|OP_I386, I386OP(jle_rel16), I386OP(jle_rel32), },
{ 0x8F, OP_2BYTE|OP_I386, I386OP(jg_rel16), I386OP(jg_rel32), },
{ 0x90, OP_2BYTE|OP_I386, I386OP(seto_rm8), I386OP(seto_rm8), },
{ 0x91, OP_2BYTE|OP_I386, I386OP(setno_rm8), I386OP(setno_rm8), },
{ 0x92, OP_2BYTE|OP_I386, I386OP(setc_rm8), I386OP(setc_rm8), },
{ 0x93, OP_2BYTE|OP_I386, I386OP(setnc_rm8), I386OP(setnc_rm8), },
{ 0x94, OP_2BYTE|OP_I386, I386OP(setz_rm8), I386OP(setz_rm8), },
{ 0x95, OP_2BYTE|OP_I386, I386OP(setnz_rm8), I386OP(setnz_rm8), },
{ 0x96, OP_2BYTE|OP_I386, I386OP(setbe_rm8), I386OP(setbe_rm8), },
{ 0x97, OP_2BYTE|OP_I386, I386OP(seta_rm8), I386OP(seta_rm8), },
{ 0x98, OP_2BYTE|OP_I386, I386OP(sets_rm8), I386OP(sets_rm8), },
{ 0x99, OP_2BYTE|OP_I386, I386OP(setns_rm8), I386OP(setns_rm8), },
{ 0x9A, OP_2BYTE|OP_I386, I386OP(setp_rm8), I386OP(setp_rm8), },
{ 0x9B, OP_2BYTE|OP_I386, I386OP(setnp_rm8), I386OP(setnp_rm8), },
{ 0x9C, OP_2BYTE|OP_I386, I386OP(setl_rm8), I386OP(setl_rm8), },
{ 0x9D, OP_2BYTE|OP_I386, I386OP(setge_rm8), I386OP(setge_rm8), },
{ 0x9E, OP_2BYTE|OP_I386, I386OP(setle_rm8), I386OP(setle_rm8), },
{ 0x9F, OP_2BYTE|OP_I386, I386OP(setg_rm8), I386OP(setg_rm8), },
{ 0xA0, OP_2BYTE|OP_I386, I386OP(push_fs16), I386OP(push_fs32), },
{ 0xA1, OP_2BYTE|OP_I386, I386OP(pop_fs16), I386OP(pop_fs32), },
{ 0xA2, OP_2BYTE|OP_I486, I486OP(cpuid), I486OP(cpuid), },
{ 0xA3, OP_2BYTE|OP_I386, I386OP(bt_rm16_r16), I386OP(bt_rm32_r32), },
{ 0xA4, OP_2BYTE|OP_I386, I386OP(shld16_i8), I386OP(shld32_i8), },
{ 0xA5, OP_2BYTE|OP_I386, I386OP(shld16_cl), I386OP(shld32_cl), },
{ 0xA8, OP_2BYTE|OP_I386, I386OP(push_gs16), I386OP(push_gs32), },
{ 0xA9, OP_2BYTE|OP_I386, I386OP(pop_gs16), I386OP(pop_gs32), },
{ 0xAA, OP_2BYTE|OP_I386, I386OP(unimplemented), I386OP(unimplemented), },
{ 0xAB, OP_2BYTE|OP_I386, I386OP(bts_rm16_r16), I386OP(bts_rm32_r32), },
{ 0xAC, OP_2BYTE|OP_I386, I386OP(shrd16_i8), I386OP(shrd32_i8), },
{ 0xAD, OP_2BYTE|OP_I386, I386OP(shrd16_cl), I386OP(shrd32_cl), },
{ 0xAE, OP_2BYTE|OP_I386, I386OP(invalid), I386OP(invalid), },
{ 0xAF, OP_2BYTE|OP_I386, I386OP(imul_r16_rm16), I386OP(imul_r32_rm32), },
{ 0xB0, OP_2BYTE|OP_I486, I486OP(cmpxchg_rm8_r8), I486OP(cmpxchg_rm8_r8), },
{ 0xB1, OP_2BYTE|OP_I486, I486OP(cmpxchg_rm16_r16), I486OP(cmpxchg_rm32_r32), },
{ 0xB2, OP_2BYTE|OP_I386, I386OP(lss16), I386OP(lss32), },
{ 0xB3, OP_2BYTE|OP_I386, I386OP(btr_rm16_r16), I386OP(btr_rm32_r32), },
{ 0xB4, OP_2BYTE|OP_I386, I386OP(lfs16), I386OP(lfs32), },
{ 0xB5, OP_2BYTE|OP_I386, I386OP(lgs16), I386OP(lgs32), },
{ 0xB6, OP_2BYTE|OP_I386, I386OP(movzx_r16_rm8), I386OP(movzx_r32_rm8), },
{ 0xB7, OP_2BYTE|OP_I386, I386OP(invalid), I386OP(movzx_r32_rm16), },
{ 0xBA, OP_2BYTE|OP_I386, I386OP(group0FBA_16), I386OP(group0FBA_32), },
{ 0xBB, OP_2BYTE|OP_I386, I386OP(btc_rm16_r16), I386OP(btc_rm32_r32), },
{ 0xBC, OP_2BYTE|OP_I386, I386OP(bsf_r16_rm16), I386OP(bsf_r32_rm32), },
{ 0xBD, OP_2BYTE|OP_I386, I386OP(bsr_r16_rm16), I386OP(bsr_r32_rm32), },
{ 0xBE, OP_2BYTE|OP_I386, I386OP(movsx_r16_rm8), I386OP(movsx_r32_rm8), },
{ 0xBF, OP_2BYTE|OP_I386, I386OP(invalid), I386OP(movsx_r32_rm16), },
{ 0xC0, OP_2BYTE|OP_I486, I486OP(xadd_rm8_r8), I486OP(xadd_rm8_r8), },
{ 0xC1, OP_2BYTE|OP_I486, I486OP(xadd_rm16_r16), I486OP(xadd_rm32_r32), },
{ 0xC7, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmpxchg8b_m64), PENTIUMOP(cmpxchg8b_m64), },
{ 0xC8, OP_2BYTE|OP_I486, I486OP(bswap_eax), I486OP(bswap_eax), },
{ 0xC9, OP_2BYTE|OP_I486, I486OP(bswap_ecx), I486OP(bswap_ecx), },
{ 0xCA, OP_2BYTE|OP_I486, I486OP(bswap_edx), I486OP(bswap_edx), },
{ 0xCB, OP_2BYTE|OP_I486, I486OP(bswap_ebx), I486OP(bswap_ebx), },
{ 0xCC, OP_2BYTE|OP_I486, I486OP(bswap_esp), I486OP(bswap_esp), },
{ 0xCD, OP_2BYTE|OP_I486, I486OP(bswap_ebp), I486OP(bswap_ebp), },
{ 0xCE, OP_2BYTE|OP_I486, I486OP(bswap_esi), I486OP(bswap_esi), },
{ 0xCF, OP_2BYTE|OP_I486, I486OP(bswap_edi), I486OP(bswap_edi), }
};
src/cpu/i386/i386priv.h
+1094
View File
File diff suppressed because it is too large. Load diff
src/cpu/i386/i486ops.c
+424
View File
@@ -0,0 +1,424 @@
/* Intel 486+ specific opcodes */
static void I486OP(cpuid)(i386_state *cpustate) /* Opcode 0x0F A2 */
{
if (cpustate->cpuid_id0 == 0)
{
/* this 486 doesn't support the CPUID instruction */
logerror("CPUID not supported at %08x!\n", cpustate->eip);
i386_trap(cpustate, 6, 0);
}
else
{
switch (REG32(EAX))
{
case 0:
{
REG32(EAX) = cpustate->cpuid_max_input_value_eax;
REG32(EBX) = cpustate->cpuid_id0;
REG32(ECX) = cpustate->cpuid_id2;
REG32(EDX) = cpustate->cpuid_id1;
CYCLES(cpustate,CYCLES_CPUID);
break;
}
case 1:
{
REG32(EAX) = cpustate->cpu_version;
REG32(EDX) = cpustate->feature_flags;
CYCLES(cpustate,CYCLES_CPUID_EAX1);
break;
}
}
}
}
static void I486OP(invd)(i386_state *cpustate) /* Opcode 0x0f 08 */
{
/* Nothing to do ? */
CYCLES(cpustate,CYCLES_INVD);
}
static void I486OP(wbinvd)(i386_state *cpustate) /* Opcode 0x0f 09 */
{
/* Nothing to do ? */
}
static void I486OP(cmpxchg_rm8_r8)(i386_state *cpustate) /* Opcode 0x0f b0 */
{
UINT8 modrm = FETCH(cpustate);
if( modrm >= 0xc0 ) {
UINT8 dst = LOAD_RM8(modrm);
UINT8 src = LOAD_REG8(modrm);
if( REG8(AL) == dst ) {
STORE_RM8(modrm, src);
cpustate->ZF = 1;
CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_T);
} else {
REG8(AL) = dst;
cpustate->ZF = 0;
CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_F);
}
} else {
UINT32 ea = GetEA(cpustate,modrm);
UINT8 dst = READ8(cpustate,ea);
UINT8 src = LOAD_REG8(modrm);
if( REG8(AL) == dst ) {
WRITE8(cpustate,modrm, src);
cpustate->ZF = 1;
CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_T);
} else {
REG8(AL) = dst;
cpustate->ZF = 0;
CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_F);
}
}
}
static void I486OP(cmpxchg_rm16_r16)(i386_state *cpustate) /* Opcode 0x0f b1 */
{
UINT8 modrm = FETCH(cpustate);
if( modrm >= 0xc0 ) {
UINT16 dst = LOAD_RM16(modrm);
UINT16 src = LOAD_REG16(modrm);
if( REG16(AX) == dst ) {
STORE_RM16(modrm, src);
cpustate->ZF = 1;
CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_T);
} else {
REG16(AX) = dst;
cpustate->ZF = 0;
CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_F);
}
} else {
UINT32 ea = GetEA(cpustate,modrm);
UINT16 dst = READ16(cpustate,ea);
UINT16 src = LOAD_REG16(modrm);
if( REG16(AX) == dst ) {
WRITE16(cpustate,modrm, src);
cpustate->ZF = 1;
CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_T);
} else {
REG16(AX) = dst;
cpustate->ZF = 0;
CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_F);
}
}
}
static void I486OP(cmpxchg_rm32_r32)(i386_state *cpustate) /* Opcode 0x0f b1 */
{
UINT8 modrm = FETCH(cpustate);
if( modrm >= 0xc0 ) {
UINT32 dst = LOAD_RM32(modrm);
UINT32 src = LOAD_REG32(modrm);
if( REG32(EAX) == dst ) {
STORE_RM32(modrm, src);
cpustate->ZF = 1;
CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_T);
} else {
REG32(EAX) = dst;
cpustate->ZF = 0;
CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_F);
}
} else {
UINT32 ea = GetEA(cpustate,modrm);
UINT32 dst = READ32(cpustate,ea);
UINT32 src = LOAD_REG32(modrm);
if( REG32(EAX) == dst ) {
WRITE32(cpustate,ea, src);
cpustate->ZF = 1;
CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_T);
} else {
REG32(EAX) = dst;
cpustate->ZF = 0;
CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_F);
}
}
}
static void I486OP(xadd_rm8_r8)(i386_state *cpustate) /* Opcode 0x0f c0 */
{
UINT8 modrm = FETCH(cpustate);
if( modrm >= 0xc0 ) {
UINT8 dst = LOAD_RM8(modrm);
UINT8 src = LOAD_REG8(modrm);
STORE_RM16(modrm, dst + src);
STORE_REG16(modrm, dst);
CYCLES(cpustate,CYCLES_XADD_REG_REG);
} else {
UINT32 ea = GetEA(cpustate,modrm);
UINT8 dst = READ8(cpustate,ea);
UINT8 src = LOAD_REG8(modrm);
WRITE8(cpustate,ea, dst + src);
STORE_REG8(modrm, dst);
CYCLES(cpustate,CYCLES_XADD_REG_MEM);
}
}
static void I486OP(xadd_rm16_r16)(i386_state *cpustate) /* Opcode 0x0f c1 */
{
UINT8 modrm = FETCH(cpustate);
if( modrm >= 0xc0 ) {
UINT16 dst = LOAD_RM16(modrm);
UINT16 src = LOAD_REG16(modrm);
STORE_RM16(modrm, dst + src);
STORE_REG16(modrm, dst);
CYCLES(cpustate,CYCLES_XADD_REG_REG);
} else {
UINT32 ea = GetEA(cpustate,modrm);
UINT16 dst = READ16(cpustate,ea);
UINT16 src = LOAD_REG16(modrm);
WRITE16(cpustate,ea, dst + src);
STORE_REG16(modrm, dst);
CYCLES(cpustate,CYCLES_XADD_REG_MEM);
}
}
static void I486OP(xadd_rm32_r32)(i386_state *cpustate) /* Opcode 0x0f c1 */
{
UINT8 modrm = FETCH(cpustate);
if( modrm >= 0xc0 ) {
UINT32 dst = LOAD_RM32(modrm);
UINT32 src = LOAD_REG32(modrm);
STORE_RM32(modrm, dst + src);
STORE_REG32(modrm, dst);
CYCLES(cpustate,CYCLES_XADD_REG_REG);
} else {
UINT32 ea = GetEA(cpustate,modrm);
UINT32 dst = READ32(cpustate,ea);
UINT32 src = LOAD_REG32(modrm);
WRITE32(cpustate,ea, dst + src);
STORE_REG32(modrm, dst);
CYCLES(cpustate,CYCLES_XADD_REG_MEM);
}
}
static void I486OP(group0F01_16)(i386_state *cpustate) /* Opcode 0x0f 01 */
{
UINT8 modrm = FETCH(cpustate);
UINT16 address;
UINT32 ea;
switch( (modrm >> 3) & 0x7 )
{
case 0: /* SGDT */
{
if( modrm >= 0xc0 ) {
address = LOAD_RM16(modrm);
ea = i386_translate( cpustate, CS, address );
} else {
ea = GetEA(cpustate,modrm);
}
WRITE16(cpustate,ea, cpustate->gdtr.limit);
WRITE32(cpustate,ea + 2, cpustate->gdtr.base & 0xffffff);
CYCLES(cpustate,CYCLES_SGDT);
break;
}
case 1: /* SIDT */
{
if (modrm >= 0xc0)
{
address = LOAD_RM16(modrm);
ea = i386_translate( cpustate, CS, address );
}
else
{
ea = GetEA(cpustate,modrm);
}
WRITE16(cpustate,ea, cpustate->idtr.limit);
WRITE32(cpustate,ea + 2, cpustate->idtr.base & 0xffffff);
CYCLES(cpustate,CYCLES_SIDT);
break;
}
case 2: /* LGDT */
{
if( modrm >= 0xc0 ) {
address = LOAD_RM16(modrm);
ea = i386_translate( cpustate, CS, address );
} else {
ea = GetEA(cpustate,modrm);
}
cpustate->gdtr.limit = READ16(cpustate,ea);
cpustate->gdtr.base = READ32(cpustate,ea + 2) & 0xffffff;
CYCLES(cpustate,CYCLES_LGDT);
break;
}
case 3: /* LIDT */
{
if( modrm >= 0xc0 ) {
address = LOAD_RM16(modrm);
ea = i386_translate( cpustate, CS, address );
} else {
ea = GetEA(cpustate,modrm);
}
cpustate->idtr.limit = READ16(cpustate,ea);
cpustate->idtr.base = READ32(cpustate,ea + 2) & 0xffffff;
CYCLES(cpustate,CYCLES_LIDT);
break;
}
case 4: /* SMSW */
{
if( modrm >= 0xc0 ) {
STORE_RM16(modrm, cpustate->cr[0]);
CYCLES(cpustate,CYCLES_SMSW_REG);
} else {
ea = GetEA(cpustate,modrm);
WRITE16(cpustate,ea, cpustate->cr[0]);
CYCLES(cpustate,CYCLES_SMSW_MEM);
}
break;
}
case 6: /* LMSW */
{
/* TODO: Check for protection fault */
UINT8 b;
if( modrm >= 0xc0 ) {
b = LOAD_RM8(modrm);
CYCLES(cpustate,CYCLES_LMSW_REG);
} else {
ea = GetEA(cpustate,modrm);
CYCLES(cpustate,CYCLES_LMSW_MEM);
b = READ8(cpustate,ea);
}
cpustate->cr[0] &= ~0x03;
cpustate->cr[0] |= b & 0x03;
break;
}
case 7: /* INVLPG */
{
/* Nothing to do ? */
break;
}
default:
i386_fatal("i486: unimplemented opcode 0x0f 01 /%d at %08X", (modrm >> 3) & 0x7, cpustate->eip - 2);
break;
}
}
static void I486OP(group0F01_32)(i386_state *cpustate) /* Opcode 0x0f 01 */
{
UINT8 modrm = FETCH(cpustate);
UINT32 address, ea;
switch( (modrm >> 3) & 0x7 )
{
case 0: /* SGDT */
{
if( modrm >= 0xc0 ) {
address = LOAD_RM32(modrm);
ea = i386_translate( cpustate, CS, address );
} else {
ea = GetEA(cpustate,modrm);
}
WRITE16(cpustate,ea, cpustate->gdtr.limit);
WRITE32(cpustate,ea + 2, cpustate->gdtr.base);
CYCLES(cpustate,CYCLES_SGDT);
break;
}
case 1: /* SIDT */
{
if (modrm >= 0xc0)
{
address = LOAD_RM32(modrm);
ea = i386_translate( cpustate, CS, address );
}
else
{
ea = GetEA(cpustate,modrm);
}
WRITE16(cpustate,ea, cpustate->idtr.limit);
WRITE32(cpustate,ea + 2, cpustate->idtr.base);
CYCLES(cpustate,CYCLES_SIDT);
break;
}
case 2: /* LGDT */
{
if( modrm >= 0xc0 ) {
address = LOAD_RM32(modrm);
ea = i386_translate( cpustate, CS, address );
} else {
ea = GetEA(cpustate,modrm);
}
cpustate->gdtr.limit = READ16(cpustate,ea);
cpustate->gdtr.base = READ32(cpustate,ea + 2);
CYCLES(cpustate,CYCLES_LGDT);
break;
}
case 3: /* LIDT */
{
if( modrm >= 0xc0 ) {
address = LOAD_RM32(modrm);
ea = i386_translate( cpustate, CS, address );
} else {
ea = GetEA(cpustate,modrm);
}
cpustate->idtr.limit = READ16(cpustate,ea);
cpustate->idtr.base = READ32(cpustate,ea + 2);
CYCLES(cpustate,CYCLES_LIDT);
break;
}
case 7: /* INVLPG */
{
/* Nothing to do ? */
break;
}
default:
i386_fatal("i486: unimplemented opcode 0x0f 01 /%d at %08X", (modrm >> 3) & 0x7, cpustate->eip - 2);
break;
}
}
static void I486OP(bswap_eax)(i386_state *cpustate) /* Opcode 0x0f 38 */
{
REG32(EAX) = SWITCH_ENDIAN_32(REG32(EAX));
CYCLES(cpustate,1); /* TODO */
}
static void I486OP(bswap_ecx)(i386_state *cpustate) /* Opcode 0x0f 39 */
{
REG32(ECX) = SWITCH_ENDIAN_32(REG32(ECX));
CYCLES(cpustate,1); /* TODO */
}
static void I486OP(bswap_edx)(i386_state *cpustate) /* Opcode 0x0f 3A */
{
REG32(EDX) = SWITCH_ENDIAN_32(REG32(EDX));
CYCLES(cpustate,1); /* TODO */
}
static void I486OP(bswap_ebx)(i386_state *cpustate) /* Opcode 0x0f 3B */
{
REG32(EBX) = SWITCH_ENDIAN_32(REG32(EBX));
CYCLES(cpustate,1); /* TODO */
}
static void I486OP(bswap_esp)(i386_state *cpustate) /* Opcode 0x0f 3C */
{
REG32(ESP) = SWITCH_ENDIAN_32(REG32(ESP));
CYCLES(cpustate,1); /* TODO */
}
static void I486OP(bswap_ebp)(i386_state *cpustate) /* Opcode 0x0f 3D */
{
REG32(EBP) = SWITCH_ENDIAN_32(REG32(EBP));
CYCLES(cpustate,1); /* TODO */
}
static void I486OP(bswap_esi)(i386_state *cpustate) /* Opcode 0x0f 3E */
{
REG32(ESI) = SWITCH_ENDIAN_32(REG32(ESI));
CYCLES(cpustate,1); /* TODO */
}
static void I486OP(bswap_edi)(i386_state *cpustate) /* Opcode 0x0f 3F */
{
REG32(EDI) = SWITCH_ENDIAN_32(REG32(EDI));
CYCLES(cpustate,1); /* TODO */
}
src/cpu/i386/pentops.c
+53
View File
@@ -0,0 +1,53 @@
/* Pentium+ specific opcodes */
static void PENTIUMOP(rdmsr)(i386_state *cpustate) /* Opcode 0x0f 32 */
{
/* TODO */
CYCLES(cpustate,CYCLES_RDMSR);
}
static void PENTIUMOP(wrmsr)(i386_state *cpustate) /* Opcode 0x0f 30 */
{
/* TODO */
CYCLES(cpustate,1); /* TODO: correct cycle count */
}
static void PENTIUMOP(rdtsc)(i386_state *cpustate) /* Opcode 0x0f 31 */
{
UINT64 ts = cpustate->tsc + (cpustate->base_cycles - i386_ICount);
REG32(EAX) = (UINT32)(ts);
REG32(EDX) = (UINT32)(ts >> 32);
CYCLES(cpustate,CYCLES_RDTSC);
}
static void I386OP(cyrix_unknown)(i386_state *cpustate) /* Opcode 0x0f 74 */
{
CYCLES(cpustate,1);
}
static void PENTIUMOP(cmpxchg8b_m64)(i386_state *cpustate) /* Opcode 0x0f c7 */
{
UINT8 modm = FETCH(cpustate);
if( modm >= 0xc0 ) {
i386_fatal("pentium: cmpxchg8b_m64 - invalid modm");
} else {
UINT32 ea = GetEA(cpustate,modm);
UINT64 value = READ64(cpustate,ea);
UINT64 edx_eax = (((UINT64) REG32(EDX)) << 32) | REG32(EAX);
UINT64 ecx_ebx = (((UINT64) REG32(ECX)) << 32) | REG32(EBX);
if( value == edx_eax ) {
WRITE64(cpustate,ea, ecx_ebx);
cpustate->ZF = 1;
CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_T);
} else {
REG32(EDX) = (UINT32) (value >> 32);
REG32(EAX) = (UINT32) (value >> 0);
cpustate->ZF = 0;
CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_F);
}
}
}
src/cpu/i386/x87ops.c
+352
View File
@@ -0,0 +1,352 @@
/* Intel x87 FPU opcodes */
#define ST(x) (cpustate->fpu_reg[(cpustate->fpu_top + (x)) & 7])
#define FPU_INFINITY_DOUBLE COMBINE_64_32_32(0x7ff00000, 0x00000000)
#define FPU_INFINITY_SINGLE (0x7f800000)
#define FPU_SIGN_BIT_DOUBLE COMBINE_64_32_32(0x80000000, 0x00000000)
#define FPU_SIGN_BIT_SINGLE (0x80000000)
/* FPU control word flags */
#define FPU_MASK_INVALID_OP 0x0001
#define FPU_MASK_DENORMAL_OP 0x0002
#define FPU_MASK_ZERO_DIVIDE 0x0004
#define FPU_MASK_OVERFLOW 0x0008
#define FPU_MASK_UNDERFLOW 0x0010
#define FPU_MASK_PRECISION 0x0020
/* FPU status word flags */
#define FPU_BUSY 0x8000
#define FPU_C3 0x4000
#define FPU_STACK_TOP_MASK 0x3800
#define FPU_C2 0x0400
#define FPU_C1 0x0200
#define FPU_C0 0x0100
#define FPU_ERROR_SUMMARY 0x0080
#define FPU_STACK_FAULT 0x0040
#define FPU_EXCEPTION_PRECISION 0x0020
#define FPU_EXCEPTION_UNDERFLOW 0x0010
#define FPU_EXCEPTION_OVERFLOW 0x0008
#define FPU_EXCEPTION_ZERO_DIVIDE 0x0004
#define FPU_EXCEPTION_DENORMAL_OP 0x0002
#define FPU_EXCEPTION_INVALID_OP 0x0001
static INLINE void FPU_PUSH(i386_state *cpustate, X87_REG value)
{
cpustate->fpu_top--;
if (cpustate->fpu_top < 0)
{
cpustate->fpu_top = 7;
}
cpustate->fpu_reg[cpustate->fpu_top] = value;
}
static INLINE X87_REG FPU_POP(i386_state *cpustate)
{
X87_REG value = cpustate->fpu_reg[cpustate->fpu_top];
cpustate->fpu_tag_word |= 3 << (cpustate->fpu_top * 2); /* set FPU register tag to 3 (empty) */
cpustate->fpu_top++;
if (cpustate->fpu_top > 7)
{
cpustate->fpu_top = 0;
}
return value;
}
static void I386OP(fpu_group_d8)(i386_state *cpustate) /* Opcode 0xd8 */
{
UINT8 modrm = FETCH(cpustate);
i386_fatal("I386: FPU Op D8 %02X at %08X", modrm, cpustate->pc-2);
}
static void I386OP(fpu_group_d9)(i386_state *cpustate) /* Opcode 0xd9 */
{
UINT8 modrm = FETCH(cpustate);
if (modrm < 0xc0)
{
UINT32 ea = GetEA(cpustate,modrm);
switch ((modrm >> 3) & 0x7)
{
case 5: /* FLDCW */
{
cpustate->fpu_control_word = READ16(cpustate,ea);
CYCLES(cpustate,1); /* TODO */
break;
}
case 7: /* FSTCW */
{
WRITE16(cpustate,ea, cpustate->fpu_control_word);
CYCLES(cpustate,1); /* TODO */
break;
}
default:
i386_fatal("I386: FPU Op D9 %02X at %08X", modrm, cpustate->pc-2);
}
}
else
{
switch (modrm & 0x3f)
{
/* FLD */
case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
{
X87_REG t = ST(modrm & 7);
FPU_PUSH(cpustate,t);
CYCLES(cpustate,1); /* TODO */
break;
}
case 0x20: /* FCHS */
{
ST(0).i ^= FPU_SIGN_BIT_DOUBLE;
CYCLES(cpustate,1); /* TODO */
break;
}
case 0x28: /* FLD1 */
{
X87_REG t;
t.f = 1.0;
FPU_PUSH(cpustate,t);
CYCLES(cpustate,1); /* TODO */
break;
}
case 0x2e: /* FLDZ */
{
X87_REG t;
t.f = 0.0;
FPU_PUSH(cpustate,t);
CYCLES(cpustate,1); /* TODO */
break;
}
default:
i386_fatal("I386: FPU Op D9 %02X at %08X", modrm, cpustate->pc-2);
}
}
}
static void I386OP(fpu_group_da)(i386_state *cpustate) /* Opcode 0xda */
{
UINT8 modrm = FETCH(cpustate);
i386_fatal("I386: FPU Op DA %02X at %08X", modrm, cpustate->pc-2);
}
static void I386OP(fpu_group_db)(i386_state *cpustate) /* Opcode 0xdb */
{
UINT8 modrm = FETCH(cpustate);
if (modrm < 0xc0)
{
i386_fatal("I386: FPU Op DB %02X at %08X", modrm, cpustate->pc-2);
}
else
{
switch (modrm & 0x3f)
{
case 0x23: /* FINIT */
{
cpustate->fpu_control_word = 0x37f;
cpustate->fpu_status_word = 0;
cpustate->fpu_tag_word = 0xffff;
cpustate->fpu_data_ptr = 0;
cpustate->fpu_inst_ptr = 0;
cpustate->fpu_opcode = 0;
CYCLES(cpustate,1); /* TODO */
break;
}
case 0x24: /* FSETPM (treated as nop on 387+) */
{
CYCLES(cpustate,1);
break;
}
default:
i386_fatal("I386: FPU Op DB %02X at %08X", modrm, cpustate->pc-2);
}
}
}
static void I386OP(fpu_group_dc)(i386_state *cpustate) /* Opcode 0xdc */
{
UINT8 modrm = FETCH(cpustate);
if (modrm < 0xc0)
{
/*UINT32 ea = GetEA(cpustate,modrm); */
switch ((modrm >> 3) & 0x7)
{
default:
i386_fatal("I386: FPU Op DC %02X at %08X", modrm, cpustate->pc-2);
}
}
else
{
switch (modrm & 0x3f)
{
case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
{
/* FDIVR */
if ((ST(modrm & 7).i & COMBINE_64_32_32(0x7fffffff, 0xffffffff)) == 0)
{
/* set result as infinity if zero divide is masked */
if (cpustate->fpu_control_word & FPU_MASK_ZERO_DIVIDE)
{
ST(modrm & 7).i |= FPU_INFINITY_DOUBLE;
}
}
else
{
ST(modrm & 7).f = ST(0).f / ST(modrm & 7).f;
}
CYCLES(cpustate,1); /* TODO */
break;
}
default:
i386_fatal("I386: FPU Op DC %02X at %08X", modrm, cpustate->pc-2);
}
}
}
static void I386OP(fpu_group_dd)(i386_state *cpustate) /* Opcode 0xdd */
{
UINT8 modrm = FETCH(cpustate);
if (modrm < 0xc0)
{
UINT32 ea = GetEA(cpustate,modrm);
switch ((modrm >> 3) & 0x7)
{
case 7: /* FSTSW */
{
WRITE16(cpustate,ea, (cpustate->fpu_status_word & ~FPU_STACK_TOP_MASK) | (cpustate->fpu_top << 10));
CYCLES(cpustate,1); /* TODO */
break;
}
default:
i386_fatal("I386: FPU Op DD %02X at %08X", modrm, cpustate->pc-2);
}
}
else
{
switch (modrm & 0x3f)
{
default:
i386_fatal("I386: FPU Op DD %02X at %08X", modrm, cpustate->pc-2);
}
}
}
static void I386OP(fpu_group_de)(i386_state *cpustate) /* Opcode 0xde */
{
UINT8 modrm = FETCH(cpustate);
if (modrm < 0xc0)
{
/* UINT32 ea = GetEA(cpustate,modrm); */
switch ((modrm >> 3) & 0x7)
{
default:
i386_fatal("I386: FPU Op DE %02X at %08X", modrm, cpustate->pc-2);
}
}
else
{
switch (modrm & 0x3f)
{
case 0x19: /* FCOMPP */
{
cpustate->fpu_status_word &= ~(FPU_C3 | FPU_C2 | FPU_C0);
if (ST(0).f > ST(1).f)
{
/* C3 = 0, C2 = 0, C0 = 0 */
}
else if (ST(0).f < ST(1).f)
{
cpustate->fpu_status_word |= FPU_C0;
}
else if (ST(0).f == ST(1).f)
{
cpustate->fpu_status_word |= FPU_C3;
}
else
{
/* unordered */
cpustate->fpu_status_word |= (FPU_C3 | FPU_C2 | FPU_C0);
}
FPU_POP(cpustate);
FPU_POP(cpustate);
CYCLES(cpustate,1); /* TODO */
break;
}
/* FDIVP */
case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x3d: case 0x3e: case 0x3f:
{
if ((ST(0).i & COMBINE_64_32_32(0x7fffffff, 0xffffffff)) == 0)
{
/* set result as infinity if zero divide is masked */
if (cpustate->fpu_control_word & FPU_MASK_ZERO_DIVIDE)
{
ST(modrm & 7).i |= FPU_INFINITY_DOUBLE;
}
}
else
{
ST(modrm & 7).f = ST(modrm & 7).f / ST(0).f;
}
FPU_POP(cpustate);
CYCLES(cpustate,1); /* TODO */
break;
}
default:
i386_fatal("I386: FPU Op DE %02X at %08X", modrm, cpustate->pc-2);
}
}
}
static void I386OP(fpu_group_df)(i386_state *cpustate) /* Opcode 0xdf */
{
UINT8 modrm = FETCH(cpustate);
if (modrm < 0xc0)
{
/* UINT32 ea = GetEA(cpustate,modrm); */
switch ((modrm >> 3) & 0x7)
{
default:
i386_fatal("I386: FPU Op DF %02X at %08X", modrm, cpustate->pc-2);
}
}
else
{
switch (modrm & 0x3f)
{
case 0x20: /* FSTSW AX */
{
REG16(AX) = (cpustate->fpu_status_word & ~FPU_STACK_TOP_MASK) | (cpustate->fpu_top << 10);
CYCLES(cpustate,1); /* TODO */
break;
}
default:
i386_fatal("I386: FPU Op DF %02X at %08X", modrm, cpustate->pc-2);
}
}
}
src/cpu/i86/i86.c
+48
View File
@@ -63,6 +63,7 @@ typedef struct
INT8 nmi_state;
INT8 irq_state;
int extra_cycles; /* extra cycles for interrupts */
INT8 test_state; /* the TEST input */
}
i86_Regs;
@@ -123,12 +124,53 @@ static void i86_state_register(void)
state_save_register_INT8( type, cpu, "NMI_STATE", &I.nmi_state, 1);
state_save_register_INT8( type, cpu, "IRQ_STATE", &I.irq_state, 1);
state_save_register_int( type, cpu, "EXTRA_CYCLES", &I.extra_cycles);
state_save_register_INT8( type, cpu, "TEST_STATE", &I.test_state, 1);
}
/* the 16-bit data bus, see i86intf.h */
int i86_bus16;
int i86_bus16_word;
unsigned i86_read_word16(unsigned ea)
{
unsigned lo, hi;
/* an odd address is two byte cycles on the 8086 too */
if (ea & 1)
{
lo = cpu_readmem20(ea);
hi = cpu_readmem20((ea + 1) & AMASK);
return lo | (hi << 8);
}
i86_bus16_word = 1;
lo = cpu_readmem20(ea);
hi = cpu_readmem20(ea + 1);
i86_bus16_word = 0;
return lo | (hi << 8);
}
void i86_write_word16(unsigned ea, unsigned val)
{
if (ea & 1)
{
cpu_writemem20(ea, val & 0xff);
cpu_writemem20((ea + 1) & AMASK, (val >> 8) & 0xff);
return;
}
i86_bus16_word = 1;
cpu_writemem20(ea, val & 0xff);
cpu_writemem20(ea + 1, (val >> 8) & 0xff);
i86_bus16_word = 0;
}
void i86_init(void)
{
unsigned int i, j, c;
BREGS reg_name[8] = {AL, CL, DL, BL, AH, CH, DH, BH};
/* the 16-bit data bus is off unless the driver turns it on */
i86_bus16 = 0;
i86_bus16_word = 0;
for (i = 0; i < 256; i++)
{
for (j = i, c = 0; j > 0; j >>= 1)
@@ -157,6 +199,7 @@ void i86_reset(void *param)
{
memset(&I, 0, sizeof (I));
I.test_state = 1;
I.sregs[CS] = 0xf000;
I.base[CS] = SegBase(CS);
I.pc = 0xffff0 & AMASK;
@@ -287,6 +330,11 @@ void i86_set_reg(int regnum, unsigned val)
void i86_set_irq_line(int irqline, int state)
{
if (irqline == I86_TEST_LINE)
{
I.test_state = (state != CLEAR_LINE);
return;
}
if (irqline == IRQ_LINE_NMI)
{
if (I.nmi_state == state)
src/cpu/i86/i86.h
+8 -4
View File
@@ -71,20 +71,24 @@ typedef enum { AL,AH,CL,CH,DL,DH,BL,BH,SPL,SPH,BPL,BPH,SIL,SIH,DIL,DIH } BREGS;
/************************************************************************/
/* the 16-bit data bus of the 8086 (see i86intf.h): off unless a driver turns it on */
unsigned i86_read_word16(unsigned ea);
void i86_write_word16(unsigned ea, unsigned val);
#define SegBase(Seg) (I.sregs[Seg] << 4)
#define DefaultBase(Seg) ((seg_prefix && (Seg == DS || Seg == SS)) ? prefix_base : I.base[Seg])
#define GetMemB(Seg,Off) (cpu_readmem20((DefaultBase(Seg) + (Off)) & AMASK))
#define GetMemW(Seg,Off) ((WORD)GetMemB(Seg, Off) + (WORD)(GetMemB(Seg, (Off) + 1) << 8))
#define GetMemW(Seg,Off) (i86_bus16 ? i86_read_word16((DefaultBase(Seg) + (Off)) & AMASK) : ((WORD)GetMemB(Seg, Off) + (WORD)(GetMemB(Seg, (Off) + 1) << 8)))
#define PutMemB(Seg,Off,x) cpu_writemem20((DefaultBase(Seg) + (Off)) & AMASK, (x))
#define PutMemW(Seg,Off,x) { PutMemB(Seg, Off, (x) & 0xff); PutMemB(Seg, (Off) + 1, ((x) >> 8) & 0xff); }
#define PutMemW(Seg,Off,x) { if (i86_bus16) i86_write_word16((DefaultBase(Seg) + (Off)) & AMASK, (x)); else { PutMemB(Seg, Off, (x) & 0xff); PutMemB(Seg, (Off) + 1, ((x) >> 8) & 0xff); } }
#define PEEKBYTE(ea) (cpu_readmem20((ea) & AMASK))
#define ReadByte(ea) (cpu_readmem20((ea) & AMASK))
#define ReadWord(ea) (cpu_readmem20((ea) & AMASK) + (cpu_readmem20(((ea) + 1) & AMASK) << 8))
#define ReadWord(ea) (i86_bus16 ? i86_read_word16((ea) & AMASK) : (cpu_readmem20((ea) & AMASK) + (cpu_readmem20(((ea) + 1) & AMASK) << 8)))
#define WriteByte(ea,val) cpu_writemem20((ea) & AMASK, val);
#define WriteWord(ea,val) { cpu_writemem20((ea) & AMASK, (val) & 0xff); cpu_writemem20(((ea) + 1) & AMASK, ((val) >> 8) & 0xff); }
#define WriteWord(ea,val) { if (i86_bus16) i86_write_word16((ea) & AMASK, (val)); else { cpu_writemem20((ea) & AMASK, (val) & 0xff); cpu_writemem20(((ea) + 1) & AMASK, ((val) >> 8) & 0xff); } }
#define read_port(port) cpu_readport16(port)
#define write_port(port,val) cpu_writeport16(port,val)
src/cpu/i86/i86intf.h
+14
View File
@@ -11,9 +11,23 @@ enum {
I86_VECTOR, I86_PENDING, I86_NMI_STATE, I86_IRQ_STATE
};
/* the TEST input (WAIT instruction): a CPU waits at a WAIT instruction
while it is cleared; it is asserted at reset, so WAIT goes on unless a
driver clears it */
#define I86_TEST_LINE 1
/* Public variables */
extern int i86_ICount;
/* The 8086 has a 16-bit data bus, but the core accesses memory a byte at a
time. A driver whose hardware needs an aligned word access to be one bus
cycle sets i86_bus16 (all the i86 CPUs of the machine): the core then
accesses an aligned word as its low byte then its high byte, with
i86_bus16_word set during the two accesses, so the handlers can make
them one 16-bit access. Off by default: nothing changes for the others. */
extern int i86_bus16;
extern int i86_bus16_word;
/* Public functions */
extern void i86_init(void);
src/cpu/i86/instr86.c
+37 -8
View File
@@ -544,8 +544,13 @@ static void PREFIX(rep)(int flagval)
for (; count > 0; count--)
{
if (ICOUNT <= 0) { I.pc = I.prevpc; break; }
PutMemB(ES,I.regs.w[DI],I.regs.b[AL]);
PutMemB(ES,I.regs.w[DI]+1,I.regs.b[AH]);
if (i86_bus16)
PutMemW(ES,I.regs.w[DI],I.regs.w[AX])
else
{
PutMemB(ES,I.regs.w[DI],I.regs.b[AL]);
PutMemB(ES,I.regs.w[DI]+1,I.regs.b[AH]);
}
I.regs.w[DI] += 2 * I.DirVal;
ICOUNT -= cycles.rep_stos16_count;
}
@@ -1994,6 +1999,15 @@ static void PREFIX86(_call_far)(void)
static void PREFIX86(_wait)(void) /* Opcode 0x9b */
{
#ifndef I286
/* the TEST input cleared: wait on this instruction */
if (!I.test_state)
{
ICOUNT = 0;
I.pc--;
return;
}
#endif
ICOUNT -= cycles.wait;
}
@@ -2060,8 +2074,13 @@ static void PREFIX86(_mov_axdisp)(void) /* Opcode 0xa1 */
addr += FETCH << 8;
ICOUNT -= cycles.mov_am16;
I.regs.b[AL] = GetMemB(DS, addr);
I.regs.b[AH] = GetMemB(DS, addr+1);
if (i86_bus16)
I.regs.w[AX] = GetMemW(DS, addr);
else
{
I.regs.b[AL] = GetMemB(DS, addr);
I.regs.b[AH] = GetMemB(DS, addr+1);
}
}
static void PREFIX86(_mov_dispal)(void) /* Opcode 0xa2 */
@@ -2083,8 +2102,13 @@ static void PREFIX86(_mov_dispax)(void) /* Opcode 0xa3 */
addr += FETCH << 8;
ICOUNT -= cycles.mov_ma16;
PutMemB(DS, addr, I.regs.b[AL]);
PutMemB(DS, addr+1, I.regs.b[AH]);
if (i86_bus16)
PutMemW(DS, addr, I.regs.w[AX])
else
{
PutMemB(DS, addr, I.regs.b[AL]);
PutMemB(DS, addr+1, I.regs.b[AH]);
}
}
static void PREFIX86(_movsb)(void) /* Opcode 0xa4 */
@@ -2148,8 +2172,13 @@ static void PREFIX86(_stosb)(void) /* Opcode 0xaa */
static void PREFIX86(_stosw)(void) /* Opcode 0xab */
{
PutMemB(ES,I.regs.w[DI],I.regs.b[AL]);
PutMemB(ES,I.regs.w[DI]+1,I.regs.b[AH]);
if (i86_bus16)
PutMemW(ES,I.regs.w[DI],I.regs.w[AX])
else
{
PutMemB(ES,I.regs.w[DI],I.regs.b[AL]);
PutMemB(ES,I.regs.w[DI]+1,I.regs.b[AH]);
}
I.regs.w[DI] += 2 * I.DirVal;
ICOUNT -= cycles.stos16;
}
src/cpu/i960/i960.c
+34 -2
View File
@@ -120,9 +120,33 @@ static INLINE int i960_is_burst( UINT32 address )
return i960_burst_cb == NULL || i960_burst_cb( address );
}
/* port: the opcodes are read straight from the memory block of the last
fetch (ROM, RAM or a bank: what cpu_readmem32ledw_dword reads there);
anything else goes through the memory system. Forgotten at every
timeslice, as the banks are only set up between them */
static UINT32 i960_fetch_start, i960_fetch_len;
static const UINT8 *i960_fetch_ptr;
static UINT32 i960_readop_slow( UINT32 address )
{
offs_t start, len;
const UINT8 *p = (const UINT8 *)memory_get_read_range( cpu_getactivecpu(), address, &start, &len );
if( p != NULL )
{
/* the block in the CPU's addresses (the mask only drops high bits) */
i960_fetch_start = address - ( ( address & mem_amask ) - start );
i960_fetch_len = len;
i960_fetch_ptr = p;
}
return cpu_readmem32ledw_dword( address );
}
static INLINE UINT32 i960_readop( UINT32 address )
{
return cpu_readmem32ledw_dword( address );
UINT32 off = address - i960_fetch_start;
if( off < i960_fetch_len )
return *(const data32_t *)( i960_fetch_ptr + ( off & ~3 ) );
return i960_readop_slow( address );
}
static void i960_fatal( const char *fmt, ... )
@@ -880,7 +904,14 @@ static void execute_burst_stall_op(UINT32 opcode)
check_immediate_irqs();
}
static void execute_op(UINT32 opcode)
/* port: inlined in its only caller, the i960_execute loop: as a function,
saving and restoring its registers on every instruction cost a fifth of
the time spent in the CPU */
#if defined(__GNUC__)
static INLINE __attribute__((always_inline)) void execute_op(UINT32 opcode)
#else
static INLINE void execute_op(UINT32 opcode)
#endif
{
UINT32 t1, t2;
double t1f, t2f;
@@ -2521,6 +2552,7 @@ int i960_execute( int cycles )
UINT32 opcode;
i960_icount = cycles;
i960_fetch_len = 0;
/* delay checking irqs if we are in burst stall mode */
if( m_stall_state.burst_mode == 0 )
src/cpu/konami/konami.c
+1
View File
@@ -483,6 +483,7 @@ void konami_init(void)
state_save_register_UINT8("konami", cpu, "NMI", &konami.nmi_state, 1);
state_save_register_UINT8("konami", cpu, "IRQ", &konami.irq_state[0], 1);
state_save_register_UINT8("konami", cpu, "FIRQ", &konami.irq_state[1], 1);
state_save_register_int("konami", cpu, "extra_cycles", &konami.extra_cycles); /* the cycles of an interrupt taken outside the execute loop */
}
void konami_reset(void *param)
src/cpu/m37710/m37710.c
+22 -7
View File
@@ -413,6 +413,9 @@ static void m37710_timer_b2_cb(int param)
cpuintrf_pop_context();
}
/* timer A output pins (set by the driver just before it clocks the timer, not saved) */
static int m37710_timer_out[5];
static void m37710_external_tick(int timer, int state)
{
/* we only care if the state is "on" */
@@ -426,15 +429,22 @@ static void m37710_external_tick(int timer, int state)
{
if ((m37710i_cpu.m37710_regs[0x56+timer] & 0x3) == 1)
{
if (m37710i_cpu.m37710_regs[0x46+(timer*2)] == 0xff)
/* the count direction, as current MAME: timer B counts down; timer A
follows its output pin (mode bit 4) or the up/down register */
int upcount = 0;
UINT16 count = m37710i_cpu.m37710_regs[0x46+(timer*2)] | (m37710i_cpu.m37710_regs[0x46+(timer*2)+1] << 8);
if (timer <= 4)
{
m37710i_cpu.m37710_regs[0x46+(timer*2)] = 0;
m37710i_cpu.m37710_regs[0x46+(timer*2)+1]++;
}
else
{
m37710i_cpu.m37710_regs[0x46+(timer*2)]++;
if (m37710i_cpu.m37710_regs[0x56+timer] & 0x10)
upcount = m37710_timer_out[timer];
else
upcount = (m37710i_cpu.m37710_regs[0x44] >> timer) & 1;
}
count = upcount ? count + 1 : count - 1;
m37710i_cpu.m37710_regs[0x46+(timer*2)] = count & 0xff;
m37710i_cpu.m37710_regs[0x46+(timer*2)+1] = count >> 8;
}
else
{
@@ -1086,6 +1096,11 @@ void m37710_set_irq_line(int line, int state)
m37710_external_tick(line - M37710_LINE_TIMERA0TICK, state);
return;
}
if (line >= M37710_LINE_TIMERA0OUT && line <= M37710_LINE_TIMERA4OUT)
{
m37710_timer_out[line - M37710_LINE_TIMERA0OUT] = (state != CLEAR_LINE);
return;
}
FTABLE_SET_LINE(line, state);
}
src/cpu/m37710/m37710.h
+7
View File
@@ -63,6 +63,13 @@ enum
M37710_LINE_TIMERB1TICK,
M37710_LINE_TIMERB2TICK,
/* timer A output pins: the count direction of an event counter in up/down pin mode */
M37710_LINE_TIMERA0OUT,
M37710_LINE_TIMERA1OUT,
M37710_LINE_TIMERA2OUT,
M37710_LINE_TIMERA3OUT,
M37710_LINE_TIMERA4OUT,
M37710_LINE_MAX
};
src/cpu/m6800/m6800.c
+18
View File
@@ -554,6 +554,24 @@ static void state_register(const char *type)
state_save_register_UINT8 (type, cpu, "NMI_STATE", &m6800.nmi_state, 1);
state_save_register_UINT8 (type, cpu, "IRQ_STATE", &m6800.irq_state[M6800_IRQ_LINE], 1);
state_save_register_UINT8 (type, cpu, "TIN_STATE", &m6800.irq_state[M6800_TIN_LINE], 1);
state_save_register_UINT16(type, cpu, "PPC", &m6800.ppc.w.l, 1);
state_save_register_UINT8 (type, cpu, "WAI_STATE", &m6800.wai_state, 1);
state_save_register_UINT8 (type, cpu, "IC_EDDGE", &m6800.ic_eddge, 1);
state_save_register_int (type, cpu, "EXTRA_CYCLES", &m6800.extra_cycles);
/* the internal registers of the 6801/6803/63701: ports, timer, RAM control */
state_save_register_UINT8 (type, cpu, "PORT1_DDR", &m6800.port1_ddr, 1);
state_save_register_UINT8 (type, cpu, "PORT2_DDR", &m6800.port2_ddr, 1);
state_save_register_UINT8 (type, cpu, "PORT1_DATA", &m6800.port1_data, 1);
state_save_register_UINT8 (type, cpu, "PORT2_DATA", &m6800.port2_data, 1);
state_save_register_UINT8 (type, cpu, "TCSR", &m6800.tcsr, 1);
state_save_register_UINT8 (type, cpu, "PENDING_TCSR", &m6800.pending_tcsr, 1);
state_save_register_UINT8 (type, cpu, "IRQ2", &m6800.irq2, 1);
state_save_register_UINT8 (type, cpu, "RAM_CTRL", &m6800.ram_ctrl, 1);
state_save_register_UINT32(type, cpu, "COUNTER", &m6800.counter.d, 1);
state_save_register_UINT32(type, cpu, "OUTPUT_COMPARE", &m6800.output_compare.d, 1);
state_save_register_UINT16(type, cpu, "INPUT_CAPTURE", &m6800.input_capture, 1);
state_save_register_UINT32(type, cpu, "TIMER_OVER", &m6800.timer_over.d, 1);
state_save_register_UINT32(type, cpu, "TIMER_NEXT", &timer_next, 1);
}
void m6800_init(void)
src/cpu/m68000/m68k.h
+8
View File
@@ -260,6 +260,14 @@ void m68k_set_fc_callback(void (*callback)(unsigned int new_fc));
*/
void m68k_set_instr_hook_callback(void (*callback)(void));
/* Called after CMPI.L #imm,Dn with the immediate value and the register
* number, and when an RTE is executed in supervisor mode. The FD1094 changes
* its decryption state on these. Shared by all the 68000 CPUs; m68k_init()
* clears them.
*/
extern void (*m68k_cmpild_callback)(unsigned int val, int reg);
extern void (*m68k_rte_callback)(void);
/* ======================================================================== */
src/cpu/m68000/m68k_in.c
+16
View File
@@ -4178,6 +4178,14 @@ M68KMAKE_OP(cmpi, 32, ., d)
FLAG_Z = MASK_OUT_ABOVE_32(res);
FLAG_V = VFLAG_SUB_32(src, dst, res);
FLAG_C = CFLAG_SUB_32(src, dst, res);
if (m68k_cmpild_callback)
{
m68k_cmpild_callback(src, REG_IR & 7);
#if M68K_EMULATE_PREFETCH
CPU_PREF_ADDR = 1; /* the next words are fetched again (FD1094 state change) */
#endif
}
}
@@ -8968,6 +8976,14 @@ M68KMAKE_OP(rte, 32, ., .)
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
if (m68k_rte_callback)
{
m68k_rte_callback();
#if M68K_EMULATE_PREFETCH
CPU_PREF_ADDR = 1; /* fetched again with the new state */
#endif
}
if(CPU_TYPE_IS_000(CPU_TYPE))
{
new_sr = m68ki_pull_16();
src/cpu/m68000/m68kcpu.c
+6
View File
@@ -68,6 +68,10 @@ char* m68ki_cpu_names[9] =
/* The CPU core */
m68ki_cpu_core m68ki_cpu = {0};
/* FD1094 hooks, shared by all the 68000 CPUs (see m68k.h) */
void (*m68k_cmpild_callback)(unsigned int val, int reg) = NULL;
void (*m68k_rte_callback)(void) = NULL;
#if M68K_EMULATE_ADDRESS_ERROR
jmp_buf m68ki_aerr_trap;
#endif /* M68K_EMULATE_ADDRESS_ERROR */
@@ -755,6 +759,8 @@ void m68k_init(void)
m68k_set_pc_changed_callback(NULL);
m68k_set_fc_callback(NULL);
m68k_set_instr_hook_callback(NULL);
m68k_cmpild_callback = NULL;
m68k_rte_callback = NULL;
}
/* Pulse the RESET line on the CPU */
src/cpu/m68000/m68kopac.c
+8
View File
@@ -11782,6 +11782,14 @@ void m68k_op_cmpi_32_d(void)
FLAG_Z = MASK_OUT_ABOVE_32(res);
FLAG_V = VFLAG_SUB_32(src, dst, res);
FLAG_C = CFLAG_SUB_32(src, dst, res);
if (m68k_cmpild_callback)
{
m68k_cmpild_callback(src, REG_IR & 7);
#if M68K_EMULATE_PREFETCH
CPU_PREF_ADDR = 1; /* the next words are fetched again (FD1094 state change) */
#endif
}
}
src/cpu/m68000/m68kopnz.c
+8
View File
@@ -3924,6 +3924,14 @@ void m68k_op_rte_32(void)
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
if (m68k_rte_callback)
{
m68k_rte_callback();
#if M68K_EMULATE_PREFETCH
CPU_PREF_ADDR = 1; /* fetched again with the new state */
#endif
}
if(CPU_TYPE_IS_000(CPU_TYPE))
{
new_sr = m68ki_pull_16();
src/cpu/m6809/m6809.c
+2
View File
@@ -512,12 +512,14 @@ void m6809_init(void)
state_save_register_UINT16("m6809", cpu, "S", &S, 1);
state_save_register_UINT16("m6809", cpu, "X", &X, 1);
state_save_register_UINT16("m6809", cpu, "Y", &Y, 1);
state_save_register_UINT16("m6809", cpu, "D", &D, 1); /* the accumulators A and B */
state_save_register_UINT8("m6809", cpu, "DP", &DP, 1);
state_save_register_UINT8("m6809", cpu, "CC", &CC, 1);
state_save_register_UINT8("m6809", cpu, "INT", &m6809.int_state, 1);
state_save_register_UINT8("m6809", cpu, "NMI", &m6809.nmi_state, 1);
state_save_register_UINT8("m6809", cpu, "IRQ", &m6809.irq_state[0], 1);
state_save_register_UINT8("m6809", cpu, "FIRQ", &m6809.irq_state[1], 1);
state_save_register_int("m6809", cpu, "extra_cycles", &m6809.extra_cycles); /* the cycles of an interrupt taken outside the execute loop */
}
void m6809_reset(void *param)
src/cpu/mb86233/mb86233.c
+2
View File
@@ -1160,6 +1160,8 @@ void mb86233_init( void )
state_save_register_int( "mb86233", cpu, "gpio1", &mb.gpio[ 1 ] );
state_save_register_int( "mb86233", cpu, "gpio2", &mb.gpio[ 2 ] );
state_save_register_int( "mb86233", cpu, "gpio3", &mb.gpio[ 3 ] );
/* a stalled FIFO access is retried when the CPU runs again */
state_save_register_int( "mb86233", cpu, "stall", &mb.stall );
}
void mb86233_reset( void *param )
src/cpu/mips/psx.h
+3
View File
@@ -223,6 +223,9 @@ extern void psxcpu_ram_written(const void *host, UINT32 bytes);
per machine. */
extern int psxcpu_jit_available(void);
extern void psxcpu_set_jit(int enable);
/* fn is called before the instruction at pc runs (NULL: none); set at */
/* machine init, cleared at the CPU init */
extern void psxcpu_set_pc_hook(UINT32 pc, void (*fn)(void));
#ifdef MAME_DEBUG
extern unsigned DasmMIPS(char *buff, unsigned _pc);
src/cpu/mips/psx_cpu.c
+22
View File
@@ -348,6 +348,12 @@ static INLINE void psx_write32( offs_t address, data32_t data )
cpu_writemem32ledw_dword( address, data );
}
/* a driver hook called before the instruction at one address runs (the */
/* hacks MAME does with a debugger breakpoint or a read tap on the code) */
#define PC_HOOK_NONE 1 /* never an instruction address */
static UINT32 pc_hook_pc = PC_HOOK_NONE;
static void ( *pc_hook_fn )( void );
static void loop_arrive( UINT32 l, UINT32 from );
static int loop_kind( UINT32 l );
static int loop_pure_armed;
@@ -539,6 +545,8 @@ void mips_init( void )
fastram_count = 0;
fastram_last = &fastram[ 0 ];
psxcpu_set_jit( 0 );
pc_hook_pc = PC_HOOK_NONE;
pc_hook_fn = NULL;
state_save_register_UINT32( "psxcpu", cpu, "op", &mipscpu.op, 1 );
state_save_register_UINT32( "psxcpu", cpu, "pc", &mipscpu.pc, 1 );
@@ -565,6 +573,16 @@ void mips_reset( void *param )
void mips_exit( void )
{
psxcpu_set_jit( 0 );
pc_hook_pc = PC_HOOK_NONE;
pc_hook_fn = NULL;
}
void psxcpu_set_pc_hook( UINT32 pc, void ( *fn )( void ) )
{
pc_hook_pc = fn != NULL && ( pc & 3 ) == 0 ? pc : PC_HOOK_NONE;
pc_hook_fn = fn;
/* the recompiler leaves that instruction to the interpreter */
jit_reset_flush();
}
/* one instruction at mipscpu.pc (opcode in mipscpu.op), without the cycle */
@@ -1789,6 +1807,10 @@ int mips_execute( int cycles )
}
{
UINT32 from = mipscpu.pc;
if( from == pc_hook_pc )
{
pc_hook_fn();
}
mipscpu.op = cpu_readop32( from );
mips_step();
mips_ICount--;
src/cpu/mips/psxjit.c
+5
View File
@@ -1377,6 +1377,11 @@ static void jit_compile( struct jit_block *block, UINT32 pc )
{
maxcount = JIT_MAX_BLOCK;
}
/* the hooked instruction runs in the interpreter: the block stops before it */
if( pc_hook_pc != PC_HOOK_NONE && pc_hook_pc >= pc && ( pc_hook_pc - pc ) / 4 < maxcount )
{
maxcount = ( pc_hook_pc - pc ) / 4;
}
for( i = 0; i < maxcount; i++ )
{
ops[ i ] = *(const UINT32 *)( host + i * 4 );
src/cpu/namcoc71/c71.c
+1650
View File
File diff suppressed because it is too large. Load diff
src/cpu/namcoc71/c71.h
+75
View File
@@ -0,0 +1,75 @@
/***************************************************************************
Namco C71 (TMS320C25 with Namco internal ROM) - fast DSP core
Written for Namco System 22 / Super System 22. The instruction
semantics follow the TMS320C2x core of current MAME; the memory
system is a page table set up by the driver, so the core does not
go through the generic memory handlers.
Word addresses everywhere: program, data and I/O are 16-bit word
spaces.
***************************************************************************/
#ifndef C71_H
#define C71_H
#include "osd_cpu.h"
#include "cpuintrf.h"
#include "memory.h"
/* interrupt lines (IFR bits) */
#define C71_INT0 0
#define C71_INT1 1
#define C71_INT2 2
#define C71_TINT 3
#define C71_RINT 4
#define C71_XINT 5
enum
{
C71_PC=1,
C71_PFC, C71_STR0, C71_STR1, C71_IFR,
C71_RPTC, C71_ACC, C71_PREG, C71_TREG,
C71_AR0, C71_AR1, C71_AR2, C71_AR3,
C71_AR4, C71_AR5, C71_AR6, C71_AR7,
C71_STK0, C71_STK1, C71_STK2, C71_STK3,
C71_STK4, C71_STK5, C71_STK6, C71_STK7,
C71_DRR, C71_DXR, C71_TIM, C71_PRD,
C71_IMR, C71_GREG
};
/* the generic memory interface is not used: give the CPU empty maps */
#define NAMCOC71_PGM_OFFSET 0
typedef data16_t (*c71_read_fn)(offs_t offset);
typedef void (*c71_write_fn)(offs_t offset, data16_t data);
/* driver configuration, by CPU number; call from DRIVER_INIT or MACHINE_INIT */
void c71_set_internal_rom(int cpunum, const data16_t *rom); /* 0x1000 words, native order (a CPU region) */
void c71_map_data(int cpunum, offs_t start, offs_t end, data16_t *base, int writable);
void c71_map_program(int cpunum, offs_t start, offs_t end, data16_t *base, int writable);
void c71_set_data_handlers(int cpunum, c71_read_fn rd, c71_write_fn wr); /* everything not mapped */
void c71_set_io(int cpunum, int port, c71_read_fn rd, c71_write_fn wr);
void c71_set_bio(int cpunum, int (*bio)(void));
void c71_set_serial(int cpunum, data16_t (*dr_in)(void), void (*dx_out)(data16_t));
/* the DSP spins in [pc_start, pc_end] waiting for BIO or an interrupt: burn the timeslice there */
void c71_set_idle_loop(int cpunum, int slot, UINT16 pc_start, UINT16 pc_end);
extern int c71_icount;
void c71_init(void);
void c71_reset(void *param);
void c71_exit(void);
int c71_execute(int cycles);
unsigned c71_get_context(void *dst);
void c71_set_context(void *src);
unsigned c71_get_reg(int regnum);
void c71_set_reg(int regnum, unsigned val);
void c71_set_irq_line(int irqline, int state);
void c71_set_irq_callback(int (*callback)(int irqline));
const char *c71_info(void *context, int regnum);
unsigned c71_dasm(char *buffer, unsigned pc);
#endif
src/cpu/nec/v25.c
+1306
View File
File diff suppressed because it is too large. Load diff
src/cpu/nec/v25.h
+53
View File
@@ -0,0 +1,53 @@
/*****************************************************************************
NEC V25 (and V25+) CPU, see v25.c
license:BSD-3-Clause
copyright-holders:Bryan McPhail, Alex W. Jackson
*****************************************************************************/
#ifndef V25_H
#define V25_H
#include "memory.h"
#include "osd_cpu.h"
/* input lines, besides 0 (INT) and IRQ_LINE_NMI */
#define V25_INPUT_LINE_INTP0 10
#define V25_INPUT_LINE_INTP1 11
#define V25_INPUT_LINE_INTP2 12
#define V25_INPUT_LINE_POLL 20
enum
{
V25_PC=1, V25_IP, V25_AW, V25_CW, V25_DW, V25_BW, V25_SP, V25_BP, V25_IX, V25_IY,
V25_DS1, V25_PS, V25_SS, V25_DS0, V25_PSW, V25_IDB, V25_PENDING
};
extern int v25_ICount;
extern void v25_init(void);
extern void v25_reset(void *param);
extern void v25_exit(void);
extern int v25_execute(int cycles);
extern unsigned v25_get_context(void *dst);
extern void v25_set_context(void *src);
extern unsigned v25_get_reg(int regnum);
extern void v25_set_reg(int regnum, unsigned val);
extern void v25_set_irq_line(int irqline, int state);
extern void v25_set_irq_callback(int (*callback)(int irqline));
extern const char *v25_info(void *context, int regnum);
extern unsigned v25_dasm(char *buffer, unsigned pc);
/* Configuration, from DRIVER_INIT (before the CPU is reset).
The opcodes are decrypted with the table when the CPU is in secure
mode (the default when there is a table). */
extern void v25_set_decryption_table(int cpunum, const UINT8 *table);
/* the port pins: PT (input only), P0, P1 (upper 4 bits), P2 */
extern void v25_set_port_handlers(int cpunum,
read8_handler pt_in, read8_handler p0_in, read8_handler p1_in, read8_handler p2_in,
write8_handler p0_out, write8_handler p1_out, write8_handler p2_out);
#endif
src/cpu/nec/v25ops.h
+1710
View File
File diff suppressed because it is too large. Load diff
src/cpu/pic16c5x/pic16c5x.c
+3 -5
View File
@@ -704,11 +704,9 @@ void pic16C5x_init(void)
state_save_register_UINT8("pic16C5x", cpu, "TRISA", &R.TRISA, 1);
state_save_register_UINT8("pic16C5x", cpu, "TRISB", &R.TRISB, 1);
state_save_register_UINT8("pic16C5x", cpu, "TRISC", &R.TRISC, 1);
state_save_register_UINT8("pic16C5x", cpu, "PORTA", &R.PORTA, 1);
state_save_register_UINT8("pic16C5x", cpu, "PORTB", &R.PORTB, 1);
state_save_register_UINT8("pic16C5x", cpu, "PORTC", &R.PORTC, 1);
state_save_register_UINT8("pic16C5x", cpu, "Old_T0", &old_T0, 1);
state_save_register_UINT8("pic16C5x", cpu, "STR", &R.STATUS, 1);
/* STATUS and the ports are in the data RAM (picRAM), saved with the memory
of the CPU: R.picRAM is not set yet here */
state_save_register_UINT8("pic16C5x", cpu, "RAM_mask", &picRAMmask, 1);
state_save_register_UINT16("pic16C5x", cpu, "WDT", &R.WDT, 1);
state_save_register_UINT16("pic16C5x", cpu, "Prescaler", &R.prescaler, 1);
@@ -858,7 +856,7 @@ int pic16C5x_execute(int cycles)
CALL_MAME_DEBUG;
R.opcode.d = M_RDOP(R.PC);
R.PC++;
R.PC = (R.PC + 1) & ADDR_MASK; /* wraps to 0 after the reset vector 0x7ff of the 2K parts */
R.PCL++;
if ((R.opcode.w.l & 0xff0) != 0x000) { /* Do all opcodes except the 00? ones */
src/cpu/sh2/sh2.c
+187 -100
View File
@@ -147,10 +147,23 @@ typedef struct
int is_slave, cpu_number;
data16_t (*opcode_read)(offs_t pc);
data32_t (*dma_read_hook)(UINT32 src, UINT32 dst, data32_t data, int size);
UINT8 **jit_rpage; /* sh2jit.c: this CPU's page tables for direct reads and writes */
UINT8 **jit_wpage;
} SH2;
int sh2_icount;
static SH2 sh2;
/*
The state of the active SH-2 is its own context buffer: switching
CPUs (every timeslice, many thousand times a frame on the ST-V with
its tight interleave) only moves this pointer instead of copying
the whole state out and in. Each CPU's saved state items point into
its buffer too, so a state save reads it whether it is active or not.
*/
static SH2 sh2_boot; /* before a CPU's buffer is known */
static SH2 *sh2p = &sh2_boot;
#define sh2 (*sh2p)
/* Atrocious hack that makes the soldivid music correct*/
@@ -179,6 +192,16 @@ static void sh2_timer_callback(int data);
#define Rn ((opcode>>8)&15)
#define Rm ((opcode>>4)&15)
#ifdef SH2JIT_VERIFY
extern int sh2_jit_verify_logging;
void sh2_jit_verify_store(UINT32 address, int size);
#define SH2JIT_STORE(A, size) do { if (sh2_jit_verify_logging) sh2_jit_verify_store(A, size); if (sh2_jit_code_present) sh2_jit_ram_written((A) & AM, size); } while (0)
#else
/* a store over translated code flushes the recompiler's cache */
#define SH2JIT_STORE(A, size) do { if (sh2_jit_code_present) sh2_jit_ram_written((A) & AM, size); } while (0)
#endif
static INLINE data8_t RB(offs_t A)
{
if (A >= 0xe0000000)
@@ -233,6 +256,7 @@ static INLINE void WB(offs_t A, data8_t V)
if (A >= 0xc0000000)
{
cpu_writemem32bedw(A,V);
SH2JIT_STORE(A, 1);
return;
}
@@ -240,6 +264,7 @@ static INLINE void WB(offs_t A, data8_t V)
return;
cpu_writemem32bedw(A & AM,V);
SH2JIT_STORE(A, 1);
}
static INLINE void WW(offs_t A, data16_t V)
@@ -253,6 +278,7 @@ static INLINE void WW(offs_t A, data16_t V)
if (A >= 0xc0000000)
{
cpu_writemem32bedw_word(A,V);
SH2JIT_STORE(A, 2);
return;
}
@@ -260,6 +286,7 @@ static INLINE void WW(offs_t A, data16_t V)
return;
cpu_writemem32bedw_word(A & AM,V);
SH2JIT_STORE(A, 2);
}
static INLINE void WL(offs_t A, data32_t V)
@@ -273,6 +300,7 @@ static INLINE void WL(offs_t A, data32_t V)
if (A >= 0xc0000000)
{
cpu_writemem32bedw_dword(A,V);
SH2JIT_STORE(A, 4);
return;
}
@@ -280,6 +308,7 @@ static INLINE void WL(offs_t A, data32_t V)
return;
cpu_writemem32bedw_dword(A & AM,V);
SH2JIT_STORE(A, 4);
}
static INLINE void sh2_exception(const char *message, int irqline)
@@ -2291,6 +2320,61 @@ static INLINE void op1111(UINT16 opcode)
NOP();
}
/* one instruction (in the interpreter's loop and for the recompiler's checks) */
static INLINE void sh2_dispatch(UINT16 opcode)
{
switch ((opcode >> 12) & 15)
{
case 0: op0000(opcode); break;
case 1: op0001(opcode); break;
case 2: op0010(opcode); break;
case 3: op0011(opcode); break;
case 4: op0100(opcode); break;
case 5: op0101(opcode); break;
case 6: op0110(opcode); break;
case 7: op0111(opcode); break;
case 8: op1000(opcode); break;
case 9: op1001(opcode); break;
case 10: op1010(opcode); break;
case 11: op1011(opcode); break;
case 12: op1100(opcode); break;
case 13: op1101(opcode); break;
case 14: op1110(opcode); break;
default: op1111(opcode); break;
}
}
static INLINE void sh2_step(void)
{
UINT32 opcode;
if (sh2.delay)
{
opcode = sh2.opcode_read ? sh2.opcode_read(sh2.delay) : RW(sh2.delay & AM);
change_pc32bedw(sh2.pc & AM);
sh2.pc -= 2;
}
else
opcode = sh2.opcode_read ? sh2.opcode_read(sh2.pc) : RW(sh2.pc & AM);
CALL_MAME_DEBUG;
sh2.delay = 0;
sh2.pc += 2;
sh2.ppc = sh2.pc;
sh2_dispatch(opcode);
if(sh2.test_irq && !sh2.delay)
{
CHECK_PENDING_IRQ("mame_sh2_execute");
sh2.test_irq = 0;
}
sh2_icount--;
}
#include "sh2jit.c"
/*****************************************************************************
* MAME CPU INTERFACE
*****************************************************************************/
@@ -2324,6 +2408,10 @@ void sh2_reset(void *param)
sh2.cpu_number = cpu_getactivecpu();
/* code and memory handlers may differ after a reset */
if (jit_enabled)
jit_flush();
sh2.pc = RL(0);
sh2.r[15] = RL(4);
sh2.sr = I;
@@ -2335,11 +2423,15 @@ void sh2_reset(void *param)
/* Shut down CPU core */
void sh2_exit(void)
{
sh2_jit_set(0);
if (sh2.m)
free(sh2.m);
sh2.m = NULL;
/* the core frees the buffers after this */
sh2p = &sh2_boot;
}
/* Execute cycles - returns number of cycles actually run */
int sh2_execute(int cycles)
{
@@ -2350,49 +2442,10 @@ int sh2_execute(int cycles)
do
{
UINT32 opcode;
if (sh2.delay)
{
opcode = sh2.opcode_read ? sh2.opcode_read(sh2.delay) : RW(sh2.delay & AM);
change_pc32bedw(sh2.pc & AM);
sh2.pc -= 2;
}
else
opcode = sh2.opcode_read ? sh2.opcode_read(sh2.pc) : RW(sh2.pc & AM);
CALL_MAME_DEBUG;
sh2.delay = 0;
sh2.pc += 2;
sh2.ppc = sh2.pc;
switch ((opcode >> 12) & 15)
{
case 0: op0000(opcode); break;
case 1: op0001(opcode); break;
case 2: op0010(opcode); break;
case 3: op0011(opcode); break;
case 4: op0100(opcode); break;
case 5: op0101(opcode); break;
case 6: op0110(opcode); break;
case 7: op0111(opcode); break;
case 8: op1000(opcode); break;
case 9: op1001(opcode); break;
case 10: op1010(opcode); break;
case 11: op1011(opcode); break;
case 12: op1100(opcode); break;
case 13: op1101(opcode); break;
case 14: op1110(opcode); break;
default: op1111(opcode); break;
}
if(sh2.test_irq && !sh2.delay)
{
CHECK_PENDING_IRQ("mame_sh2_execute");
sh2.test_irq = 0;
}
sh2_icount--;
/* a block, when there is one for the PC (no slot or interrupt test pending) */
if (jit_enabled && !sh2.delay && !sh2.test_irq && sh2_jit_run())
continue;
sh2_step();
} while( sh2_icount > 0 );
return cycles - sh2_icount;
@@ -2401,16 +2454,17 @@ int sh2_execute(int cycles)
/* Get registers, return context size */
unsigned sh2_get_context(void *dst)
{
if( dst )
memcpy(dst, &sh2, sizeof(SH2));
if( dst && dst != (void *)sh2p )
memcpy(dst, sh2p, sizeof(SH2));
return sizeof(SH2);
}
/* Set registers */
void sh2_set_context(void *src)
{
/* the core passes a CPU's own buffer: it becomes the live state */
if( src )
memcpy(&sh2, src, sizeof(SH2));
sh2p = (SH2 *)src;
}
static void sh2_timer_resync(void)
@@ -2597,6 +2651,7 @@ static void sh2_dmac_check(int dma)
if(incd == 2)
dst --;
cpu_writemem32bedw(dst, DMA_READ(src, dst, cpu_readmem32bedw(src), 0));
SH2JIT_STORE(dst, 1);
if(incs == 1)
src ++;
if(incd == 1)
@@ -2613,6 +2668,7 @@ static void sh2_dmac_check(int dma)
if(incd == 2)
dst -= 2;
cpu_writemem32bedw_word(dst, DMA_READ(src, dst, cpu_readmem32bedw_word(src), 1));
SH2JIT_STORE(dst, 2);
if(incs == 1)
src += 2;
if(incd == 1)
@@ -2629,6 +2685,7 @@ static void sh2_dmac_check(int dma)
if(incd == 2)
dst -= 4;
cpu_writemem32bedw_dword(dst, DMA_READ(src, dst, cpu_readmem32bedw_dword(src), 2));
SH2JIT_STORE(dst, 4);
if(incs == 1)
src += 4;
if(incd == 1)
@@ -2647,6 +2704,7 @@ static void sh2_dmac_check(int dma)
cpu_writemem32bedw_dword(dst+4, DMA_READ(src+4, dst+4, cpu_readmem32bedw_dword(src+4), 2));
cpu_writemem32bedw_dword(dst+8, DMA_READ(src+8, dst+8, cpu_readmem32bedw_dword(src+8), 2));
cpu_writemem32bedw_dword(dst+12, DMA_READ(src+12, dst+12, cpu_readmem32bedw_dword(src+12), 2));
SH2JIT_STORE(dst, 16);
src += 16;
if(incd == 1)
dst += 16;
@@ -2666,6 +2724,46 @@ static void sh2_dmac_check(int dma)
}
}
/* the division unit, as in current MAME (sh7604.cpp) */
static void sh2_divu_start(INT64 dividend)
{
INT32 divisor = (INT32)sh2.m[0x40];
INT64 remainder;
UINT32 quotient;
int i, negative;
sh2.m[0x41] = (UINT32)dividend;
if (divisor && (dividend != (INT64)((UINT64)1 << 63) || divisor != -1))
{
INT64 q = dividend / divisor;
if (q == (INT32)q)
{
sh2.m[0x45] = (UINT32)q;
sh2.m[0x44] = (UINT32)(dividend % divisor);
return;
}
}
/* overflow (zero divisor or a quotient outside 32 bits): the unit stops after three
steps, leaving the partial remainder in DVDNTH; with OVFIE clear DVDNTL saturates */
remainder = dividend >> 32;
quotient = (UINT32)dividend;
for (i = 0; i < 3; i++)
{
int subtract = (remainder < 0) == (divisor < 0);
remainder = (remainder << 1) | ((quotient >> 31) & 1);
quotient <<= 1;
remainder += subtract ? -(INT64)divisor : (INT64)divisor;
quotient |= ((remainder < 0) == (divisor < 0)) ? 1 : 0;
}
negative = (dividend < 0) != (divisor < 0);
sh2.m[0x44] = (UINT32)remainder;
sh2.m[0x45] = (sh2.m[0x42] & 2) ? quotient : negative ? 0x80000000 : 0x7fffffff;
sh2.m[0x42] |= 1;
sh2_recalc_irq();
}
WRITE32_HANDLER( sh2_internal_w )
{
UINT32 old = sh2.m[offset];
@@ -2728,64 +2826,19 @@ WRITE32_HANDLER( sh2_internal_w )
/* Division box*/
case 0x40: /* DVSR*/
break;
case 0x41: /* DVDNT*/
{
INT32 a = sh2.m[0x41];
INT32 b = sh2.m[0x40];
log_cb(RETRO_LOG_DEBUG, LOGPRE "SH2 #%d div+mod %d/%d\n", cpu_getactivecpu(), a, b);
if (b)
{
sh2.m[0x45] = a / b;
sh2.m[0x44] = a % b;
}
else
{
sh2.m[0x42] |= 0x00010000;
sh2.m[0x45] = 0x7fffffff;
sh2.m[0x44] = 0x7fffffff;
sh2_recalc_irq();
}
break;
}
case 0x42: /* DVCR*/
sh2.m[0x42] = (sh2.m[0x42] & ~0x00001000) | (old & sh2.m[0x42] & 0x00010000);
sh2_recalc_irq();
case 0x41: /* DVDNT: a 32-bit division, the dividend sign-extended into DVDNTH */
sh2_divu_start((INT32)sh2.m[0x41]);
break;
case 0x42: /* DVCR: OVF (bit 0) and OVFIE (bit 1) are plain read/write bits */
break;
case 0x43: /* VCRDIV*/
sh2_recalc_irq();
break;
case 0x44: /* DVDNTH*/
break;
case 0x45: /* DVDNTL*/
{
INT64 a = sh2.m[0x45] | ((UINT64)(sh2.m[0x44]) << 32);
INT64 b = sh2.m[0x40];
log_cb(RETRO_LOG_DEBUG, LOGPRE "SH2 #%d div+mod %08x%08x/%08x\n", cpu_getactivecpu(), sh2.m[0x44], sh2.m[0x45], sh2.m[0x40]);
if (b)
{
INT64 q = a / b;
if (q != (INT32)q)
{
sh2.m[0x42] |= 0x00010000;
sh2.m[0x45] = 0x7fffffff;
sh2.m[0x44] = 0x7fffffff;
sh2_recalc_irq();
}
else
{
sh2.m[0x45] = q;
sh2.m[0x44] = a % b;
}
}
else
{
sh2.m[0x42] |= 0x00010000;
sh2.m[0x45] = 0x7fffffff;
sh2.m[0x44] = 0x7fffffff;
sh2_recalc_irq();
}
break;
}
case 0x45: /* DVDNTL: a 64-bit division of DVDNTH:DVDNTL */
sh2_divu_start((INT64)(((UINT64)sh2.m[0x44] << 32) | sh2.m[0x45]));
break;
/* DMA controller*/
case 0x60: /* SAR0*/
@@ -2840,7 +2893,11 @@ READ32_HANDLER( sh2_internal_r )
switch( offset )
{
case 0x04: /* TIER, FTCSR, FRC*/
sh2_timer_resync();
/* only a read of FRC brings it up to date, as in current MAME (frc_r):
reading TIER or FTCSR does not (a slave CPU waiting for its input
capture flag reads FTCSR tens of thousands of times a frame) */
if ((mem_mask & 0xffff) != 0xffff)
sh2_timer_resync();
return (sh2.m[4] & 0xffff0000) | sh2.frc;
case 0x05: /* OCRx, TCR, TOCR*/
if(sh2.m[5] & 0x10)
@@ -3096,6 +3153,12 @@ void sh2_init(void)
{
int cpu = cpu_getactivecpu();
/* this CPU's buffer from now on (the core allocated it before the init) */
sh2p = (SH2 *)cpunum_get_context_buffer(cpu);
if (!sh2p)
sh2p = &sh2_boot;
memset(sh2p, 0, sizeof(SH2));
sh2.timer = timer_alloc(sh2_timer_callback);
timer_adjust(sh2.timer, TIME_NEVER, 0, 0);
@@ -3136,5 +3199,29 @@ void sh2_init(void)
state_save_register_UINT32("sh2", cpu, "R13", &sh2.r[13], 1);
state_save_register_UINT32("sh2", cpu, "R14", &sh2.r[14], 1);
state_save_register_UINT32("sh2", cpu, "EA", &sh2.ea, 1);
/* the rest of the CPU: the delay slot, the divider, the interrupts and
the on-chip modules (their registers, the free running timer, the DMA) */
state_save_register_UINT32("sh2", cpu, "PPC", &sh2.ppc, 1);
state_save_register_UINT32("sh2", cpu, "delay", &sh2.delay, 1);
state_save_register_UINT32("sh2", cpu, "cpu_off", &sh2.cpu_off, 1);
state_save_register_UINT32("sh2", cpu, "dvsr", &sh2.dvsr, 1);
state_save_register_UINT32("sh2", cpu, "dvdnth", &sh2.dvdnth, 1);
state_save_register_UINT32("sh2", cpu, "dvdntl", &sh2.dvdntl, 1);
state_save_register_UINT32("sh2", cpu, "dvcr", &sh2.dvcr, 1);
state_save_register_UINT32("sh2", cpu, "pending_irq", &sh2.pending_irq, 1);
state_save_register_UINT32("sh2", cpu, "test_irq", &sh2.test_irq, 1);
state_save_register_INT32("sh2", cpu, "irq_queue", (INT32 *)sh2.irq_queue, 16 * 2);
state_save_register_INT8("sh2", cpu, "irq_line_state", sh2.irq_line_state, 16);
state_save_register_INT8("sh2", cpu, "nmi_line_state", &sh2.nmi_line_state, 1);
state_save_register_UINT32("sh2", cpu, "m", sh2.m, 0x200 / 4);
state_save_register_UINT16("sh2", cpu, "frc", &sh2.frc, 1);
state_save_register_UINT16("sh2", cpu, "ocra", &sh2.ocra, 1);
state_save_register_UINT16("sh2", cpu, "ocrb", &sh2.ocrb, 1);
state_save_register_UINT16("sh2", cpu, "icr", &sh2.icr, 1);
state_save_register_UINT32("sh2", cpu, "frc_base", &sh2.frc_base, 1);
state_save_register_int("sh2", cpu, "frt_input", &sh2.frt_input);
state_save_register_int("sh2", cpu, "internal_irq_level", &sh2.internal_irq_level);
state_save_register_int("sh2", cpu, "internal_irq_vector", &sh2.internal_irq_vector);
state_save_register_INT32("sh2", cpu, "dma_timer_active", (INT32 *)sh2.dma_timer_active, 2);
return;
}
src/cpu/sh2/sh2.h
+11
View File
@@ -69,6 +69,17 @@ struct sh2_config
data32_t (*dma_read_hook)(UINT32 src, UINT32 dst, data32_t data, int size);
};
/* optional recompiler (sh2jit.c): a driver declares the RAM the CPUs run
from and read directly ('base': host memory of 'start', as the memory
system keeps it), then enables it; anything else stays with the
interpreter. Writes the driver makes there by other means than the
CPUs (DMA) must be reported with sh2_jit_ram_written. */
int sh2_jit_available(void);
void sh2_jit_add_fastram(offs_t start, offs_t end, int readonly, void *base);
void sh2_jit_set(int enable);
void sh2_jit_ram_written(UINT32 address, UINT32 bytes);
extern int sh2_jit_code_present;
extern void sh2_init(void);
extern void sh2_reset (void *param); /* Reset registers to the initial values */
extern void sh2_exit (void); /* Shut down CPU core */
src/cpu/sh2/sh2jit.c
+2229
View File
File diff suppressed because it is too large. Load diff
src/cpu/sh3/sh3.c
+3212
View File
File diff suppressed because it is too large. Load diff
src/cpu/sh3/sh3.h
+87
View File
@@ -0,0 +1,87 @@
/*****************************************************************************
sh3.h
Hitachi SH-3 (SH7709S) CPU core, from current MAME (sh.cpp, sh4.cpp,
sh3comn.cpp, sh4comn.cpp, sh4tmu.cpp, sh7709s.cpp: R. Belmont,
David Haywood, Jesus Ramos and the other authors of those files).
Big endian, 32-bit data bus (32bedw). No FPU and no MMU (current MAME
doesn't emulate the SH-3 MMU either). The internal registers of the
SH7709S are emulated in the core; the I/O ports call the driver.
*****************************************************************************/
#ifndef _SH3_H
#define _SH3_H
#include "cpuintrf.h"
#include "osd_cpu.h"
/* the external interrupt lines IRL0-IRL3 (current MAME: SH4_IRL0-SH4_IRL3) */
#define SH3_IRL0 0
#define SH3_IRL1 1
#define SH3_IRL2 2
#define SH3_IRL3 3
/* the I/O ports, for the port callbacks */
enum
{
SH3_PORT_A = 0, SH3_PORT_B, SH3_PORT_C, SH3_PORT_D, SH3_PORT_E, SH3_PORT_F,
SH3_PORT_G, SH3_PORT_H, SH3_PORT_J, SH3_PORT_K, SH3_PORT_L, SH3_PORT_COUNT
};
enum
{
SH3_PC=1, SH3_SR, SH3_PR, SH3_GBR, SH3_VBR, SH3_MACH, SH3_MACL,
SH3_R0, SH3_R1, SH3_R2, SH3_R3, SH3_R4, SH3_R5, SH3_R6, SH3_R7,
SH3_R8, SH3_R9, SH3_R10, SH3_R11, SH3_R12, SH3_R13, SH3_R14, SH3_R15,
SH3_SSR, SH3_SPC, SH3_EA
};
struct sh3_config
{
/* the SH7709S cache and bus timing of current MAME (sh7709s.cpp, made
for the CV1000): data accesses and cache misses cost cycles */
int cache_timing;
/* the clock of the peripheral modules (TMU), Hz */
int pm_clock;
/* the I/O ports (SH3_PORT_x); NULL reads 0 */
data8_t (*port_r)(int port);
void (*port_w)(int port, data8_t data);
};
extern int sh3_ICount;
/* the fast memory: plain RAM or ROM at base (an array of data32_t, as the
memory system keeps a 32-bit big-endian space), read, written and fetched
without the memory handlers; physical addresses (29 bits). Set from
DRIVER_INIT, emptied at the CPU init */
#define SH3_FASTRAM_MAX 4
void sh3_set_fastram(UINT32 start, UINT32 end, int readonly, data32_t *base);
/* the cache and bus timing of an access done by a memory handler (current
MAME: sh7709s_device::update_access_cycles) */
void sh3_update_access_cycles(UINT32 address, int write);
/* the recompiler (sh3jit.c): available on this host, and on/off (off by default) */
int sh3_jit_available(void);
void sh3_set_jit(int enable);
/* the total number of cycles run */
UINT32 sh3_total_cycles_lo(void);
void sh3_init(void);
void sh3_reset(void *param);
void sh3_exit(void);
int sh3_execute(int cycles);
unsigned sh3_get_context(void *dst);
void sh3_set_context(void *src);
unsigned sh3_get_reg(int regnum);
void sh3_set_reg(int regnum, unsigned val);
void sh3_set_irq_line(int irqline, int state);
void sh3_set_irq_callback(int (*callback)(int irqline));
const char *sh3_info(void *context, int regnum);
unsigned sh3_dasm(char *buffer, unsigned pc);
#endif
src/cpu/sh3/sh3jit.c
+1329
View File
File diff suppressed because it is too large. Load diff
src/cpu/sharc/sharc.c
+2 -1
View File
@@ -1188,7 +1188,8 @@ int sharc_execute(int cycles)
}
}
if (!m_core->write_stalled)
/* port: no call when channels 6 and 7 are idle (most instructions) */
if (!m_core->write_stalled && (m_core->dma_status & ((1 << 6) | (1 << 7))))
{
dma_stalled = dma_run_cycle(6);
dma_stalled |= dma_run_cycle(7);
src/cpu/z80/z80.c
+8
View File
@@ -3487,6 +3487,7 @@ if( _BC > 1 && _PCD < 0xfffc ) { \
if( op3==0x20 && op4==0xfb ) \
{ \
int cnt = \
cc[Z80_TABLE_op][0x0b] + \
cc[Z80_TABLE_op][0x78] + \
cc[Z80_TABLE_op][0xb1] + \
cc[Z80_TABLE_op][0x20] + \
@@ -3505,6 +3506,7 @@ if( _BC > 1 && _PCD < 0xfffc ) { \
if( (ad1 + 256 * ad2) == (_PCD - 1) ) \
{ \
int cnt = \
cc[Z80_TABLE_op][0x0b] + \
cc[Z80_TABLE_op][0x78] + \
cc[Z80_TABLE_op][0xb1] + \
cc[Z80_TABLE_op][0xc2] + \
@@ -3530,6 +3532,7 @@ if( _DE > 1 && _PCD < 0xfffc ) { \
if( op3==0x20 && op4==0xfb ) \
{ \
int cnt = \
cc[Z80_TABLE_op][0x1b] + \
cc[Z80_TABLE_op][0x7a] + \
cc[Z80_TABLE_op][0xb3] + \
cc[Z80_TABLE_op][0x20] + \
@@ -3548,6 +3551,7 @@ if( _DE > 1 && _PCD < 0xfffc ) { \
if( (ad1 + 256 * ad2) == (_PCD - 1) ) \
{ \
int cnt = \
cc[Z80_TABLE_op][0x1b] + \
cc[Z80_TABLE_op][0x7a] + \
cc[Z80_TABLE_op][0xb3] + \
cc[Z80_TABLE_op][0xc2] + \
@@ -3573,6 +3577,7 @@ if( _HL > 1 && _PCD < 0xfffc ) { \
if( op3==0x20 && op4==0xfb ) \
{ \
int cnt = \
cc[Z80_TABLE_op][0x2b] + \
cc[Z80_TABLE_op][0x7c] + \
cc[Z80_TABLE_op][0xb5] + \
cc[Z80_TABLE_op][0x20] + \
@@ -3591,6 +3596,7 @@ if( _HL > 1 && _PCD < 0xfffc ) { \
if( (ad1 + 256 * ad2) == (_PCD - 1) ) \
{ \
int cnt = \
cc[Z80_TABLE_op][0x2b] + \
cc[Z80_TABLE_op][0x7c] + \
cc[Z80_TABLE_op][0xb5] + \
cc[Z80_TABLE_op][0xc2] + \
@@ -4117,6 +4123,8 @@ void z80_init(void)
state_save_register_UINT8("z80", cpu, "int_state", Z80.int_state, 4);
state_save_register_UINT8("z80", cpu, "nmi_state", &Z80.nmi_state, 1);
state_save_register_UINT8("z80", cpu, "irq_state", &Z80.irq_state, 1);
/* the cycles of an interrupt taken outside of z80_execute, counted at the next one */
state_save_register_INT32("z80", cpu, "extra_cycles", (INT32 *)&Z80.extra_cycles, 1);
/* daisy chain needs to be saved by z80ctc.c somehow */
}
src/cpuexec.c
+121 -19
View File
@@ -142,7 +142,8 @@ struct cpuinfo
UINT64 totalcycles; /* total CPU cycles executed */
double localtime; /* local time, relative to the timer system's global time */
double clockscale; /* current active clock scale factor */
double clockscale; /* current active clock scale factor, set by drivers and CPU cores */
double overclock; /* user overclock factor (core options), applied on top of clockscale */
int vblankint_countdown; /* number of vblank callbacks left until we interrupt */
int vblankint_multiplier; /* number of vblank callbacks per interrupt */
@@ -180,10 +181,40 @@ static INT32 saved_suspend[MAX_CPU];
static double saved_localtime[MAX_CPU];
static UINT32 saved_cycles[MAX_CPU * 2];
/* With the timer system in the save state (timer_state_loaded()), the
rest of the scheduling is loaded exactly too: all the suspend reasons
and the triggers they wait for, the interrupts left in the frame, the
VBLANK countdowns and the frame number. The timers they depend on (spin,
trigger time, VBLANK) are then the ones of the save. */
#define EXACT_PER_CPU 7
static INT32 saved_exact[MAX_CPU * EXACT_PER_CPU];
static INT32 saved_exact_globals[3];
/* the triggers of cpu_spinuntil_time() and cpu_yielduntil_time(): numbered in
turn, the number is in the state (the CPU waits on it, a timer pulls it) */
static INT32 spin_timetrig, yield_timetrig;
static int vblank;
static int current_frame;
static int vblank_countdown;
static void cpu_suspend_presave(void)
{
int cpunum;
for (cpunum = 0; cpunum < cpu_gettotalcpu(); cpunum++)
{
INT32 *e = &saved_exact[cpunum * EXACT_PER_CPU];
e[0] = cpu[cpunum].suspend;
e[1] = cpu[cpunum].nextsuspend;
e[2] = cpu[cpunum].eatcycles;
e[3] = cpu[cpunum].nexteatcycles;
e[4] = cpu[cpunum].trigger;
e[5] = cpu[cpunum].iloops;
e[6] = cpu[cpunum].vblankint_countdown;
}
saved_exact_globals[0] = vblank;
saved_exact_globals[1] = current_frame;
saved_exact_globals[2] = vblank_countdown;
for (cpunum = 0; cpunum < cpu_gettotalcpu(); cpunum++)
{
saved_suspend[cpunum] = cpu[cpunum].nextsuspend & SUSPEND_LASTING_REASONS;
@@ -204,14 +235,31 @@ static void cpu_suspend_postload(void)
cpu[cpunum].eatcycles = cpu[cpunum].nexteatcycles = 1;
cpu[cpunum].localtime = saved_localtime[cpunum];
cpu[cpunum].totalcycles = ((UINT64)saved_cycles[cpunum * 2 + 1] << 32) | saved_cycles[cpunum * 2];
if (timer_state_loaded())
{
INT32 *e = &saved_exact[cpunum * EXACT_PER_CPU];
cpu[cpunum].suspend = e[0];
cpu[cpunum].nextsuspend = e[1];
cpu[cpunum].eatcycles = e[2];
cpu[cpunum].nexteatcycles = e[3];
cpu[cpunum].trigger = e[4];
cpu[cpunum].iloops = e[5];
cpu[cpunum].vblankint_countdown = e[6];
}
}
if (timer_state_loaded())
{
vblank = saved_exact_globals[0];
current_frame = saved_exact_globals[1];
vblank_countdown = saved_exact_globals[2];
}
}
static int time_to_reset;
static int time_to_quit;
static int vblank;
static int current_frame;
static INT32 watchdog_counter;
static int cycles_running;
@@ -226,7 +274,6 @@ static int cycles_stolen;
*************************************/
static void *vblank_timer;
static int vblank_countdown;
static int vblank_multiplier;
static double vblank_period;
@@ -297,9 +344,10 @@ int cpu_init(void)
memset(&cpu[cpunum], 0, sizeof(cpu[cpunum]));
cpu[cpunum].suspend = SUSPEND_REASON_RESET;
cpu[cpunum].clockscale = cputype_get_interface(cputype)->overclock;
cpu[cpunum].overclock = 1.0;
/* compute the cycle times */
sec_to_cycles[cpunum] = cpu[cpunum].clockscale * Machine->drv->cpu[cpunum].cpu_clock;
sec_to_cycles[cpunum] = cpu[cpunum].clockscale * cpu[cpunum].overclock * Machine->drv->cpu[cpunum].cpu_clock;
cycles_to_sec[cpunum] = 1.0 / sec_to_cycles[cpunum];
/* initialize this CPU */
@@ -316,6 +364,11 @@ int cpu_init(void)
state_save_register_INT32("cpu", 0, "suspend", saved_suspend, cpu_gettotalcpu());
state_save_register_double("cpu", 0, "localtime", saved_localtime, cpu_gettotalcpu());
state_save_register_UINT32("cpu", 0, "totalcycles", saved_cycles, cpu_gettotalcpu() * 2);
state_save_register_INT32("cpu", 0, "exact", saved_exact, cpu_gettotalcpu() * EXACT_PER_CPU);
state_save_register_INT32("cpu", 0, "exact globals", saved_exact_globals, 3);
spin_timetrig = yield_timetrig = 0;
state_save_register_INT32("cpu", 0, "spin timetrig", &spin_timetrig, 1);
state_save_register_INT32("cpu", 0, "yield timetrig", &yield_timetrig, 1);
state_save_register_func_presave(cpu_suspend_presave);
state_save_register_func_postload(cpu_suspend_postload);
@@ -323,6 +376,10 @@ int cpu_init(void)
if (cpuint_init())
return 1;
/* the timer system, in the save states: registered after the CPU and
interrupt state, so its postload runs before theirs */
timer_save_init();
return 0;
}
@@ -885,6 +942,24 @@ double cpunum_get_clockscale(int cpunum)
/*************************************
*
* Recomputes a CPU's cycle times from
* its clock, clock scale and overclock
*
*************************************/
static void update_cycle_rate(int cpunum)
{
sec_to_cycles[cpunum] = cpu[cpunum].clockscale * cpu[cpunum].overclock * Machine->drv->cpu[cpunum].cpu_clock;
cycles_to_sec[cpunum] = 1.0 / sec_to_cycles[cpunum];
/* re-compute the perfect interleave factor */
compute_perfect_interleave();
}
/*************************************
*
* Sets the current scaling factor
@@ -897,11 +972,42 @@ void cpunum_set_clockscale(int cpunum, double clockscale)
VERIFY_CPUNUM_VOID(cpunum_set_clockscale);
cpu[cpunum].clockscale = clockscale;
sec_to_cycles[cpunum] = cpu[cpunum].clockscale * Machine->drv->cpu[cpunum].cpu_clock;
cycles_to_sec[cpunum] = 1.0 / sec_to_cycles[cpunum];
update_cycle_rate(cpunum);
}
/* re-compute the perfect interleave factor */
compute_perfect_interleave();
/*************************************
*
* Returns the user overclock factor
* for a CPU's clock speed
*
*************************************/
double cpunum_get_overclock(int cpunum)
{
VERIFY_CPUNUM(1.0, cpunum_get_overclock);
return cpu[cpunum].overclock;
}
/*************************************
*
* Sets the user overclock factor for
* a CPU's clock speed. It multiplies
* the clock scale, so a clock scale
* that a driver or CPU core sets is
* kept
*
*************************************/
void cpunum_set_overclock(int cpunum, double overclock)
{
VERIFY_CPUNUM_VOID(cpunum_set_overclock);
cpu[cpunum].overclock = overclock;
update_cycle_rate(cpunum);
}
@@ -1370,21 +1476,17 @@ void cpu_yield(void)
void cpu_spinuntil_time(double duration)
{
static int timetrig = 0;
cpu_spinuntil_trigger(TRIGGER_SUSPENDTIME + timetrig);
cpu_triggertime(duration, TRIGGER_SUSPENDTIME + timetrig);
timetrig = (timetrig + 1) & 255;
cpu_spinuntil_trigger(TRIGGER_SUSPENDTIME + spin_timetrig);
cpu_triggertime(duration, TRIGGER_SUSPENDTIME + spin_timetrig);
spin_timetrig = (spin_timetrig + 1) & 255;
}
void cpu_yielduntil_time(double duration)
{
static int timetrig = 0;
cpu_yielduntil_trigger(TRIGGER_YIELDTIME + timetrig);
cpu_triggertime(duration, TRIGGER_YIELDTIME + timetrig);
timetrig = (timetrig + 1) & 255;
cpu_yielduntil_trigger(TRIGGER_YIELDTIME + yield_timetrig);
cpu_triggertime(duration, TRIGGER_YIELDTIME + yield_timetrig);
yield_timetrig = (yield_timetrig + 1) & 255;
}
src/cpuexec.h
+8 -2
View File
@@ -179,6 +179,12 @@ double cpunum_get_clockscale(int cpunum);
/* Sets the current scaling factor for a CPU's clock speed */
void cpunum_set_clockscale(int cpunum, double clockscale);
/* Returns the user overclock factor for a CPU's clock speed */
double cpunum_get_overclock(int cpunum);
/* Sets the user overclock factor, which multiplies the clock scale */
void cpunum_set_overclock(int cpunum, double overclock);
/* Temporarily boosts the interleave factor */
void cpu_boost_interleave(double timeslice_time, double boost_duration);
@@ -186,8 +192,8 @@ void cpu_boost_interleave(double timeslice_time, double boost_duration);
#define timer_suspendcpu(cpunum, suspend, reason) do { if (suspend) cpunum_suspend(cpunum, reason, 1); else cpunum_resume(cpunum, reason); } while (0)
#define timer_holdcpu(cpunum, suspend, reason) do { if (suspend) cpunum_suspend(cpunum, reason, 0); else cpunum_resume(cpunum, reason); } while (0)
#define cpu_getstatus(cpunum) (!cpunum_is_suspended(cpunum, SUSPEND_REASON_HALT | SUSPEND_REASON_RESET | SUSPEND_REASON_DISABLE))
#define timer_get_overclock(cpunum) cpunum_get_clockscale(cpunum)
#define timer_set_overclock(cpunum, overclock) cpunum_set_clockscale(cpunum, overclock)
#define timer_get_overclock(cpunum) cpunum_get_overclock(cpunum)
#define timer_set_overclock(cpunum, overclock) cpunum_set_overclock(cpunum, overclock)
src/cpuint.c
+3 -1
View File
@@ -77,7 +77,9 @@ static void cpuint_postload(void)
{
if (irq_event_index[cpunum] > MAX_IRQ_EVENTS)
irq_event_index[cpunum] = MAX_IRQ_EVENTS;
if (irq_event_index[cpunum] > 0)
/* the timer that empties the queue is in the state, when the
timers are */
if (irq_event_index[cpunum] > 0 && !timer_state_loaded())
timer_set(TIME_NOW, cpunum, cpu_empty_event_queue);
}
}
src/cpuintrf.c
+34
View File
@@ -67,6 +67,9 @@
#if (HAS_V20 || HAS_V30 || HAS_V33)
#include "cpu/nec/necintrf.h"
#endif
#if (HAS_V25)
#include "cpu/nec/v25.h"
#endif
#if (HAS_V60 || HAS_V70)
#include "cpu/v60/v60.h"
#endif
@@ -121,6 +124,9 @@
#if (HAS_TMS32025)
#include "cpu/tms32025/tms32025.h"
#endif
#if (HAS_NAMCOC71)
#include "cpu/namcoc71/c71.h"
#endif
#if (HAS_I960)
#include "cpu/i960/i960.h"
#endif
@@ -151,6 +157,9 @@
#if (HAS_H83002)
#include "cpu/h83002/h83002.h"
#endif
#if (HAS_I386)
#include "cpu/i386/i386.h"
#endif
#if (HAS_M37702)
#include "cpu/m37710/m37710.h"
#endif
@@ -178,6 +187,9 @@
#if (HAS_SH2)
#include "cpu/sh2/sh2.h"
#endif
#if (HAS_SH3)
#include "cpu/sh3/sh3.h"
#endif
#if (HAS_DSP32C)
#include "cpu/dsp32/dsp32.h"
#endif
@@ -432,6 +444,9 @@ const struct cpu_interface cpuintrf[] =
#if (HAS_V30)
CPU0(V30, v30, 1,255,1.00, 8, 20, 0,20,LE,1, 5 ),
#endif
#if (HAS_V25)
CPU0(V25, v25, 1,255,1.00, 8, 20, 0,20,LE,1, 5 ),
#endif
#if (HAS_V33)
CPU0(V33, v33, 1,255,1.00, 8, 20, 0,20,LE,1, 5 ),
#endif
@@ -561,6 +576,10 @@ const struct cpu_interface cpuintrf[] =
#if (HAS_TMS32025)
CPU3(TMS32025,tms32025, 3, 0,1.00,16,18bew, -1,18,BE,2, 4 ),
#endif
#if (HAS_NAMCOC71)
#define c71_ICount c71_icount
CPU0(NAMCOC71, c71, 6, 0,1.00,16,16bew, -1,16,BE,2, 4 ),
#endif
#if (HAS_TMS32031)
#define tms32031_ICount tms32031_icount
CPU0(TMS32031,tms32031, 4, 0,1.00,32,26ledw,-2,26,LE,4, 4 ),
@@ -592,6 +611,9 @@ const struct cpu_interface cpuintrf[] =
#if (HAS_H83002)
CPU0(H83002, h8_3002, 8, 0,1.00,16,24bew, 0,24,BE,2,10 ),
#endif
#if (HAS_I386)
CPU0(I386, i386, 1, 0,1.00,32,32ledw, 0,32,LE,1,15 ),
#endif
#if (HAS_MN10200)
CPU0(MN10200, mn10200, 4, 0,1.00,16,24lew, 0,24,LE,1, 6 ),
#endif
@@ -645,6 +667,9 @@ const struct cpu_interface cpuintrf[] =
#if (HAS_SH2)
CPU4(SH2, sh2, 16, 0,1.00,32,32bedw, 0,32,BE,2, 2 ),
#endif
#if (HAS_SH3)
CPU0(SH3, sh3, 4, 0,1.00,32,32bedw, 0,32,BE,2, 2 ),
#endif
#if (HAS_DSP32C)
#define dsp32c_ICount dsp32_icount
CPU0(DSP32C, dsp32c, 4, 0,1.00,32,24ledw, 0,24,LE,4, 4 ),
@@ -1268,6 +1293,15 @@ void *cpunum_get_context_ptr(int cpunum)
return (cpu_active_context[cpu[cpunum].family] == cpunum) ? NULL : cpu[cpunum].context;
}
/* the context buffer of a CPU, also from its init function (when the CPU
does not count in totalcpu yet), whether it is active or not */
void *cpunum_get_context_buffer(int cpunum)
{
if (cpunum < 0 || cpunum >= MAX_CPU)
return NULL;
return cpu[cpunum].context;
}
/*--------------------------
Get/set cycle table
src/cpuintrf.h
+13
View File
@@ -103,6 +103,9 @@ enum
#if (HAS_V30)
CPU_V30,
#endif
#if (HAS_V25)
CPU_V25,
#endif
#if (HAS_V33)
CPU_V33,
#endif
@@ -232,6 +235,9 @@ enum
#if (HAS_TMS32025)
CPU_TMS32025,
#endif
#if (HAS_NAMCOC71)
CPU_NAMCOC71,
#endif
#if (HAS_TMS32031)
CPU_TMS32031,
#endif
@@ -262,6 +268,9 @@ enum
#if (HAS_H83002)
CPU_H83002,
#endif
#if (HAS_I386)
CPU_I386,
#endif
#if (HAS_MN10200)
CPU_MN10200,
#endif
@@ -302,6 +311,9 @@ enum
#if (HAS_SH2)
CPU_SH2,
#endif
#if (HAS_SH3)
CPU_SH3,
#endif
#if (HAS_DSP32C)
CPU_DSP32C,
#endif
@@ -627,6 +639,7 @@ void cpunum_write_bytes(int cpunum, offs_t address, const UINT8 *data, UINT32 co
/* return a pointer to the saved context of a given CPU, or NULL if the
context is active (and contained within the CPU core */
void *cpunum_get_context_ptr(int cpunum);
void *cpunum_get_context_buffer(int cpunum);
/* return a pointer to the active cycle count table for a given CPU */
const void *cpunum_get_cycle_table(int cpunum, int which);
src/drawgfx.c
+11 -1
View File
@@ -1,6 +1,7 @@
#ifndef DECLARE
#include "driver.h"
#include "state.h"
#ifdef MSB_FIRST
@@ -3516,11 +3517,20 @@ static INLINE void plotclip(struct mame_bitmap *bitmap,int x,int y,int pen,const
plot_pixel(bitmap,x,y,pen);
}
/* where each crosshair was and since which frame: in the save states, so a
crosshair hides at the same frame after a load or a run-ahead rewind */
static INT32 inactive_xy [MAX_PLAYER_COUNT][3];
void crosshair_state_save_register(void)
{
memset(inactive_xy, 0, sizeof(inactive_xy));
state_save_register_INT32("crosshair", 0, "inactive", &inactive_xy[0][0], MAX_PLAYER_COUNT * 3);
}
void draw_crosshair(int player_number, struct mame_bitmap *bitmap,int x,int y,const struct rectangle *clip)
{
unsigned long color,black,white;
int i;
static int inactive_xy [MAX_PLAYER_COUNT][3];
if (!options.crosshair_enable)
{
src/drawgfx.h
+1
View File
@@ -272,6 +272,7 @@ void mdrawgfxzoom( struct mame_bitmap *dest_bmp,const struct GfxElement *gfx,
void drawgfx_toggle_crosshair(void);
void draw_crosshair(int player_number, struct mame_bitmap *bitmap,int x,int y,const struct rectangle *clip);
void crosshair_state_save_register(void);
static INLINE void sect_rect(struct rectangle *dst, const struct rectangle *src)
{
src/driver.c
+423 -80
View File
@@ -250,9 +250,13 @@ const struct GameDriver *test_drivers[] =
DRIVER( froggers ) /* bootleg */
DRIVER( amidars ) /* GX337 (c) 1982 Konami */
DRIVER( triplep ) /* (c) 1982 KKI */ /* made by Sanritsu? */
DRIVER( triplepa ) /* (c) 1982 KKI */
DRIVER( knockout ) /* (c) 1982 KKK */
DRIVER( knockoutb ) /* bootleg */
DRIVER( knockoutc ) /* bootleg (ESG) */
DRIVER( mariner ) /* (c) 1981 Amenip */
DRIVER( 800fath ) /* (c) 1981 Amenip + U.S. Billiards license */
DRIVER( 800fatha ) /* (c) 1981 Amenip + U.S. Billiards license */
DRIVER( mars ) /* (c) 1981 Artic */
DRIVER( devilfsh ) /* (c) 1982 Artic */
DRIVER( newsin7 ) /* (c) 1983 ATW USA, Inc. */
@@ -371,6 +375,8 @@ const struct GameDriver *test_drivers[] =
DRIVER( kodure ) /* (c) 1987 (Japan) */
DRIVER( armedf ) /* (c) 1988 */
DRIVER( cclimbr2 ) /* (c) 1988 (Japan) */
DRIVER( skyrobo ) /* (c) 1989 */
DRIVER( bigfghtr ) /* (c) 1989 */
/* Nichibutsu Mahjong games */
DRIVER( hyhoo ) /* (c) 1987 */
@@ -742,18 +748,49 @@ const struct GameDriver *test_drivers[] =
DRIVER( cybsled ) /* (c) 1993 */
/* Namco System 22 games */
DRIVER( namcoc74 ) /* C74 BIOS */
DRIVER( ridgerac ) /* (c) 1993 */
DRIVER( ridgeraca ) /* (c) 1993 */
DRIVER( ridgeracb ) /* (c) 1993 */
DRIVER( ridgeracc ) /* (c) 1993 */
DRIVER( ridgeracj ) /* (c) 1993 */
DRIVER( ridgera2 ) /* (c) 1994 */
DRIVER( ridgera2j ) /* (c) 1994 */
DRIVER( ridgera2ja ) /* (c) 1994 */
DRIVER( ridgera28 ) /* (c) 1994 */
DRIVER( cybrcomm ) /* (c) 1994 */
DRIVER( raverace ) /* (c) 1995 */
DRIVER( raveracej ) /* (c) 1995 */
DRIVER( raveraceja ) /* (c) 1995 */
DRIVER( acedrive ) /* (c) 1994 */
DRIVER( victlap ) /* (c) 1996 */
DRIVER( victlapa ) /* (c) 1996 */
DRIVER( victlapj ) /* (c) 1996 */
/* Namco Super System 22 games */
DRIVER( alpinerd ) /* (c) 1994 */
DRIVER( alpinerc ) /* (c) 1994 */
DRIVER( raveracw ) /* (c) 1995 */
DRIVER( ridgeraj )
DRIVER( ridger2j )
DRIVER( acedrvrw )
DRIVER( victlapw )
DRIVER( cybrcomm )
DRIVER( airco22b )
DRIVER( cybrcycc )
DRIVER( timecrsa )
DRIVER( alpinerjc ) /* (c) 1994 */
DRIVER( airco22b ) /* (c) 1995 */
DRIVER( cybrcycc ) /* (c) 1995 */
DRIVER( cybrcyccj ) /* (c) 1995 */
DRIVER( dirtdash ) /* (c) 1995 */
DRIVER( dirtdasha ) /* (c) 1995 */
DRIVER( dirtdashb ) /* (c) 1995 */
DRIVER( dirtdashj ) /* (c) 1995 */
DRIVER( timecris ) /* (c) 1996 */
DRIVER( timecrisa ) /* (c) 1996 */
DRIVER( timecrisj ) /* (c) 1996 */
DRIVER( propcycl ) /* (c) 1996 */
DRIVER( propcyclj ) /* (c) 1996 */
DRIVER( alpines ) /* (c) 1996 */
DRIVER( tokyowar ) /* (c) 1996 */
DRIVER( tokyowarj ) /* (c) 1996 */
DRIVER( aquajet ) /* (c) 1996 */
DRIVER( alpinr2b ) /* (c) 1996 */
DRIVER( alpinr2a ) /* (c) 1996 */
DRIVER( adillor ) /* (c) 1997 */
DRIVER( adillorj ) /* (c) 1997 */
/* Universal games */
@@ -1872,20 +1909,41 @@ const struct GameDriver *test_drivers[] =
DRIVER( ghox ) /* TP-021 (c) 1991 Toaplan */
DRIVER( ghoxj ) /* TP-021 (c) 1991 Toaplan */
DRIVER( dogyuun ) /* TP-022 (c) 1992 Toaplan */
DRIVER( dogyuuna ) /* TP-022 (c) 1992 Toaplan */
DRIVER( dogyuunb ) /* TP-022 (c) 1992 Toaplan */
DRIVER( dogyuunt ) /* TP-022 (c) 1992 Toaplan */
DRIVER( dogyuunto ) /* TP-022 (c) 1992 Toaplan */
DRIVER( kbash ) /* TP-023 (c) 1993 Toaplan */
DRIVER( kbashk ) /* TP-023 (c) 1993 Toaplan */
DRIVER( kbashp ) /* TP-023 (c) 1993 Toaplan */
DRIVER( kbash2 ) /* TP-023 */
DRIVER( truxton2 ) /* TP-024 (c) 1992 Toaplan */
DRIVER( pipibibs ) /* TP-025 */
DRIVER( whoopee ) /* TP-025 */
DRIVER( pipibibi ) /* (c) 1991 Ryouta Kikaku (bootleg?) */
DRIVER( fixeight ) /* TP-026 (c) 1992 + Taito license */
DRIVER( fixeighb ) /* TP-026 */
DRIVER( fixeight ) /* TP-026 (c) 1992 Toaplan */
DRIVER( fixeightk ) /* TP-026 (c) 1992 Toaplan */
DRIVER( fixeighth ) /* TP-026 (c) 1992 Toaplan */
DRIVER( fixeighttw ) /* TP-026 (c) 1992 Toaplan */
DRIVER( fixeighta ) /* TP-026 (c) 1992 Toaplan */
DRIVER( fixeightu ) /* TP-026 (c) 1992 Toaplan */
DRIVER( fixeightj ) /* TP-026 (c) 1992 Toaplan */
DRIVER( fixeightt ) /* TP-026 (c) 1992 Toaplan + Taito license */
DRIVER( fixeightkt ) /* TP-026 (c) 1992 Toaplan + Taito license */
DRIVER( fixeightht ) /* TP-026 (c) 1992 Toaplan + Taito license */
DRIVER( fixeighttwt ) /* TP-026 (c) 1992 Toaplan + Taito license */
DRIVER( fixeightat ) /* TP-026 (c) 1992 Toaplan + Taito license */
DRIVER( fixeightut ) /* TP-026 (c) 1992 Toaplan + Taito license */
DRIVER( fixeightjt ) /* TP-026 (c) 1992 Toaplan + Taito license */
DRIVER( fixeightbl ) /* bootleg */
DRIVER( grindstm ) /* TP-027 (c) 1992 Toaplan */
DRIVER( grindstma ) /* TP-027 (c) 1992 Toaplan */
DRIVER( vfive ) /* TP-027 (c) 1993 Toaplan (Japan) */
DRIVER( grindstm ) /* TP-027 (c) 1993 Toaplan + Unite Trading license (Korea) */
DRIVER( grindsta ) /* TP-027 (c) 1993 Toaplan + Unite Trading license (Korea) */
DRIVER( batsugun ) /* TP-030 (c) 1993 Toaplan */
DRIVER( batugnsp ) /* TP-??? (c) 1993 Toaplan */
DRIVER( batsuguna ) /* TP-030 (c) 1993 Toaplan */
DRIVER( batsugunc ) /* TP-030 (c) 1993 Toaplan */
DRIVER( batsugunb ) /* TP-030 (c) 1993 Toaplan */
DRIVER( batsugunsp ) /* TP-030 (c) 1993 Toaplan */
DRIVER( snowbro2 ) /* TP-??? (c) 1994 Hanafram */
/* see http://www.vsa-ag.ch/r8zing/ for a list of Raizing/8ing games */
DRIVER( sstriker ) /* (c) 1993 Raizing */
@@ -1973,6 +2031,38 @@ V-V TP-027
DRIVER( gaia ) /* (c) 1999 Noise Factory */
DRIVER( theroes ) /* (c) 2001 Primetek Investmants */
/* Cave CV1000 games */
DRIVER( mushisam ) /* Mushihime-Sama (Japan, 2004/10/12.MASTER VER.) */
DRIVER( mushisama ) /* Mushihime-Sama (Japan, 2004/10/12 MASTER VER.) */
DRIVER( mushisamb ) /* Mushihime-Sama (Japan, 2004/10/12 MASTER VER) */
DRIVER( ibara ) /* Ibara (Japan, 2005/03/22 MASTER VER.., '06. 3. 7 ver.) */
DRIVER( ibarao ) /* Ibara (Japan, 2005/03/22 MASTER VER..) */
DRIVER( ibarablk ) /* Ibara Kuro Black Label (Japan, 2006/02/06. MASTER VER.) */
DRIVER( ibarablka ) /* Ibara Kuro Black Label (Japan, 2006/02/06 MASTER VER.) */
DRIVER( espgal2 ) /* Espgaluda II (Japan, 2005/11/14.MASTER VER.) */
DRIVER( espgal2a ) /* Espgaluda II (Japan, 2005/11/14 MASTER VER, newer CV1000-B PCB) */
DRIVER( espgal2b ) /* Espgaluda II (Japan, 2005/11/14 MASTER VER, original CV1000-B PCB) */
DRIVER( mushitam ) /* Puzzle! Mushihime-Tama (Japan, 2005/09/09.MASTER VER) */
DRIVER( mushitama ) /* Puzzle! Mushihime-Tama (Japan, 2005/09/09 MASTER VER) */
DRIVER( pinkswts ) /* Pink Sweets: Ibara Sorekara (Japan, 2006/04/06 MASTER VER....) */
DRIVER( pinkswtsa ) /* Pink Sweets: Ibara Sorekara (Japan, 2006/04/06 MASTER VER...) */
DRIVER( pinkswtsb ) /* Pink Sweets: Ibara Sorekara (Japan, 2006/04/06 MASTER VER.) */
DRIVER( pinkswtsx ) /* Pink Sweets: Ibara Sorekara (Japan, 2006/xx/xx MASTER VER.) */
DRIVER( pinkswtssc ) /* Pink Sweets: Suicide Club (2017/10/31 SUICIDECLUB VER., bootleg) */
DRIVER( futari15 ) /* Mushihime-Sama Futari Ver 1.5 (Japan, 2006/12/8.MASTER VER. 1.54.) */
DRIVER( futari15a ) /* Mushihime-Sama Futari Ver 1.5 (Japan, 2006/12/8 MASTER VER 1.54) */
DRIVER( futari10 ) /* Mushihime-Sama Futari Ver 1.0 (Japan, 2006/10/23 MASTER VER.) */
DRIVER( futaribl ) /* Mushihime-Sama Futari Black Label - Another Ver (World, 2009/11/27 INTERNATIONAL BL) */
DRIVER( futariblj ) /* Mushihime-Sama Futari Black Label (Japan, 2007/12/11 BLACK LABEL VER) */
DRIVER( mmpork ) /* Muchi Muchi Pork! (Japan, 2007/ 4/17 MASTER VER.) */
DRIVER( deathsml ) /* Deathsmiles (Japan, 2007/10/09 MASTER VER) */
DRIVER( dsmbl ) /* Deathsmiles MegaBlack Label (Japan, 2008/10/06 MEGABLACK LABEL VER) */
DRIVER( ddpdfk ) /* DoDonPachi Dai-Fukkatsu Ver 1.5 (Japan, 2008/06/23 MASTER VER 1.5) */
DRIVER( ddpdfk10 ) /* DoDonPachi Dai-Fukkatsu Ver 1.0 (Japan, 2008/05/16 MASTER VER) */
DRIVER( dfkbl ) /* DoDonPachi Dai-Fukkatsu Black Label (Japan, 2010/1/18 BLACK LABEL) */
DRIVER( akatana ) /* Akai Katana (2010/ 8/13 MASTER VER.) */
DRIVER( ddpsdoj ) /* DoDonPachi SaiDaiOuJou (2012/ 4/20) */
/* Kyugo games */
/* Kyugo only made four games: Repulse, Flash Gal, SRD Mission and Air Wolf. */
/* Gyrodine was made by Crux. Crux was antecedent of Toa Plan, and spin-off from Orca. */
@@ -2072,6 +2162,24 @@ V-V TP-027
DRIVER( gngmaidencenh ) /* Hack */
DRIVER( gngmaident ) /* Hack */
DRIVER( gngmaidentenh ) /* Hack */
DRIVER( gngprincess ) /* Hack */
DRIVER( gngprincessa ) /* Hack */
DRIVER( gngprincessaenh ) /* Hack */
DRIVER( gngprincessb ) /* Hack */
DRIVER( gngprincessbenh ) /* Hack */
DRIVER( gngprincessc ) /* Hack */
DRIVER( gngprincesscenh ) /* Hack */
DRIVER( gngprincessenh ) /* Hack */
DRIVER( gngprincesst ) /* Hack */
DRIVER( gngprincesstenh ) /* Hack */
DRIVER( makprincess ) /* Hack */
DRIVER( makprincessb ) /* Hack */
DRIVER( makprincessbenh ) /* Hack */
DRIVER( makprincessc ) /* Hack */
DRIVER( makprincesscenh ) /* Hack */
DRIVER( makprincessenh ) /* Hack */
DRIVER( makprincessg ) /* Hack */
DRIVER( makprincessgenh ) /* Hack */
DRIVER( gngknight ) /* Hack */
DRIVER( gngknightenh ) /* Hack */
DRIVER( gngknighta ) /* Hack */
@@ -2784,6 +2892,45 @@ V-V TP-027
DRIVER( raystormo ) /* RayStorm (Ver 2.05O) */
DRIVER( raystormu ) /* RayStorm (Ver 2.05A) */
DRIVER( raystormj ) /* RayStorm (Ver 2.05J) */
DRIVER( chaoshea ) /* Chaos Heat (V2.09O 1998/10/02 17:00) */
DRIVER( chaosheaj ) /* Chaos Heat (V2.08J 1998/09/25 17:00) */
DRIVER( raycris ) /* RayCrisis (V2.03O 1998/11/15 15:43) */
DRIVER( raycrisj ) /* RayCrisis (V2.03J 1998/11/15 15:43) */
DRIVER( spuzbobl ) /* Super Puzzle Bobble (V2.05O 1999/2/24 18:00) */
DRIVER( spuzboblj ) /* Super Puzzle Bobble (V2.04J 1999/2/17 02:10) */
DRIVER( gobyrc ) /* Go By RC (V2.03O 1999/05/25 13:31) */
DRIVER( rcdego ) /* RC De Go (V2.03J 1999/05/22 19:29) */
DRIVER( flipmaze ) /* Flip Maze (V2.04J 1999/09/02 20:00) */
DRIVER( mawasunda ) /* Mawasunda!! (V2.08J 2000/02/01 11:02:54) */
DRIVER( shikigam ) /* Shikigami no Shiro (V2.03J 2001/08/07 18:11) */
DRIVER( shikigama ) /* Shikigami no Shiro - internal build (V1.02J 2001/09/27 18:45) */
DRIVER( sianniv ) /* Space Invaders Anniversary (V2.02J 2003/09/12 20:00) */
DRIVER( kollon ) /* Kollon (V2.04JA 2003/11/01 12:00) */
DRIVER( kollonc ) /* Kollon (V2.04JC 2003/11/01 12:00) */
DRIVER( otenamih ) /* Otenami Haiken (V2.04J 1999/02/01 18:00:00) */
DRIVER( psyvaria ) /* Psyvariar -Medium Unit- (V2.02O 2000/02/22 13:00) */
DRIVER( psyvarij ) /* Psyvariar -Medium Unit- (V2.04J 2000/02/15 11:00) */
DRIVER( psyvarrv ) /* Psyvariar -Revision- (V2.04J 2000/08/11 22:00) */
DRIVER( zokuoten ) /* Zoku Otenamihaiken (V2.05J 2003/05/12 18:00) */
DRIVER( zokuotena ) /* Zoku Otenamihaiken (V2.03J 2001/02/16 16:00) */
DRIVER( zooo ) /* Zooo (V2.01JA 2004/04/13 12:00) */
DRIVER( otenamhf ) /* Otenami Haiken Final (V2.07JC 2005/04/20 15:36) */
DRIVER( mahjngoh ) /* Mahjong Oh (V2.06J 1999/11/23 08:52:22) */
DRIVER( shanghss ) /* Shanghai Shoryu Sairin (V2.03J 2000/05/26 12:45:28) */
DRIVER( soutenry ) /* Soutenryu (V2.07J 2000/12/14 11:13:02) */
DRIVER( usagi ) /* Usagi (V2.02J 2001/10/02 12:41:19) */
DRIVER( shangtou ) /* Shanghai Sangokuhai Tougi (Ver 2.01J 2002/01/18 18:26:58) */
DRIVER( nightrai ) /* Night Raid (V2.03J 2001/02/26 17:00) */
DRIVER( otenki ) /* Otenki Kororin (V2.01J 2001/07/02 10:00) */
DRIVER( xiistag ) /* XII Stag (V2.01J 2002/6/26 22:27) */
DRIVER( aerofgtsg ) /* Aero Fighters Special (VER 1.00G) */
DRIVER( brvbladeg ) /* Brave Blade (VER 1.40G) */
DRIVER( flamegung ) /* Flame Gunner (VER 1.40G) */
DRIVER( ftimpactg ) /* Fighters' Impact (VER 2.10G) */
DRIVER( gdariusg ) /* G-Darius (VER 2.70G) */
DRIVER( raystormg ) /* RayStorm (VER 2.60G) */
DRIVER( shngmtkbg ) /* Shanghai Matekibuyuu (VER 1.20G) */
DRIVER( tblkkuzug ) /* The Block Kuzushi (VER 1.10G) */
DRIVER( ftimpcta ) /* Fighters' Impact A (Ver 2.00J) */
DRIVER( ftimpact ) /* Fighters' Impact (Ver 2.02O) */
DRIVER( ftimpactu ) /* Fighters' Impact (Ver 2.02A) */
@@ -2886,7 +3033,20 @@ V-V TP-027
DRIVER( g13knd ) /* Golgo 13 Kiseki no Dandou (Japan, GLS1/VER.A) */
/* Namco System 10 */
DRIVER( mrdrilr2 ) /* Mr Driller 2 */
DRIVER( mrdrilr2 ) /* Mr. Driller 2 (World, DR22 Ver.A) */
DRIVER( mrdrilr2j ) /* Mr. Driller 2 (Japan, DR21 Ver.A) */
DRIVER( mrdrilr2u ) /* Mr. Driller 2 (US, DR23 Ver.A) */
DRIVER( gjspace ) /* GekiToride-Jong Space (10011 Ver.A) */
DRIVER( knpuzzle ) /* Kotoba no Puzzle Mojipittan (Japan, KPM1 Ver.A) */
DRIVER( mrdrilrg ) /* Mr. Driller G (Japan, DRG1 Ver.A) */
DRIVER( chocovdr ) /* Uchuu Daisakusen: Chocovader Contactee (Japan, CVC1 Ver.A) */
DRIVER( gamshara ) /* Gamshara (20020912A / 10021 Ver.A) */
DRIVER( gamsharao ) /* Gamshara (20020716A / 10021 Ver.A) */
DRIVER( panikuru ) /* Panikuru Panekuru (Japan, PPA1 Ver.A) */
DRIVER( startrgn ) /* Star Trigon (Japan, STT1 Ver.A) */
DRIVER( konotako ) /* Kono e Tako (10021 Ver.A) */
DRIVER( ptblank3 ) /* Point Blank 3 (World, GNN2 Ver.A) */
DRIVER( gunbalina ) /* Gunbalina (Japan, GNN1 Ver.A) */
/* Konami GQ */
DRIVER( cryptklr )
@@ -3192,25 +3352,19 @@ DokiDoki Penguin Land *not confirmed
DRIVER( aliensya ) /* (c) 1987 (protected) */
DRIVER( aliensyb ) /* (c) 1987 (protected) */
DRIVER( aliensyj ) /* (c) 1987 (protected. Japan) */
DRIVER( astorm ) /* (c) 1990 (protected) */
DRIVER( astorm2p ) /* (c) 1990 (protected 2 Players) */
DRIVER( aurail1 ) /* (c) 1990 Sega / Westone (protected) */
DRIVER( aurailj ) /* (c) 1990 Sega / Westone (protected) */
DRIVER( bayrouta ) /* (c) 1989 (protected) */
DRIVER( bayrtbl1 ) /* (c) 1989 (protected) (bootleg) */
DRIVER( bayrtbl2 ) /* (c) 1989 (protected) (bootleg) */
DRIVER( enduror ) /* (c) 1985 (protected) */
DRIVER( eswat ) /* (c) 1989 (protected) */
DRIVER( fpoint ) /* (c) 1989 (protected) */
DRIVER( goldnaxb ) /* (c) 1989 (protected) */
DRIVER( goldnaxc ) /* (c) 1989 (protected) */
DRIVER( goldnaxj ) /* (c) 1989 (protected. Japan) */
DRIVER( jyuohki ) /* (c) 1988 (protected. Altered Beast Japan) */
DRIVER( moonwalk ) /* (c) 1990 (protected) */
DRIVER( moonwlka ) /* (c) 1990 (protected) */
DRIVER( passsht ) /* (protected) */
DRIVER( sdioj ) /* (c) 1987 (protected. Japan) */
DRIVER( shangon ) /* (c) 1992 (protected) */
DRIVER( shinobia ) /* (c) 1987 (protected) */
DRIVER( shinobib ) /* (c) 1987 (protected) */
DRIVER( tetris ) /* (c) 1988 (protected) */
@@ -3221,11 +3375,6 @@ DokiDoki Penguin Land *not confirmed
DRIVER( hamaway )
DRIVER( aceattac ) /* (protected) */
DRIVER( afighter ) /* (protected) */
DRIVER( bloxeed ) /* (protected) */
DRIVER( cltchitr ) /* (protected) */
DRIVER( cotton ) /* (protected) */
DRIVER( cottona ) /* (protected) */
DRIVER( ddcrew ) /* (protected) */
DRIVER( dunkshot ) /* (protected) */
DRIVER( dunkshota ) /* (protected) */
DRIVER( dunkshoto ) /* (protected) */
@@ -3233,7 +3382,6 @@ DokiDoki Penguin Land *not confirmed
DRIVER( sdib ) /* (protected) */
DRIVER( sjryuko ) /* (protected) */
DRIVER( exctleag ) /* (protected) */
DRIVER( lghost ) /* (protected) */
DRIVER( loffire ) /* (protected) */
DRIVER( mvp ) /* (protected) */
DRIVER( ryukyu ) /* (protected) */
@@ -3258,13 +3406,26 @@ DokiDoki Penguin Land *not confirmed
DRIVER( aurail1d ) /* (c) 1990 Sega / Westone */
DRIVER( aurailjd ) /* (c) 1990 Sega / Westone */
DRIVER( bayroute ) /* (c) 1989 Sunsoft / Sega */
DRIVER( cottond )
DRIVER( cotton ) /* (c) 1991 (FD1094 317-0181a) */
DRIVER( cottonu ) /* (c) 1991 (FD1094 317-0180) */
DRIVER( cottonj ) /* (c) 1991 (FD1094 317-0179b) */
DRIVER( cottonja ) /* (c) 1991 (FD1094 317-0179a) */
DRIVER( cottond ) /* bootleg (decrypted cotton) */
DRIVER( cottonud ) /* bootleg (decrypted cottonu) */
DRIVER( cottonjd ) /* bootleg (decrypted cottonj) */
DRIVER( cottonjad ) /* bootleg (decrypted cottonja) */
DRIVER( bulletd )
DRIVER( bodyslam ) /* (c) 1986 */
DRIVER( dduxbl ) /* (c) 1989 (Datsu bootleg) */
DRIVER( dumpmtmt ) /* (c) 1986 (Japan) */
DRIVER( endurob2 ) /* (c) 1985 (Beta bootleg) */
DRIVER( endurobl ) /* (c) 1985 (Herb bootleg) */
DRIVER( enduror ) /* (c) 1986 (FD1089B) */
DRIVER( endurora ) /* (c) 1986 (FD1089B) */
DRIVER( endurorb ) /* (c) 1986 (FD1089B) */
DRIVER( enduror1 ) /* (c) 1986 (FD1089B) */
DRIVER( endurobl ) /* (c) 1986 (Herb bootleg) */
DRIVER( endurob2 ) /* (c) 1986 (Beta bootleg) */
DRIVER( endurord ) /* (c) 1986 (bootleg) */
DRIVER( enduror1d ) /* (c) 1986 (bootleg) */
DRIVER( eswatbl ) /* (c) 1989 (but bootleg) */
DRIVER( fantzone ) /* (c) 1986 */
DRIVER( fantzono ) /* (c) 1986 */
@@ -3276,6 +3437,52 @@ DokiDoki Penguin Land *not confirmed
DRIVER( hangon ) /* (c) 1985 */
DRIVER( hwchamp ) /* (c) 1987 */
DRIVER( mjleague ) /* (c) 1985 */
DRIVER( astorm ) /* (c) 1990 (FD1094 317-0154) */
DRIVER( astorm3 ) /* (c) 1990 (FD1094 317-0148) */
DRIVER( astormu ) /* (c) 1990 (FD1094 317-0147) */
DRIVER( astormj ) /* (c) 1990 (FD1094 317-0146) */
DRIVER( astorm3d ) /* bootleg (decrypted astorm3) */
DRIVER( astormud ) /* bootleg (decrypted astormu) */
DRIVER( astormjd ) /* bootleg (decrypted astormj) */
DRIVER( bloxeed ) /* (c) 1989 (FD1094 317-0139) */
DRIVER( bloxeeda ) /* (c) 1989 (FD1094 317-0139) */
DRIVER( bloxeedd ) /* bootleg (decrypted bloxeed) */
DRIVER( cltchitr ) /* (c) 1991 (FD1094 317-0176) */
DRIVER( cltchitrj ) /* (c) 1991 (FD1094 317-0175) */
DRIVER( cltchitrd ) /* bootleg (decrypted cltchitr) */
DRIVER( cltchitrjd ) /* bootleg (decrypted cltchitrj) */
DRIVER( wwallyj ) /* (c) 1992 (FD1094 317-0197B) */
DRIVER( wwallyja ) /* (c) 1992 (FD1094 317-0197A) */
DRIVER( wwallyja3p ) /* (c) 1992 (FD1094 317-0198A) */
DRIVER( wwallyjd ) /* bootleg (decrypted wwallyj) */
DRIVER( wwallyjad ) /* bootleg (decrypted wwallyja) */
DRIVER( ddcrew ) /* (c) 1991 (FD1094 317-0190) */
DRIVER( ddcrewu ) /* (c) 1991 (FD1094 317-0186) */
DRIVER( ddcrew2 ) /* (c) 1991 (FD1094 317-0184) */
DRIVER( ddcrew1 ) /* (c) 1991 (FD1094 317-0187) */
DRIVER( ddcrewj ) /* (c) 1991 (FD1094 317-0185) */
DRIVER( ddcrewj2 ) /* (c) 1991 (FD1094 317-0182) */
DRIVER( ddcrewd ) /* bootleg (decrypted ddcrew) */
DRIVER( ddcrewud ) /* bootleg (decrypted ddcrewu) */
DRIVER( ddcrew2d ) /* bootleg (decrypted ddcrew2) */
DRIVER( ddcrew1d ) /* bootleg (decrypted ddcrew1) */
DRIVER( ddcrewjd ) /* bootleg (decrypted ddcrewj) */
DRIVER( ddcrewj2d ) /* bootleg (decrypted ddcrewj2) */
DRIVER( desertbr ) /* (c) 1992 (FD1094 317-0196) */
DRIVER( desertbrj ) /* (c) 1992 (FD1094 317-0194) */
DRIVER( desertbrd ) /* bootleg (decrypted desertbr) */
DRIVER( desertbrjd ) /* bootleg (decrypted desertbrj) */
DRIVER( lghost ) /* (c) 1990 (FD1094 317-0166) */
DRIVER( lghostu ) /* (c) 1990 (FD1094 317-0165) */
DRIVER( lghostj ) /* (c) 1990 (FD1094 317-0164) */
DRIVER( lghostd ) /* bootleg (decrypted lghost) */
DRIVER( lghostud ) /* bootleg (decrypted lghostu) */
DRIVER( mwalk ) /* (c) 1990 (FD1094/8751 317-0159) */
DRIVER( mwalku ) /* (c) 1990 (FD1094/8751 317-0158) */
DRIVER( mwalkj ) /* (c) 1990 (FD1094/8751 317-0157) */
DRIVER( mwalkd ) /* bootleg (decrypted mwalk) */
DRIVER( mwalkud ) /* bootleg (decrypted mwalku) */
DRIVER( mwalkjd ) /* bootleg (decrypted mwalkj) */
DRIVER( moonwlkb ) /* bootleg */
DRIVER( outrun ) /* (c) 1986 (bootleg)*/
DRIVER( outruna ) /* (c) 1986 (bootleg) */
@@ -3289,12 +3496,19 @@ DokiDoki Penguin Land *not confirmed
DRIVER( rachero ) /* 1989 (decrypted) */
DRIVER( riotcity ) /* (c) 1991 Sega / Westone */
DRIVER( sdi ) /* (c) 1987 */
DRIVER( shangonb ) /* (c) 1992 (but bootleg) */
DRIVER( shangon ) /* (c) 1987 */
DRIVER( shangon1 ) /* (c) 1987 (FD1089B) */
DRIVER( shangon2 ) /* (c) 1987 (FD1089B) */
DRIVER( shangon3 ) /* (c) 1987 (FD1089B) */
DRIVER( shangon3d ) /* (c) 1987 (bootleg) */
DRIVER( shangonle ) /* (c) 1991 */
DRIVER( shangonrb ) /* (c) 1992 (bootleg) */
DRIVER( shangonrb2 ) /* (c) 1987 (Beta bootleg) */
DRIVER( sharrier ) /* (c) 1985 */
DRIVER( shdancbl ) /* (c) 1989 (but bootleg) */
DRIVER( shdancer ) /* (c) 1989 */
DRIVER( shdancrj ) /* (c) 1989 */
DRIVER( shdancrb ) /* (c) 1989 */
DRIVER( shdancerj ) /* (c) 1989 */
DRIVER( shdancer1 ) /* (c) 1989 */
DRIVER( shinobi ) /* (c) 1987 */
DRIVER( shinobl ) /* (c) 1987 (but bootleg) */
DRIVER( smgp ) /* 1989 (decrypted) */
@@ -3386,7 +3600,9 @@ Sep.1994 Quiz Ghost Hunter
DRIVER( bakubaku )
DRIVER( colmns97 )
DRIVER( cotton2 )
DRIVER( cotton2e )
DRIVER( cottonbm )
DRIVER( cottonbme ) /* bootleg (English translation) */
DRIVER( decathlt )
DRIVER( diehard )
DRIVER( dnmtdeka )
@@ -3408,14 +3624,25 @@ Sep.1994 Quiz Ghost Hunter
DRIVER( pblbeach )
DRIVER( prikura )
DRIVER( puyosun )
DRIVER( puyosune ) /* bootleg, English translation */
DRIVER( rsgun )
DRIVER( sandor )
DRIVER( thunt )
DRIVER( sassisu )
DRIVER( sasissu )
DRIVER( sanjeon )
DRIVER( critcrsh )
DRIVER( tatacot )
DRIVER( danchiq )
DRIVER( micrombc )
DRIVER( patocar )
DRIVER( skychal )
DRIVER( supgoal )
DRIVER( techbowl )
DRIVER( wasafari )
DRIVER( seabass )
DRIVER( shanhigw )
DRIVER( shienryu )
DRIVER( sleague )
DRIVER( smleague )
DRIVER( sokyugrt )
DRIVER( sss )
DRIVER( suikoenb )
@@ -3425,6 +3652,8 @@ Sep.1994 Quiz Ghost Hunter
DRIVER( vmahjong )
DRIVER( winterht )
DRIVER( znpwfv )
DRIVER( znpwfvt )
DRIVER( znpwfve )
DRIVER( danchih )
DRIVER( mausuke )
@@ -3454,57 +3683,94 @@ Propose deniam-16c 1997/06/21
BOMULEUL CHAJARA SEGA ST-V 1997/04/11
*/
/* System C games */
DRIVER( bloxeedc ) /* (c) 1989 Sega / Elorg*/
DRIVER( columns ) /* (c) 1990 Sega */
/* System C / C-2 (drivers/segac2.c) */
DRIVER( bloxeedc ) /* (c) 1989 Sega / Elorg */
DRIVER( bloxeedu ) /* (c) 1989 Sega / Elorg */
DRIVER( columns ) /* (c) 1990 Sega */
DRIVER( columnsu ) /* (c) 1990 Sega */
DRIVER( columnsj ) /* (c) 1990 Sega */
DRIVER( columns2 ) /* (c) 1990 Sega */
/* System C-2 games */
DRIVER( ssonicbr ) /* Sega, Unreleased */
DRIVER( borench ) /* (c) 1990 Sega */
DRIVER( tfrceac ) /* (c) 1990 Sega / Technosoft */
DRIVER( tfrceacj ) /* (c) 1990 Sega / Technosoft */
DRIVER( tfrceacb ) /* bootleg */
DRIVER( tfrceacjpb ) /* Prototype Bootleg */
DRIVER( ribbit ) /* (c) 1991 Sega */
DRIVER( column2j ) /* (c) 1990 Sega */
DRIVER( tfrceac ) /* (c) 1990 Technosoft / Sega */
DRIVER( tfrceacj ) /* (c) 1990 Technosoft / Sega */
DRIVER( tfrceacb ) /* (c) 1990 bootleg */
DRIVER( tfrceacjpb ) /* (c) 1990 bootleg */
DRIVER( borench ) /* (c) 1990 Sega */
DRIVER( borencha ) /* (c) 1990 Sega */
DRIVER( borenchj ) /* (c) 1990 Sega */
DRIVER( ribbit ) /* (c) 1991 Sega */
DRIVER( ribbitj ) /* (c) 1991 Sega */
DRIVER( twinsqua ) /* (c) 1991 Sega */
DRIVER( soniccar ) /* (c) 1991 Sega */
DRIVER( ssonicbr ) /* (c) 1992 hack */
DRIVER( ooparts ) /* (c) 1992 hack */
DRIVER( puyo ) /* (c) 1992 Compile / Sega */
DRIVER( puyobl ) /* (c) 1992 bootleg */
DRIVER( puyoj ) /* (c) 1992 Compile / Sega */
DRIVER( puyoja ) /* (c) 1992 Compile / Sega */
DRIVER( tantr ) /* (c) 1992 Sega */
DRIVER( tantrkor ) /* (c) 1993 Sega */
DRIVER( tantrbl ) /* bootleg */
DRIVER( tantrbl2 ) /* bootleg */
DRIVER( puyopuyo ) /* (c) 1992 Sega / Compile */
DRIVER( puyopuya ) /* (c) 1992 Sega / Compile */
DRIVER( puyopuyb ) /* bootleg */
DRIVER( ichir ) /* (c) 1994 Sega */
DRIVER( ichirk ) /* (c) 1994 Sega */
DRIVER( ichirj ) /* (c) 1994 Sega */
DRIVER( ichirjbl ) /* bootleg */
DRIVER( stkclmns ) /* (c) 1994 Sega */
DRIVER( puyopuy2 ) /* (c) 1994 Compile + Sega license */
DRIVER( tantrbl ) /* (c) 1992 bootleg */
DRIVER( tantrbl4 ) /* (c) 1992 bootleg */
DRIVER( tantrbl2 ) /* (c) 1994 bootleg */
DRIVER( tantrbl3 ) /* (c) 1994 bootleg */
DRIVER( wwanpanm ) /* (c) 1992 Sega */
DRIVER( wwanpanmo ) /* (c) 1992 Sega */
DRIVER( wwjumbo ) /* (c) 1990 Sega */
DRIVER( wwmarine ) /* (c) 1992 Sega */
DRIVER( wwpajero ) /* (c) 1990 Sega */
DRIVER( anpanman ) /* (c) 1992 Sega */
DRIVER( anpanmana ) /* (c) 1992 Sega */
DRIVER( sonicpop ) /* (c) 1993 Sega */
DRIVER( sonicfgt ) /* (c) 1993 Sega */
DRIVER( sonicfgtj ) /* (c) 1993 Sega */
DRIVER( potopoto ) /* (c) 1994 Sega */
DRIVER( zunkyou ) /* (c) 1994 Sega */
DRIVER( headonch ) /* Sega Unreleased */
DRIVER( ooparts ) /* Sega Unreleased */
DRIVER( stkclmns ) /* (c) 1994 Sega */
DRIVER( stkclmnsj ) /* (c) 1994 Sega */
DRIVER( ichir ) /* (c) 1994 Sega */
DRIVER( ichirbl ) /* (c) 1994 bootleg */
DRIVER( ichirk ) /* (c) 1994 Sega */
DRIVER( ichirj ) /* (c) 1994 Sega */
DRIVER( ichirjbl ) /* (c) 1994 bootleg */
DRIVER( puyopuy2 ) /* (c) 1994 Compile (Sega license) */
DRIVER( zunkyou ) /* (c) 1994 Sega */
DRIVER( headonch ) /* (c) 1994 hack */
DRIVER( pclubj ) /* (c) 1995 Atlus */
DRIVER( pclubjv2 ) /* (c) 1995 Atlus */
DRIVER( pclub ) /* (c) 1995 Atlus */
DRIVER( pclubjv3 ) /* (c) 1995 Atlus */
DRIVER( pclubjv4 ) /* (c) 1996 Atlus */
DRIVER( pclubjv5 ) /* (c) 1996 Atlus */
/* Atlus Print Club 'Games' C-2 board */
DRIVER( pclubj )
DRIVER( pclubjv2 )
DRIVER( pclubjv4 )
DRIVER( pclubjv5 )
/* Genie Hardware (uses Genesis VDP) also has 'Sun Mixing Co' put into tile ram */
DRIVER( puckpkmn ) /* (c) 2000 Genie */
/* Genie / Y-BOX hardware (drivers/megadriv_ybox.c) */
DRIVER( puckpkmn ) /* (c) 2000 Sun Mixing */
DRIVER( jingling ) /* (c) 2000 IBS Co. Ltd */
DRIVER( puckpkmnb ) /* bootleg */
DRIVER( jzth ) /* (c) 2000 <unknown> */
DRIVER( songjang ) /* (c) 2000 WAH LAB */
DRIVER( shuifeng ) /* (c) 1999 WAH LAB */
DRIVER( songjang ) /* (c) 2000 WAH LAP */
DRIVER( shuifeng ) /* (c) 1999 WAH LAP */
/* Sun Mixing Mega Drive based boards (drivers/megadriv_sunmix.c) */
DRIVER( topshoot ) /* (c) 1995 Sun Mixing */
DRIVER( sbubsm ) /* (c) 1996 Sun Mixing */
DRIVER( barek3mb ) /* (c) 1994 bootleg / Sega */
DRIVER( aladmdb ) /* (c) 1993 bootleg / Sega */
DRIVER( barek2ch ) /* (c) 1994 bootleg / Sega */
DRIVER( sonic2mb ) /* (c) 1993 bootleg / Sega */
DRIVER( sonic3mb ) /* (c) 1993 bootleg / Sega */
DRIVER( jparkmb ) /* (c) 1993 bootleg / Sega */
DRIVER( twinktmb ) /* (c) 1993 bootleg / Sega */
/* Mega Drive based bootlegs (drivers/megadriv_acbl.c) */
DRIVER( aladmdb ) /* (c) 1993 bootleg / Sega */
DRIVER( sonic2mb ) /* (c) 1993 bootleg / Sega */
DRIVER( sonic3mb ) /* (c) 1993 bootleg / Sega */
DRIVER( barek2mb ) /* (c) 1994 bootleg / Sega */
DRIVER( barek3mba ) /* (c) 1994 bootleg / Sega */
DRIVER( twinktmb ) /* (c) 1993 bootleg / Sega */
DRIVER( jparkmb ) /* (c) 1993 bootleg / Sega */
DRIVER( barekch ) /* (c) 1994 bootleg */
DRIVER( bk3ssrmb ) /* (c) 1994 bootleg / Sega */
DRIVER( srssf2mb ) /* (c) 1994 bootleg / Sega */
DRIVER( biohzdmb ) /* (c) 1995 bootleg / Sega */
DRIVER( mk3mdb ) /* (c) 1996 bootleg / Midway */
DRIVER( ssf2mdb ) /* (c) 1994 bootleg / Capcom */
DRIVER( srmdb ) /* (c) 1993 bootleg / Konami */
DRIVER( barek3mb ) /* (c) 1994 bootleg / Sega */
DRIVER( barek2ch ) /* (c) 1994 bootleg */
/* Sega MegaTech, the number shown ia on the label of the instruction rom */
DRIVER( mt_beast ) /* 01 */
@@ -3571,9 +3837,10 @@ BOMULEUL CHAJARA SEGA ST-V 1997/04/11
/* Sega MegaPlay */
DRIVER( mp_sonic ) /* 01 */
DRIVER( mp_gaxe2 ) /* 02 */
DRIVER( mp_gaxe2a ) /* 02 */
DRIVER( mp_gslam ) /* 03 */
DRIVER( mp_sor2 ) /* 03 */
DRIVER( mp_twc ) /* 04 */
DRIVER( mp_twcup ) /* 04 */
DRIVER( mp_soni2 ) /* 05 */
DRIVER( mp_bio ) /* 06 */
DRIVER( mp_shnb3 ) /* 07 */
@@ -4414,6 +4681,7 @@ BOMULEUL CHAJARA SEGA ST-V 1997/04/11
DRIVER( foodf ) /* 136020 (c) 1982 */ /* made by Gencomp */
DRIVER( foodf2 ) /* 136020 (c) 1982 */ /* made by Gencomp */
DRIVER( foodfc ) /* 136020 (c) 1982 */ /* made by Gencomp */
DRIVER( akkaarrh )
DRIVER( ccastles ) /* 136022 (c) 1983 */
DRIVER( ccastle3 ) /* 136022 (c) 1983 */
DRIVER( ccastle2 ) /* 136022 (c) 1983 */
@@ -5204,6 +5472,65 @@ BOMULEUL CHAJARA SEGA ST-V 1997/04/11
DRIVER( nzeroteamb ) /* New Zero Team (V33 SYSTEM TYPE_B hardware, Haoyunlai Trading Company license) */
DRIVER( zerotm2k ) /* Zero Team 2000 */
/* Seibu SPI / SYS386I games */
DRIVER( senkyu ) /* Senkyu (Japan, newer) */
DRIVER( senkyua ) /* Senkyu (Japan, earlier) */
DRIVER( batlball ) /* Battle Balls (Germany, newer) */
DRIVER( batlballo ) /* Battle Balls (Germany, earlier) */
DRIVER( batlballu ) /* Battle Balls (US) */
DRIVER( batlballa ) /* Battle Balls (Hong Kong) */
DRIVER( batlballe ) /* Battle Balls (Hong Kong, earlier) */
DRIVER( batlballpt ) /* Battle Balls (Portugal) */
DRIVER( viprp1 ) /* Viper Phase 1 (New Version, World) */
DRIVER( viprp1k ) /* Viper Phase 1 (New Version, Korea) */
DRIVER( viprp1u ) /* Viper Phase 1 (New Version, US set 1) */
DRIVER( viprp1ua ) /* Viper Phase 1 (New Version, US set 2) */
DRIVER( viprp1j ) /* Viper Phase 1 (New Version, Japan) */
DRIVER( viprp1s ) /* Viper Phase 1 (New Version, Switzerland) */
DRIVER( viprp1h ) /* Viper Phase 1 (New Version, Holland) */
DRIVER( viprp1t ) /* Viper Phase 1 (New Version, Germany) */
DRIVER( viprp1pt ) /* Viper Phase 1 (New Version, Portugal) */
DRIVER( viprp1ot ) /* Viper Phase 1 (Germany) */
DRIVER( viprp1oj ) /* Viper Phase 1 (Japan) */
DRIVER( viprp1hk ) /* Viper Phase 1 (Hong Kong) */
DRIVER( rdft ) /* Raiden Fighters (Germany) */
DRIVER( rdftj ) /* Raiden Fighters (Japan, earlier) */
DRIVER( rdftja ) /* Raiden Fighters (Japan, earliest) */
DRIVER( rdftu ) /* Raiden Fighters (US, earlier) */
DRIVER( rdftauge ) /* Raiden Fighters (Evaluation Software For Show, Germany) */
DRIVER( rdftua ) /* Raiden Fighters (US, newer) */
DRIVER( rdftjb ) /* Raiden Fighters (Japan, newer) */
DRIVER( rdftau ) /* Raiden Fighters (Australia) */
DRIVER( rdftam ) /* Raiden Fighters (Hong Kong) */
DRIVER( rdftadi ) /* Raiden Fighters (Korea, SUB4 cart) */
DRIVER( rdfta ) /* Raiden Fighters (Austria) */
DRIVER( rdftgb ) /* Raiden Fighters (Great Britain) */
DRIVER( rdftgr ) /* Raiden Fighters (Greece) */
DRIVER( rdftit ) /* Raiden Fighters (Italy) */
DRIVER( rdftadia ) /* Raiden Fighters (Korea, SUB2 cart) */
DRIVER( rdft2 ) /* Raiden Fighters 2 - Operation Hell Dive (Germany) */
DRIVER( rdft2j ) /* Raiden Fighters 2 - Operation Hell Dive (Japan set 1) */
DRIVER( rdft2a ) /* Raiden Fighters 2 - Operation Hell Dive (Hong Kong) */
DRIVER( rdft2s ) /* Raiden Fighters 2 - Operation Hell Dive (Switzerland) */
DRIVER( rdft2ja ) /* Raiden Fighters 2 - Operation Hell Dive (Japan set 2) */
DRIVER( rdft2aa ) /* Raiden Fighters 2 - Operation Hell Dive (Korea) */
DRIVER( rdft2it ) /* Raiden Fighters 2 - Operation Hell Dive (Italy) */
DRIVER( rdft2jb ) /* Raiden Fighters 2 - Operation Hell Dive (Japan set 3) */
DRIVER( rdft2jc ) /* Raiden Fighters 2 - Operation Hell Dive (Japan set 4) */
DRIVER( rdft2t ) /* Raiden Fighters 2 - Operation Hell Dive (Taiwan) */
DRIVER( rdft2u ) /* Raiden Fighters 2 - Operation Hell Dive (US) */
DRIVER( rfjet ) /* Raiden Fighters Jet (Germany) */
DRIVER( rfjetu ) /* Raiden Fighters Jet (US) */
DRIVER( rfjetj ) /* Raiden Fighters Jet (Japan) */
DRIVER( rfjeta ) /* Raiden Fighters Jet (Korea) */
DRIVER( rfjett ) /* Raiden Fighters Jet (Taiwan) */
DRIVER( rdfts ) /* Raiden Fighters (Taiwan, single board) */
DRIVER( rdft2us ) /* Raiden Fighters 2 - Operation Hell Dive (US, single board) */
DRIVER( rfjets ) /* Raiden Fighters Jet (US, single board) */
DRIVER( rfjetsa ) /* Raiden Fighters Jet (US, single board, test version?) */
DRIVER( rdft22kc ) /* Raiden Fighters 2 - Operation Hell Dive 2000 (China, SYS386I) */
DRIVER( rfjet2kc ) /* Raiden Fighters Jet 2000 (China, SYS386I) */
/* Seibu STI System games:
Viper: Phase 1 (c) 1995
Viper: Phase 1 (New version) (c) 1996
@@ -5382,6 +5709,7 @@ BOMULEUL CHAJARA SEGA ST-V 1997/04/11
DRIVER( fromancr ) /* (c) 1995 Video System Co. (Japan) */
DRIVER( fromanc4 ) /* (c) 1998 Video System Co. (Japan) */
DRIVER( inufuku ) /* (c) 1998 Video System Co. (Japan) */
DRIVER( 3on3dunk ) /* (c) 1996 Video System Co. ( US ) */
/* Psikyo games */
DRIVER( samuraia ) /* (c) 1993 (World) */
@@ -5488,6 +5816,10 @@ BOMULEUL CHAJARA SEGA ST-V 1997/04/11
/* Kaneko games */
DRIVER( jumpkun ) /* (c) 1984 Kaneko */
DRIVER( hvyunit ) /* (c) 1988 Kaneko + Taito */
DRIVER( hvyunitj ) /* (c) 1988 Kaneko + Taito (Japan) */
DRIVER( hvyunitjo ) /* (c) 1988 Kaneko + Taito (Japan Older) */
DRIVER( hvyunitu ) /* (c) 1988 Kaneko + Taito (USA) */
DRIVER( djboy ) /* (c) 1989 Kaneko */
DRIVER( djboyj ) /* (c) 1989 Kaneko */
DRIVER( airbustr ) /* (c) 1990 Kaneko + Namco */
@@ -5831,7 +6163,10 @@ Other Sun games
/* Fuuki FG-3 games */
DRIVER( asurabld ) /* (c) 1998 (Japan) */
DRIVER( asurabus ) /* (c) 2000 (Japan) */
DRIVER( asurabus ) /* (c) 2001 (USA) */
DRIVER( asurabusj ) /* (c) 2000 (Japan) */
DRIVER( asurabusja ) /* (c) 2000 (Japan) */
DRIVER( asurabusjr ) /* (c) 2000 (Japan) */
/* Unico games */
DRIVER( drgnmst ) /* (c) 1994 */
@@ -6606,4 +6941,12 @@ Other Sun games
DRIVER( roundup5 )
DRIVER( bigfight )
DRIVER( cyclwarr )
/* Tatsumi TX-1 / Buggy Boy */
DRIVER( tx1 ) /* (c) 1983 Tatsumi (Atari/Namco/Taito license) */
DRIVER( tx1jb ) /* (c) 1983 Tatsumi */
DRIVER( tx1jc ) /* (c) 1983 Tatsumi */
DRIVER( buggyboy ) /* (c) 1985 Tatsumi */
DRIVER( buggyboyb ) /* (c) 1986 Tatsumi */
DRIVER( buggyboyjr ) /* (c) 1986 Tatsumi */
#endif /* DRIVER_RECURSIVE */
src/driver.h
+2 -1
View File
@@ -70,6 +70,7 @@
#include "palette.h"
#include "cpuintrf.h"
#include "cpuexec.h"
#include "machine/random.h"
#include "cpuint.h"
#include "sndintrf.h"
#include "input.h"
@@ -440,7 +441,7 @@ struct GameDriver
#define GAME_NO_COCKTAIL 0x0100 /* screen flip support is missing */
#define GAME_NO_SOUND 0x0200 /* sound is missing */
#define GAME_IMPERFECT_SOUND 0x0400 /* sound is known to be wrong */
#define GAME_DOESNT_SERIALIZE 0x0420 /* game can not be saved through serailization */
#define GAME_DOESNT_SERIALIZE 0x0800 /* game can not be saved through serialization */
#define NOT_A_DRIVER 0x4000 /* set by the fake "root" driver_0 and by "containers" */
/* e.g. driver_neogeo. */
src/drivers/8080bw_drivers.c
+10 -1
View File
@@ -1873,7 +1873,7 @@ static READ_HANDLER( indianbt_r )
case 0x5ffc: return 0;
}
logerror("unknown port 0 read @ %x\n",activecpu_get_pc());
return rand();
return mame_rand_int();
}
static PORT_READ_START( indianbt_readport )
@@ -2241,6 +2241,15 @@ INPUT_PORTS_START( polaris )
PORT_DIPNAME( 0x01, 0x00, DEF_STR( Cabinet ) )
PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
PORT_DIPSETTING( 0x01, DEF_STR( Cocktail ) )
PORT_START /* 4, read by POLARIS_ADJ_VR1 */
PORT_ADJUSTER( 80, "Sub Volume VR1" )
PORT_START /* 5, read by POLARIS_ADJ_VR2 */
PORT_ADJUSTER( 70, "Sub Volume VR2" )
PORT_START /* 6, read by POLARIS_ADJ_VR3 */
PORT_ADJUSTER( 90, "Sub Volume VR3" )
INPUT_PORTS_END
static MACHINE_DRIVER_START( polaris )
src/drivers/ace.c
+1 -1
View File
@@ -137,7 +137,7 @@ static WRITE_HANDLER( ace_characterram_w )
static READ_HANDLER( unk_r )
{
return rand()&0xff;
return mame_rand_int()&0xff;
}
src/drivers/airbustr.c
+1 -1
View File
@@ -271,7 +271,7 @@ READ_HANDLER( devram_r )
equal values */
case 0xff4:
{
return rand();
return mame_rand_int();
} break;
default: { return devram[offset]; break;}
src/drivers/akkaarrh.c
+307
View File
@@ -0,0 +1,307 @@
// license:BSD-3-Clause
// copyright-holders:Aaron Giles
/*
Atari Akka Arrh hardware
*/
#include "driver.h"
#include "cpu/m6502/m6502.h"
#include "sound/pokey.h"
static UINT8 *akkaarrh_videoram;
static UINT8 *akkaarrh_spriteram;
static struct tilemap *akkaarrh_tilemap[4];
static UINT8 video_mirror;
static UINT8 earom[64];
static UINT8 earom_address, earom_data, earom_control;
static void get_tile_info(int tile_index)
{
int attr = akkaarrh_videoram[tile_index + 0x400];
SET_TILE_INFO(0, akkaarrh_videoram[tile_index], attr & 15, TILE_FLIPYX(attr >> 6))
}
static VIDEO_START( akkaarrh )
{
int i;
for (i = 0; i < 4; ++i)
{
akkaarrh_tilemap[i] = tilemap_create(get_tile_info, tilemap_scan_rows, TILEMAP_OPAQUE, 8, 8, 32, 30);
if (!akkaarrh_tilemap[i])
return 1;
tilemap_set_flip(akkaarrh_tilemap[i], ((i & 1) ? TILEMAP_FLIPX : 0) | ((i & 2) ? TILEMAP_FLIPY : 0));
}
return 0;
}
static VIDEO_UPDATE( akkaarrh )
{
int i;
if (!(video_mirror & 1))
tilemap_draw(bitmap, cliprect, akkaarrh_tilemap[0], 0, 0);
else
{
/* Zoom uses reflected copies of the upper-left quadrant. */
for (i = 0; i < 4; ++i)
{
struct rectangle clip = *cliprect;
int left = (i & 1) * 128;
int top = (i >> 1) * 120;
if (clip.min_x < left) clip.min_x = left;
if (clip.max_x > left + 127) clip.max_x = left + 127;
if (clip.min_y < top) clip.min_y = top;
if (clip.max_y > top + 119) clip.max_y = top + 119;
if (clip.min_x <= clip.max_x && clip.min_y <= clip.max_y)
tilemap_draw(bitmap, &clip, akkaarrh_tilemap[i], 0, 0);
}
}
for (i = 0; i < 0x100; i += 4)
drawgfx(bitmap, Machine->gfx[1], akkaarrh_spriteram[i + 1], akkaarrh_spriteram[i] & 15,
0, 0, akkaarrh_spriteram[i + 3], 240 - akkaarrh_spriteram[i + 2], cliprect, TRANSPARENCY_PEN, 0);
}
static WRITE_HANDLER( akkaarrh_videoram_w )
{
int i;
akkaarrh_videoram[offset] = data;
for (i = 0; i < 4; ++i)
tilemap_mark_tile_dirty(akkaarrh_tilemap[i], offset & 0x3ff);
}
static WRITE_HANDLER( akkaarrh_palette_w )
{
paletteram[offset] = data;
palette_set_color(offset, pal3bit(data >> 5), pal2bit(data >> 3), pal3bit(data));
}
static WRITE_HANDLER( akkaarrh_irq_ack_w )
{
cpu_set_irq_line(0, M6502_IRQ_LINE, CLEAR_LINE);
}
static WRITE_HANDLER( akkaarrh_mirror_w )
{
video_mirror = data;
}
static WRITE_HANDLER( akkaarrh_output_w )
{
int i;
if (!offset)
{
set_led_status(0, !(data & 8));
set_led_status(1, !(data & 4));
coin_counter_w(0, data & 1);
coin_counter_w(1, data & 2);
}
else
for (i = 0; i < 8; ++i)
set_led_status(2 + (offset - 1) * 8 + i, (data >> i) & 1);
}
static READ_HANDLER( akkaarrh_earom_r )
{
return earom_data;
}
static WRITE_HANDLER( akkaarrh_earom_w )
{
earom_address = offset & 63;
earom_data = data;
}
static void earom_update(void)
{
if (!(earom_control & 2))
{
/* Programming only clears bits; an erase cycle must precede it. */
if (earom_control & 4)
earom[earom_address] = 0xff;
else
earom[earom_address] &= earom_data;
}
}
static WRITE_HANDLER( akkaarrh_earom_control_w )
{
UINT8 old = earom_control;
earom_control = (old & 1) | ((data & 4) ? 0 : 2) | ((data & 2) ? 4 : 0) | (data & 8);
if ((earom_control & 8) && earom_control != old)
earom_update();
old = earom_control;
earom_control = (earom_control & ~1) | (data & 1);
/* Reads latch on the falling clock edge while chip select is active. */
if ((earom_control & 8) && (old & 1) && !(data & 1))
{
if (earom_control & 2)
earom_data = earom[earom_address];
earom_update();
}
}
static NVRAM_HANDLER( akkaarrh )
{
if (read_or_write)
mame_fwrite(file, earom, sizeof(earom));
else if (file)
mame_fread(file, earom, sizeof(earom));
else
memset(earom, 0xff, sizeof(earom));
}
static MEMORY_READ_START( akkaarrh_readmem )
{ 0x0000, 0x07ff, MRA_RAM },
{ 0x1000, 0x10ff, MRA_RAM },
{ 0x2000, 0x27ff, MRA_RAM },
{ 0x3000, 0x30ff, MRA_RAM },
{ 0x7010, 0x701f, pokey1_r },
{ 0x7020, 0x702f, pokey2_r },
{ 0x7040, 0x707f, MRA_NOP },
{ 0x7080, 0x7080, input_port_0_r },
{ 0x7081, 0x7081, input_port_1_r },
{ 0x7082, 0x7082, input_port_2_r },
{ 0x7083, 0x7083, input_port_3_r },
{ 0x7087, 0x7087, akkaarrh_earom_r },
{ 0x8000, 0xffff, MRA_ROM },
MEMORY_END
static MEMORY_WRITE_START( akkaarrh_writemem )
{ 0x0000, 0x07ff, MWA_RAM },
{ 0x1000, 0x10ff, MWA_RAM, &akkaarrh_spriteram },
{ 0x2000, 0x27ff, akkaarrh_videoram_w, &akkaarrh_videoram },
{ 0x3000, 0x30ff, akkaarrh_palette_w, &paletteram },
{ 0x4000, 0x4000, akkaarrh_irq_ack_w },
{ 0x5000, 0x5000, watchdog_reset_w },
{ 0x6000, 0x6000, akkaarrh_mirror_w },
{ 0x7010, 0x701f, pokey1_w },
{ 0x7020, 0x702f, pokey2_w },
{ 0x7040, 0x707f, akkaarrh_earom_w },
{ 0x70c0, 0x70c3, akkaarrh_output_w },
{ 0x70c7, 0x70c7, akkaarrh_earom_control_w },
{ 0x8000, 0xffff, MWA_ROM },
MEMORY_END
INPUT_PORTS_START( akkaarrh )
PORT_START
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 ) //Zoom
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) //Fire
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON2 ) //Power blaster
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN3 )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START2 )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START
PORT_ANALOG( 0x0f, 0x00, IPT_TRACKBALL_X | IPF_REVERSE, 30, 20, 0, 0)
PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START
PORT_ANALOG( 0x0f, 0x00, IPT_TRACKBALL_Y, 30, 20, 0, 0)
PORT_BIT( 0x30, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_VBLANK )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
INPUT_PORTS_END
static struct GfxLayout tile_layout =
{
8, 8, RGN_FRAC(1,4), 4,
{ RGN_FRAC(3,4), RGN_FRAC(2,4), RGN_FRAC(1,4), RGN_FRAC(0,4) },
{ 0,1,2,3,4,5,6,7 },
{ 0*8,1*8,2*8,3*8,4*8,5*8,6*8,7*8 },
8*8
};
static struct GfxLayout sprite_layout =
{
16, 16, RGN_FRAC(1,4), 4,
{ RGN_FRAC(3,4), RGN_FRAC(2,4), RGN_FRAC(1,4), RGN_FRAC(0,4) },
{ 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 },
{ 0*16,1*16,2*16,3*16,4*16,5*16,6*16,7*16,8*16,9*16,10*16,11*16,12*16,13*16,14*16,15*16 },
16*16
};
static struct GfxDecodeInfo gfxdecodeinfo[] =
{
{ REGION_GFX1, 0, &tile_layout, 0, 16 },
{ REGION_GFX2, 0, &sprite_layout, 0, 16 },
{ -1 }
};
static struct POKEYinterface pokey_interface =
{
2, /* 2 chips */
1250000, /* 125 MHz */
{ 50, 50 },
/* The 8 pot handlers */
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
/* The allpot handler */
{ 0, 0 },
};
static MACHINE_DRIVER_START( akkaarrh )
MDRV_CPU_ADD(M6502, 12096000/8)
MDRV_CPU_MEMORY(akkaarrh_readmem, akkaarrh_writemem)
/* The interrupt handler must sample VBLANK once per group of four IRQs. */
MDRV_CPU_VBLANK_INT(irq0_line_assert, 4)
MDRV_FRAMES_PER_SECOND(60)
MDRV_VBLANK_DURATION((int)(1000000.0 * 22 / (60 * 262)))
MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER)
MDRV_SCREEN_SIZE(256, 262)
MDRV_VISIBLE_AREA(0, 255, 0, 239)
MDRV_GFXDECODE(gfxdecodeinfo)
MDRV_PALETTE_LENGTH(256)
MDRV_NVRAM_HANDLER(akkaarrh)
MDRV_VIDEO_START(akkaarrh)
MDRV_VIDEO_UPDATE(akkaarrh)
/* sound hardware */
MDRV_SOUND_ADD(POKEY, pokey_interface)
MACHINE_DRIVER_END
ROM_START( akkaarrh )
ROM_REGION( 0x10000, REGION_CPU1, 0 )
ROM_LOAD( "akka_8000.p1", 0x8000, 0x1000, CRC(578bb162) SHA1(f003d9a63e397c377e4738ca31a637da1da2cbdb) )
ROM_LOAD( "akka_9000.m1", 0x9000, 0x1000, CRC(837fa612) SHA1(2a2ccbf879fd9cfc0342e6c5bbcd23962bdbbcde) )
ROM_LOAD( "akka_a000.l1", 0xa000, 0x1000, CRC(13c769e9) SHA1(8e6c7b21fa555850ba8d00abbb4516e483964b5d) )
ROM_LOAD( "akka_b000.j1", 0xb000, 0x1000, CRC(35c04f28) SHA1(71ad7eaf5bf96c1a0a321f1b04706afd40d9757f) )
ROM_LOAD( "akka_c000.h1", 0xc000, 0x1000, CRC(17e85ac4) SHA1(bd010060eaf8fbf27176d4fdec241ee3b42aece8) )
ROM_LOAD( "akka_d000.e1", 0xd000, 0x1000, CRC(03fb4143) SHA1(3a2106d7322139b9924566133d084bb7c5d769bc) )
ROM_LOAD( "akka_e000.f1", 0xe000, 0x1000, CRC(8d3e671c) SHA1(c99d92c4afaa1ba043520b98d925f83490e49f0a) )
ROM_RELOAD( 0xf000, 0x1000 )
ROM_REGION( 0x2000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "akka_pf0.l6", 0x0000, 0x0800, CRC(5c10b63e) SHA1(27ac6cebb3f6733cb830210f4723938ec2ddaafc) )
ROM_LOAD( "akka_pf1.j6", 0x0800, 0x0800, CRC(636fd64c) SHA1(c2985332b8f32a8dd096fc081df12ae1a132e6a3) )
ROM_LOAD( "akka_pf2.p6", 0x1000, 0x0800, CRC(a5f25d69) SHA1(8f5af774db3ed3969c8c0a0b530ea62198830e3d) )
ROM_LOAD( "akka_pf3.m6", 0x1800, 0x0800, CRC(a3449469) SHA1(42f2ccf6ea02987bfb91ff1ca42684e9700f2f8f) )
ROM_REGION( 0x4000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "akka_mo0.f11", 0x0000, 0x1000, CRC(71bd1bc6) SHA1(9c3d2c039c648834a7a0b98cd2dcbbbb88f74dd8) )
ROM_LOAD( "akka_mo1.d11", 0x1000, 0x1000, CRC(a5ee8ecc) SHA1(d2a8c9791dca9157d9d20b8a4f6e760e6db35f05) )
ROM_LOAD( "akka_mo2.a11", 0x2000, 0x1000, CRC(11cec4d9) SHA1(32ea614c25473aeb9a012a3980ad616592f6c3bb) )
ROM_LOAD( "akka_mo3.b11", 0x3000, 0x1000, CRC(adcf6a36) SHA1(0555a252ba39400d2c533add6ac492926674d6ad) )
ROM_END
GAME( 1982, akkaarrh, 0, akkaarrh, akkaarrh, 0, ROT0, "Atari", "Akka Arrh (prototype)" )
src/drivers/armedf.c
+323 -1
View File
@@ -147,6 +147,7 @@ Stephh's notes (based on the games M68000 code and some tests) :
#include "vidhrdw/generic.h"
#include "cpu/m68000/m68000.h"
#include "cpu/z80/z80.h"
#include "cpu/i8051/i8051.h"
#define LEGION_HACK 0
@@ -178,6 +179,24 @@ extern data16_t *terraf_text_videoram;
extern data16_t *legion_cmd;
extern struct tilemap *armedf_tx_tilemap;
static UINT8 bigfghtr_sharedram[0x3a00];
static READ_HANDLER( bigfghtr_mcu_movx_r )
{
if ( offset >= 0x0600 && offset <= 0x3fff)
return bigfghtr_sharedram[offset-0x600];
else
printf("offset mcu_read: %x\n",offset-0x600);
}
static WRITE_HANDLER( bigfghtr_mcu_movx_w )
{
if ( offset >= 0x0600 && offset <= 0x3fff)
bigfghtr_sharedram[offset-0x600] = data;
else
printf("unmapped offset mcu_write: %x\n",offset);
}
static WRITE16_HANDLER( io_w )
{
@@ -414,6 +433,113 @@ static MEMORY_WRITE16_START( armedf_writemem )
MEMORY_END
static READ16_HANDLER( bigfghtr_sharedram_r )
{
return (bigfghtr_sharedram[offset * 2] << 8) | bigfghtr_sharedram[offset * 2 + 1];
}
static WRITE16_HANDLER( bigfghtr_sharedram_w )
{
if (ACCESSING_MSB)
bigfghtr_sharedram[offset * 2] = data >> 8;
if (ACCESSING_LSB)
bigfghtr_sharedram[offset * 2 + 1] = data;
}
static READ_HANDLER( bigfghtr_mcu_sharedram_r )
{
return bigfghtr_sharedram[offset];
}
static WRITE_HANDLER( bigfghtr_mcu_sharedram_w )
{
bigfghtr_sharedram[offset] = data;
}
static READ_HANDLER( bigfghtr_mcu_p1_r )
{
return 0xdf;
}
static READ16_HANDLER( bigfghtr_latch_r )
{
cpu_set_irq_line(2, I8051_INT0_LINE, CLEAR_LINE);
cpu_set_irq_line(2, I8051_INT0_LINE, ASSERT_LINE);
return 0;
}
static WRITE16_HANDLER( bigfghtr_irq_ack_w )
{
cpu_set_irq_line(0, 1, CLEAR_LINE);
}
static INTERRUPT_GEN( bigfghtr_interrupt )
{
cpu_set_irq_line(0, 1, ASSERT_LINE);
}
static MACHINE_INIT( bigfghtr )
{
memset(bigfghtr_sharedram, 0, sizeof(bigfghtr_sharedram));
armedf_vreg = 0;
cpu_set_irq_line(2, I8051_INT0_LINE, CLEAR_LINE);
}
static MEMORY_READ16_START( bigfghtr_readmem )
{ 0x000000, 0x07ffff, MRA16_ROM },
{ 0x080000, 0x0805ff, MRA16_RAM },
{ 0x080600, 0x083fff, bigfghtr_sharedram_r },
{ 0x084000, 0x085fff, MRA16_RAM },
{ 0x086000, 0x086fff, MRA16_RAM },
{ 0x087000, 0x087fff, MRA16_RAM },
{ 0x088000, 0x089fff, MRA16_RAM },
{ 0x08a000, 0x08afff, MRA16_RAM },
{ 0x08b000, 0x08bfff, MRA16_RAM },
{ 0x08c000, 0x08c001, input_port_0_word_r },
{ 0x08c002, 0x08c003, input_port_1_word_r },
{ 0x08c004, 0x08c005, input_port_2_word_r },
{ 0x08c006, 0x08c007, input_port_3_word_r },
{ 0x400000, 0x400001, bigfghtr_latch_r },
MEMORY_END
static MEMORY_WRITE16_START( bigfghtr_writemem )
{ 0x000000, 0x07ffff, MWA16_ROM },
{ 0x080000, 0x0805ff, MWA16_RAM, &spriteram16, &spriteram_size },
{ 0x080600, 0x083fff, bigfghtr_sharedram_w },
{ 0x084000, 0x085fff, MWA16_RAM },
{ 0x086000, 0x086fff, armedf_bg_videoram_w, &armedf_bg_videoram },
{ 0x087000, 0x087fff, armedf_fg_videoram_w, &armedf_fg_videoram },
{ 0x088000, 0x089fff, armedf_text_videoram_w, &terraf_text_videoram },
{ 0x08a000, 0x08afff, paletteram16_xxxxRRRRGGGGBBBB_word_w, &paletteram16 },
{ 0x08b000, 0x08bfff, MWA16_RAM, &spr_pal_clut },
{ 0x08d000, 0x08d001, terraf_io_w },
{ 0x08d002, 0x08d003, armedf_bg_scrollx_w },
{ 0x08d004, 0x08d005, armedf_bg_scrolly_w },
{ 0x08d006, 0x08d007, armedf_fg_scrollx_w },
{ 0x08d008, 0x08d009, armedf_fg_scrolly_w },
{ 0x08d00a, 0x08d00b, sound_command_w },
{ 0x08d00c, 0x08d00d, MWA16_NOP },
{ 0x08d00e, 0x08d00f, bigfghtr_irq_ack_w },
MEMORY_END
static MEMORY_READ_START( bigfghtr_mcu_readmem )
{ 0x0000, 0x0fff, MRA_ROM },
{ 0x0600, 0x3fff, bigfghtr_mcu_sharedram_r },
MEMORY_END
static MEMORY_WRITE_START( bigfghtr_mcu_writemem )
{ 0x0000, 0x0fff, MWA_ROM },
{ 0x0600, 0x3fff, bigfghtr_mcu_sharedram_w },
MEMORY_END
static PORT_READ_START( bigfghtr_mcu_readport )
{ I8051_P1, I8051_P1, bigfghtr_mcu_p1_r },
PORT_END
static PORT_WRITE_START( bigfghtr_mcu_writeport )
{ I8051_P1, I8051_P3, MWA_NOP },
PORT_END
static MEMORY_READ_START( soundreadmem )
{ 0x0000, 0xf7ff, MRA_ROM },
{ 0xf800, 0xffff, MRA_RAM },
@@ -792,6 +918,83 @@ INPUT_PORTS_START( armedf )
INPUT_PORTS_END
INPUT_PORTS_START( bigfghtr )
PORT_START
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER1)
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER1)
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER1)
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER1)
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1)
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER1)
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER1)
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_START1 )
PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_START2 )
PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_COIN2 )
PORT_BIT( 0xf000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER2)
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER2)
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER2)
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER2)
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2)
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2)
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER2)
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_SERVICE1 )
PORT_SERVICE( 0x0200, IP_ACTIVE_LOW )
PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0xf800, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START
PORT_DIPNAME( 0x03, 0x03, DEF_STR( Lives ) )
PORT_DIPSETTING( 0x03, "3" )
PORT_DIPSETTING( 0x02, "4" )
PORT_DIPSETTING( 0x01, "5" )
PORT_DIPSETTING( 0x00, "6" )
PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Bonus_Life ) )
PORT_DIPSETTING( 0x0c, "80k then every 80k" )
PORT_DIPSETTING( 0x04, "80k then every 100k" )
PORT_DIPSETTING( 0x08, "100k then every 80k" )
PORT_DIPSETTING( 0x00, "100k then every 100k" )
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Demo_Sounds ) )
PORT_DIPSETTING( 0x10, DEF_STR( On ) )
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPNAME( 0x20, 0x00, DEF_STR( Cabinet ) )
PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
PORT_DIPSETTING( 0x20, DEF_STR( Cocktail ) )
PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Difficulty ) )
PORT_DIPSETTING( 0xc0, "Easy" )
PORT_DIPSETTING( 0x80, "Normal" )
PORT_DIPSETTING( 0x40, "Hard" )
PORT_DIPSETTING( 0x00, "Hardest" )
PORT_START
PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_A ) )
PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
PORT_DIPSETTING( 0x00, DEF_STR( Free_Play ) )
PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Coin_B ) )
PORT_DIPSETTING( 0x04, DEF_STR( 2C_1C ) )
PORT_DIPSETTING( 0x0c, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ) )
PORT_DIPSETTING( 0x08, DEF_STR( 1C_2C ) )
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x20, 0x20, "Debug 2 (requires Debug On) (P2 Start skip stage, Invulnerability)" )
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Flip_Screen ) )
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x80, 0x80, "Debug (P1 Start to pause)" )
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
INPUT_PORTS_END
static struct GfxLayout char_layout =
{
@@ -839,7 +1042,14 @@ static struct GfxDecodeInfo gfxdecodeinfo[] =
{ -1 } /* end of array */
};
static struct GfxDecodeInfo bigfghtr_gfxdecodeinfo[] =
{
{ REGION_GFX1, 0, &char_layout, 0 * 16, 32 },
{ REGION_GFX2, 0, &tile_layout, 64 * 16, 32 },
{ REGION_GFX3, 0, &tile_layout, 96 * 16, 32 },
{ REGION_GFX4, 0, &tile_layout, 32 * 16, 32 },
{ -1 }
};
static struct YM3812interface ym3812_interface =
{
@@ -848,6 +1058,13 @@ static struct YM3812interface ym3812_interface =
{ 50 } /* (not supported) */
};
static struct YM3812interface bigfghtr_ym3812_interface =
{
1, /* 1 chip (no more supported) */
24000000/6, /* 4 MHz */
{ 50 } /* (not supported) */
};
static struct DACinterface dac_interface =
{
2, /* 2 channels */
@@ -861,6 +1078,38 @@ static struct DACinterface cclimbr2_dac_interface =
};
static MACHINE_DRIVER_START( bigfghtr )
MDRV_CPU_ADD(M68000, 16000000/2)
MDRV_CPU_MEMORY(bigfghtr_readmem, bigfghtr_writemem)
MDRV_CPU_VBLANK_INT(bigfghtr_interrupt, 1)
MDRV_CPU_ADD(Z80, 24000000/6)
MDRV_CPU_MEMORY(soundreadmem, soundwritemem)
MDRV_CPU_PORTS(readport, writeport)
MDRV_CPU_PERIODIC_INT(irq0_line_hold, (8000000/2/512))
MDRV_CPU_ADD(I8751, 16000000/2/I8051_CLOCK_DIVIDER)
MDRV_CPU_MEMORY(bigfghtr_mcu_readmem, bigfghtr_mcu_writemem)
MDRV_CPU_PORTS(bigfghtr_mcu_readport, bigfghtr_mcu_writeport)
MDRV_FRAMES_PER_SECOND(8000000.0 / (531 * 254))
MDRV_VBLANK_DURATION(DEFAULT_REAL_60HZ_VBLANK_DURATION)
MDRV_INTERLEAVE(100)
MDRV_MACHINE_INIT(bigfghtr)
MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER | VIDEO_BUFFERS_SPRITERAM)
MDRV_SCREEN_SIZE(64 * 8, 32 * 8)
MDRV_VISIBLE_AREA(12 * 8, (64 - 12) * 8 - 1, 8, 247)
MDRV_GFXDECODE(bigfghtr_gfxdecodeinfo)
MDRV_PALETTE_LENGTH(2048)
MDRV_VIDEO_EOF(armedf)
MDRV_VIDEO_START(armedf)
MDRV_VIDEO_UPDATE(armedf)
/* sound hardware */
MDRV_SOUND_ADD(YM3812, bigfghtr_ym3812_interface)
MDRV_SOUND_ADD(DAC, dac_interface)
MACHINE_DRIVER_END
static MACHINE_DRIVER_START( terraf )
@@ -1272,6 +1521,71 @@ ROM_START( armedf )
ROM_LOAD( "af_12.rom", 0x20000, 0x20000, CRC(23cb6bfe) SHA1(34cb013827206bea71f5336b308ba92bee688506) )
ROM_END
ROM_START( skyrobo )
ROM_REGION( 0x80000, REGION_CPU1, 0 )
ROM_LOAD16_BYTE( "3", 0x00000, 0x20000, CRC(02d8ba9f) SHA1(7622cc17561e5d1c069341b5f412f732f901d4a8) )
ROM_LOAD16_BYTE( "1", 0x00001, 0x20000, CRC(fcfd9e2e) SHA1(c69b34653f04af8d488e323bc2db89656f76c332) )
ROM_LOAD16_BYTE( "4", 0x40000, 0x20000, CRC(37ced4b7) SHA1(9ded66f795d3c0886f48e52de632e6edb8c57e84) )
ROM_LOAD16_BYTE( "2", 0x40001, 0x20000, CRC(88d52f8e) SHA1(33b0d2b3cd38a13d8580694e7c50c059914eebe2) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "8.17k", 0x00000, 0x10000, CRC(0aeab61e) SHA1(165e0ad58542b65383fef714578da21f62df7b74) )
ROM_REGION( 0x10000, REGION_CPU3, 0 )
ROM_LOAD( "i8751.bin", 0x00000, 0x1000, BAD_DUMP CRC(64a0d225) SHA1(ccc5c33c0c412bf9e3a4f7de5e39b042e00c41dd) )
ROM_REGION( 0x08000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "7", 0x00000, 0x08000, CRC(f556ef28) SHA1(2acb83cdf23356091056f2cfbbc2b9828ee25b6f) )
ROM_REGION( 0x30000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "5.13f", 0x00000, 0x20000, CRC(d440a29f) SHA1(9e6ea7c9903e5e3e8e10ac7680c6120e1aa27250) )
ROM_LOAD( "6.15f", 0x20000, 0x10000, CRC(27469a76) SHA1(ebf2c60e1f70a589680c05adf10771ac2097b9d0) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE )
ROM_LOAD( "12.8a", 0x00000, 0x10000, CRC(a5694ea9) SHA1(ea94174495b3a65b3797932074a94df3b55fa0a2) )
ROM_LOAD( "11.6a", 0x10000, 0x10000, CRC(10b74e2c) SHA1(e3ec68726e7f277dc2043424f2e4d863eb01b3dc) )
ROM_REGION( 0x40000, REGION_GFX4, ROMREGION_DISPOSE )
ROM_LOAD16_BYTE( "9.8d", 0x00000, 0x20000, CRC(fe67800e) SHA1(0d3c4c3cb185270260fa691a97cddf082d6a056e) )
ROM_LOAD16_BYTE( "10.9d", 0x00001, 0x20000, CRC(dcb828c4) SHA1(607bc86580a6fe6e15e91131532b0eecd8b7a0cb) )
ROM_REGION( 0x0100, REGION_PROMS, 0 )
ROM_LOAD( "tf.13h", 0x0000, 0x0100, CRC(81244757) SHA1(6324f63e571f0f7a0bb9eb97f9994809db79493f) )
ROM_END
ROM_START( bigfghtr )
ROM_REGION( 0x80000, REGION_CPU1, 0 )
ROM_LOAD16_BYTE( "3.ic3", 0x00000, 0x20000, CRC(e1e1f291) SHA1(dbbd707be6250d9ffcba3fee265869b72f790e26) )
ROM_LOAD16_BYTE( "1.ic2", 0x00001, 0x20000, CRC(1100d991) SHA1(3c79398804b3a26b3df0c5734b270c37e1ba6a60) )
ROM_LOAD16_BYTE( "4.ic5", 0x40000, 0x20000, CRC(2464a83b) SHA1(00f5ac81bc33148daafeab757647b63894e0e0ca) )
ROM_LOAD16_BYTE( "2.ic4", 0x40001, 0x20000, CRC(b47bbcd5) SHA1(811bd4bc8fb662abf4734ab51e24c863d5cc3df3) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "8.17k", 0x00000, 0x10000, CRC(0aeab61e) SHA1(165e0ad58542b65383fef714578da21f62df7b74) )
ROM_REGION( 0x10000, REGION_CPU3, 0 )
ROM_LOAD( "i8751.bin", 0x00000, 0x1000, CRC(64a0d225) SHA1(ccc5c33c0c412bf9e3a4f7de5e39b042e00c41dd) )
ROM_REGION( 0x08000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "7.11c", 0x00000, 0x08000, CRC(1809e79f) SHA1(730547771f803857acb552a84a8bc21bd3bda33f) )
ROM_REGION( 0x30000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "5.13f", 0x00000, 0x20000, CRC(d440a29f) SHA1(9e6ea7c9903e5e3e8e10ac7680c6120e1aa27250) )
ROM_LOAD( "6.15f", 0x20000, 0x10000, CRC(27469a76) SHA1(ebf2c60e1f70a589680c05adf10771ac2097b9d0) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE )
ROM_LOAD( "12.8a", 0x00000, 0x10000, CRC(a5694ea9) SHA1(ea94174495b3a65b3797932074a94df3b55fa0a2) )
ROM_LOAD( "11.6a", 0x10000, 0x10000, CRC(10b74e2c) SHA1(e3ec68726e7f277dc2043424f2e4d863eb01b3dc) )
ROM_REGION( 0x40000, REGION_GFX4, ROMREGION_DISPOSE )
ROM_LOAD16_BYTE( "9.8d", 0x00000, 0x20000, CRC(fe67800e) SHA1(0d3c4c3cb185270260fa691a97cddf082d6a056e) )
ROM_LOAD16_BYTE( "10.9d", 0x00001, 0x20000, CRC(dcb828c4) SHA1(607bc86580a6fe6e15e91131532b0eecd8b7a0cb) )
ROM_REGION( 0x0100, REGION_PROMS, 0 )
ROM_LOAD( "tf.13h", 0x0000, 0x0100, CRC(81244757) SHA1(6324f63e571f0f7a0bb9eb97f9994809db79493f) )
ROM_END
DRIVER_INIT( terraf )
{
@@ -1288,6 +1602,12 @@ DRIVER_INIT( armedf )
armedf_setgfxtype(1);
}
DRIVER_INIT( bigfghtr )
{
armedf_setgfxtype(1);
i8051_set_movx_handlers(2, bigfghtr_mcu_movx_r, bigfghtr_mcu_movx_w);
}
DRIVER_INIT( kodure )
{
data16_t *ROM = (data16_t *)memory_region(REGION_CPU1);
@@ -1341,3 +1661,5 @@ GAMEX( 1987, terrafu, terraf, terraf, terraf, terrafu, ROT0, "Nichibutsu
GAMEX( 1987, kodure, 0, kodure, kodure, kodure, ROT0, "Nichibutsu", "Kodure Ookami (Japan)", GAME_IMPERFECT_GRAPHICS | GAME_UNEMULATED_PROTECTION )
GAMEX( 1988, cclimbr2, 0, cclimbr2, cclimbr2, cclimbr2, ROT0, "Nichibutsu", "Crazy Climber 2 (Japan)", GAME_IMPERFECT_GRAPHICS )
GAMEX( 1988, armedf, 0, armedf, armedf, armedf, ROT270, "Nichibutsu", "Armed Formation", GAME_IMPERFECT_GRAPHICS )
GAMEX( 1989, skyrobo, 0, bigfghtr, bigfghtr, bigfghtr, ROT0, "Nichibutsu", "Sky Robo", GAME_IMPERFECT_GRAPHICS )
GAMEX( 1989, bigfghtr, skyrobo,bigfghtr, bigfghtr, bigfghtr, ROT0, "Nichibutsu", "Tatakae! Big Fighter (Japan)", GAME_IMPERFECT_GRAPHICS )
src/drivers/asteroid.c
+3 -1
View File
@@ -650,7 +650,9 @@ INPUT_PORTS_START( llander1 )
/* The next one is a potentiometer */
PORT_START /* IN3 */
PORT_ANALOGX( 0xff, 0x00, IPT_PADDLE|IPF_REVERSE, 100, 10, 0, 255, KEYCODE_UP, KEYCODE_DOWN, JOYCODE_1_UP, JOYCODE_1_DOWN )
//PORT_ANALOGX( 0xff, 0x00, IPT_PADDLE_V|IPF_REVERSE, 100, 10, 0, 255, KEYCODE_UP, KEYCODE_DOWN, JOYCODE_1_UP, JOYCODE_1_DOWN )
PORT_ANALOG( 0xff, 0x00, IPT_PADDLE_V| IPF_REVERSE , 100, 10, 0, 255 )
INPUT_PORTS_END
src/drivers/astrocde.c
+8 -4
View File
@@ -63,6 +63,7 @@ OUT:
****************************************************************************/
#include "driver.h"
#include "state.h"
#include "vidhrdw/generic.h"
extern unsigned char *wow_videoram;
@@ -155,8 +156,8 @@ static WRITE_HANDLER( seawolf2_sound_2_w ) /* Port 41 */
sample_set_volume(9, (data & 0x80) ? 100 : 0);
/* dive panning controlled by low 3 bits */
sample_set_volume(2, (float)(~data & 0x07) / 70);
sample_set_volume(7, (float)(data & 0x07) / 70);
sample_set_volume(2, (~data & 0x07) * 100 / 7);
sample_set_volume(7, (data & 0x07) * 100 / 7);
if (rising_bits & 0x08)
{
@@ -663,14 +664,14 @@ static struct astrocade_interface astrocade_2chip_interface =
{
2, /* Number of chips */
1789773, /* Clock speed */
{255,255} /* Volume */
{25,25} /* Volume */
};
static struct astrocade_interface astrocade_1chip_interface =
{
1, /* Number of chips */
1789773, /* Clock speed */
{255} /* Volume */
{25} /* Volume */
};
static struct CustomSound_interface gorf_custom_interface =
@@ -980,6 +981,9 @@ ROM_END
static DRIVER_INIT( seawolf2 )
{
state_save_register_UINT8("seawolf2", 0, "port_1_last", &port_1_last, 1);
state_save_register_UINT8("seawolf2", 0, "port_2_last", &port_2_last, 1);
install_port_read_handler(0, 0x10, 0x10, seawolf2_controller2_r);
install_port_read_handler(0, 0x11, 0x11, seawolf2_controller1_r);
}
src/drivers/atarigx2.c
+1 -1
View File
@@ -1146,7 +1146,7 @@ static READ32_HANDLER( atarigx2_protection_r )
if (lookup_table[i][0] == 0xffffffff)
{
if (last_write_offset*2 >= 0x700 && last_write_offset*2 < 0x720)
result = rand() << 16;
result = mame_rand_int() << 16;
else
result = 0xffff << 16;
log_cb(RETRO_LOG_DEBUG, LOGPRE "%06X:Unhandled protection R@%04X = %04X\n", activecpu_get_previouspc(), offset, result);
src/drivers/battlera.c
+13 -4
View File
@@ -23,6 +23,7 @@
#include "driver.h"
#include "vidhrdw/generic.h"
#include "cpu/h6280/h6280.h"
#include "state.h"
VIDEO_UPDATE( battlera );
VIDEO_START( battlera );
@@ -107,11 +108,10 @@ static WRITE_HANDLER( YM2203_w )
}
static int msm5205next;
static int toggle;
static void battlera_adpcm_int(int data)
{
static int toggle;
MSM5205_data_w(0,msm5205next >> 4);
msm5205next<<=4;
@@ -368,5 +368,14 @@ ROM_END
/******************************************************************************/
GAMEX( 1988, battlera, 0, battlera, battlera, 0, ROT0, "Data East Corporation", "Battle Rangers (World)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
GAMEX( 1988, bldwolf, battlera, battlera, battlera, 0, ROT0, "Data East USA", "Bloody Wolf (US)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
static DRIVER_INIT( battlera )
{
state_save_register_int("battlera", 0, "control_port_select", &control_port_select);
state_save_register_int("battlera", 0, "msm5205next", &msm5205next);
state_save_register_int("battlera", 0, "adpcm_toggle", &toggle);
}
/******************************************************************************/
GAMEX( 1988, battlera, 0, battlera, battlera, battlera, ROT0, "Data East Corporation", "Battle Rangers (World)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
GAMEX( 1988, bldwolf, battlera, battlera, battlera, battlera, ROT0, "Data East USA", "Bloody Wolf (US)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
src/drivers/blmbycar.c
+1 -1
View File
@@ -86,7 +86,7 @@ static WRITE16_HANDLER( blmbycar_pot_wheel_shift_w )
static READ16_HANDLER( blmbycar_pot_wheel_r )
{
return ((pot_wheel & 0x80) ? 0x04 : 0) |
(rand() & 0x08);
(mame_rand_int() & 0x08);
}
src/drivers/bublbobl.c
+41 -1
View File
@@ -138,6 +138,7 @@ CPU 3
#include "driver.h"
#include "vidhrdw/generic.h"
#include "cpu/m6805/m6805.h"
#include "state.h"
static int ddr1, ddr2, ddr3, ddr4;
static int port1_in, port2_in, port3_in, port4_in;
@@ -170,6 +171,26 @@ WRITE_HANDLER( bublbobl_sh_nmi_disable_w );
WRITE_HANDLER( bublbobl_sh_nmi_enable_w );
void bublbobl_save_state(void);
/* save states: the M6801 ports here, the rest in machine/bublbobl_machine.c */
static void bublbobl_register_state(void)
{
bublbobl_save_state();
state_save_register_int("bublbobl", 0, "ddr1", &ddr1);
state_save_register_int("bublbobl", 0, "ddr2", &ddr2);
state_save_register_int("bublbobl", 0, "ddr3", &ddr3);
state_save_register_int("bublbobl", 0, "ddr4", &ddr4);
state_save_register_int("bublbobl", 0, "port1_in", &port1_in);
state_save_register_int("bublbobl", 0, "port2_in", &port2_in);
state_save_register_int("bublbobl", 0, "port3_in", &port3_in);
state_save_register_int("bublbobl", 0, "port4_in", &port4_in);
state_save_register_int("bublbobl", 0, "port1_out", &port1_out);
state_save_register_int("bublbobl", 0, "port2_out", &port2_out);
state_save_register_int("bublbobl", 0, "port3_out", &port3_out);
state_save_register_int("bublbobl", 0, "port4_out", &port4_out);
}
READ_HANDLER( bublbobl_mcu_ddr1_r )
{
return ddr1;
@@ -302,6 +323,24 @@ static unsigned char portA_in,portA_out,ddrA;
static unsigned char portB_in,portB_out,ddrB;
static unsigned char portC_in,portC_out,ddrC;
static void tokio_register_state(void)
{
bublbobl_save_state();
state_save_register_UINT8("tokio", 0, "from_main", &from_main, 1);
state_save_register_UINT8("tokio", 0, "from_mcu", &from_mcu, 1);
state_save_register_int ("tokio", 0, "mcu_sent", &mcu_sent);
state_save_register_int ("tokio", 0, "main_sent", &main_sent);
state_save_register_UINT8("tokio", 0, "portA_in", &portA_in, 1);
state_save_register_UINT8("tokio", 0, "portA_out", &portA_out, 1);
state_save_register_UINT8("tokio", 0, "ddrA", &ddrA, 1);
state_save_register_UINT8("tokio", 0, "portB_in", &portB_in, 1);
state_save_register_UINT8("tokio", 0, "portB_out", &portB_out, 1);
state_save_register_UINT8("tokio", 0, "ddrB", &ddrB, 1);
state_save_register_UINT8("tokio", 0, "portC_in", &portC_in, 1);
state_save_register_UINT8("tokio", 0, "portC_out", &portC_out, 1);
state_save_register_UINT8("tokio", 0, "ddrC", &ddrC, 1);
}
READ_HANDLER( tokio_68705_portA_r )
{
return (portA_out & ddrA) | (portA_in & ~ddrA);
@@ -1720,6 +1759,7 @@ static DRIVER_INIT( bublbobl )
memcpy(ROM+0x08000,ROM+0x10000,0x4000);
bublbobl_video_enable = 1;
bublbobl_register_state();
}
static DRIVER_INIT( boblbobl )
@@ -1745,7 +1785,7 @@ static DRIVER_INIT( tokio )
/* preemptively enable video, the bit is not mapped for this game and */
/* I don't know if it even has it. */
bublbobl_video_enable = 1;
bublbobl_video_enable = 1; tokio_register_state();
}
src/drivers/circus.c
+1 -1
View File
@@ -345,7 +345,7 @@ static INTERRUPT_GEN( ripcord_interrupt )
static struct DACinterface dac_interface =
{
1,
{ 255, 255 }
{ 25, 25 }
};
static MACHINE_DRIVER_START( circus )
src/drivers/cps2.c
+3 -4
View File
@@ -127,14 +127,13 @@ extern VIDEO_START( cps2 );
extern int scanline1;
extern int scanline2;
extern int scancalls;
extern int scancount;
void cps2_objram_latch(void);
void cps2_set_sprite_priorities(void);
static INTERRUPT_GEN( cps2_interrupt )
{
static int scancount;
/* 2 is vblank, 4 is some sort of scanline interrupt, 6 is both at the same time. */
if(scancount >= 261)
@@ -1390,9 +1389,9 @@ static int cps2turbo_music_start(int side, int tune)
return 0;
}
if (side)
sample_set_stereo_volume(1, 0, 255);
sample_set_stereo_volume(1, 0, 100);
else
sample_set_stereo_volume(0, 255, 0);
sample_set_stereo_volume(0, 100, 0);
return 1;
}
src/drivers/cv1k.c
+1503
View File
File diff suppressed because it is too large. Load diff
src/drivers/ddrible.c
+1 -1
View File
@@ -88,7 +88,7 @@ static WRITE_HANDLER( ddrible_coin_counter_w )
static READ_HANDLER( ddrible_vlm5030_busy_r )
{
return rand(); /* patch */
return mame_rand_int(); /* patch */
if (VLM5030_BSY()) return 1;
else return 0;
}
src/drivers/deco32.c
+2 -2
View File
@@ -263,7 +263,7 @@ static READ32_HANDLER( lockload_gun_mirror_r )
/*logerror("%08x:Read gun %d\n",activecpu_get_pc(),offset);*/
/*return ((rand()%0xffff)<<16) | rand()%0xffff;*/
if (offset) /* Mirror of player 1 and player 2 fire buttons */
return readinputport(5) | ((rand()%0xff)<<16);
return readinputport(5) | ((mame_rand_int()%0xff)<<16);
return readinputport(4) | readinputport(6) | (readinputport(6)<<16) | (readinputport(6)<<24); /*((rand()%0xff)<<16);*/
}
@@ -731,7 +731,7 @@ MEMORY_END
READ32_HANDLER( dragngun_unk_video_r)
{
return rand();
return mame_rand_int();
}
READ32_HANDLER( dragngun_gfxrom_r ) /* trampoline */
src/drivers/deco_mlc.c
+1 -1
View File
@@ -121,7 +121,7 @@ static READ32_HANDLER( avengrs_control_r )
static READ32_HANDLER(test2_r)
{
return rand();
return mame_rand_int();
}
static READ32_HANDLER(test3_r)
src/drivers/djboy.c
+1 -1
View File
@@ -953,7 +953,7 @@ static struct YM2203interface ym2203_interface =
{
1,
3000000, /* ? */
{ YM2203_VOL(0xff,0xff) }, /* gain,volume */
{ YM2203_VOL(25,25) }, /* gain,volume */
{ 0 }, /* port A read */
{ 0 }, /* port B read */
{ 0 }, /* port A write */
src/drivers/firetrk.c
+4 -4
View File
@@ -750,7 +750,7 @@ INPUT_PORTS_START( firetrk )
PORT_START
PORT_BITX(0x01, IP_ACTIVE_HIGH, IPT_BUTTON2 | IPF_PLAYER1, "Horn", IP_KEY_DEFAULT, IP_JOY_DEFAULT)
PORT_START /* 8 */
PORT_ADJUSTER( 85, "Motor Frequency" )
PORT_ADJUSTER( 80, "Motor Frequency" )
INPUT_PORTS_END
@@ -816,7 +816,7 @@ INPUT_PORTS_START( superbug )
PORT_BITX(0x04, IP_ACTIVE_HIGH, IPT_BUTTON4, "Gear 3", KEYCODE_C, IP_JOY_DEFAULT )
PORT_BITX(0x08, IP_ACTIVE_HIGH, IPT_BUTTON5, "Gear 4", KEYCODE_V, IP_JOY_DEFAULT )
PORT_START /* 8 */
PORT_ADJUSTER( 85, "Motor Frequency" )
PORT_ADJUSTER( 80, "Motor Frequency" )
INPUT_PORTS_END
@@ -893,10 +893,10 @@ INPUT_PORTS_START( montecar )
PORT_BITX(0x04, IP_ACTIVE_HIGH, IPT_BUTTON4, "Gear 3", KEYCODE_C, IP_JOY_DEFAULT )
PORT_BITX(0x08, IP_ACTIVE_HIGH, IPT_BUTTON5, "Gear 4", KEYCODE_V, IP_JOY_DEFAULT )
PORT_START /* 8 */
PORT_ADJUSTER( 85, "Motor Frequency" )
PORT_ADJUSTER( 80, "Motor Frequency" )
PORT_START /* 9 */
PORT_ADJUSTER( 80, "Motor Frequency" )
PORT_ADJUSTER( 75, "Drone Motor Frequency" )
INPUT_PORTS_END
src/drivers/fuukifg3.c
+262 -96
View File
@@ -21,8 +21,6 @@ Year + Game
--
Notes so far:
- Dips, need DIP sheet.
- Raster Effects are imperfect, bad frames when lots of new sprites.
- The scroll values are generally wrong when flip screen is on and rasters are often incorrect
@@ -88,6 +86,7 @@ FG-3J ROM-J 507KA0301P04 Rev:1.3
***************************************************************************/
#include "driver.h"
#include "state.h"
#include "vidhrdw/generic.h"
static int fuuki32_raster_enable = 1; /* Enabled by default */
@@ -320,101 +319,149 @@ PORT_END
***************************************************************************/
INPUT_PORTS_START( asurabld )
PORT_START /* IN0 - $800000.w/$800002.w*/
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_START1 )
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_START2 )
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_SERVICE1 )
PORT_BIT( 0xfe00, IP_ACTIVE_LOW, IPT_UNKNOWN )
/* inputs shared by Asura Blade and Asura Buster; the review build of
Asura Buster has a 4th button per player (P1 button 4 pauses the game) */
#define FUUKI32_INPUTS( button4 ) \
PORT_START /* IN0 - $800000.w/$800002.w*/ \
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 ) \
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 ) \
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_START1 ) \
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_START2 ) \
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_SERVICE1 ) \
PORT_BIT( 0xfe00, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
\
PORT_START /* IN1 - $810000.w/$810002.w*/ \
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_PLAYER1 ) \
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_PLAYER1 ) \
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_PLAYER1 ) \
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_PLAYER1 ) \
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1 ) \
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER1 ) \
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER1 ) \
PORT_BIT( 0x0080, IP_ACTIVE_LOW, button4 | IPF_PLAYER1 ) \
PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_PLAYER2 ) \
PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_PLAYER2 ) \
PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_PLAYER2 ) \
PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_PLAYER2 ) \
PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 ) \
PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2 ) \
PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER2 ) \
PORT_BIT( 0x8000, IP_ACTIVE_LOW, button4 | IPF_PLAYER2 )
PORT_START /* IN1 - $810000.w/$810002.w*/
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_PLAYER1 )
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_PLAYER1 )
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_PLAYER1 )
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_PLAYER1 )
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1 )
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER1 )
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER1 )
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_PLAYER2 )
PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_PLAYER2 )
PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_PLAYER2 )
PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_PLAYER2 )
PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 )
PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2 )
PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER2 )
PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START /* IN2 - $880000.w/$880002.w*/
PORT_SERVICE( 0x0001, 0x0001 )
PORT_DIPNAME( 0x0002, 0x0002, "Blood Colour" ) /* Any other censorship? (Tested in 3 locations)*/
PORT_DIPSETTING( 0x0002, "Red" )
/* DSW1 bits 0-1 and 4-7 (SW1:1,2 and SW1:5-8); bits 2-3 are the
"Demo Sounds & Music" switch, different in each game */
#define FUUKI32_DSW1_LOW \
PORT_START /* IN2 - $880000.w/$880002.w*/ \
PORT_SERVICE( 0x0001, 0x0001 ) /* SW1:1 */ \
PORT_DIPNAME( 0x0002, 0x0002, "Blood Colour" ) /* SW1:2 - Any other censorship? (Tested in 3 locations)*/ \
PORT_DIPSETTING( 0x0002, "Red" ) \
PORT_DIPSETTING( 0x0000, "Green" )
PORT_DIPNAME( 0x0004, 0x0004, DEF_STR( Unknown ) ) /* Tested @ 0917AC*/
PORT_DIPSETTING( 0x0004, DEF_STR( Off ) )
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
PORT_DIPNAME( 0x0008, 0x0008, DEF_STR( Unknown ) ) /* Tested @ 0917AC*/
PORT_DIPSETTING( 0x0008, DEF_STR( Off ) )
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
PORT_DIPNAME( 0x0030, 0x0030, "Timer" )
PORT_DIPSETTING( 0x0000, "Slow" )
PORT_DIPSETTING( 0x0030, "Medium" )
PORT_DIPSETTING( 0x0010, "Fast" )
PORT_DIPSETTING( 0x0020, "Very Fast" )
PORT_DIPNAME( 0x00c0, 0x0000, "Coinage Mode" )
PORT_DIPSETTING( 0x00c0, "Split" )
PORT_DIPSETTING( 0x0000, "Joint" )
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_START /* IN3 - $890000.w/$890002.w*/
PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Flip_Screen ) )
PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
PORT_DIPNAME( 0x000e, 0x0000, "Computer Level" ) /* See @ 0917CC*/
PORT_DIPSETTING( 0x0000, "0" )
PORT_DIPSETTING( 0x0008, "1" )
PORT_DIPSETTING( 0x0004, "2" )
PORT_DIPSETTING( 0x000c, "3" )
PORT_DIPSETTING( 0x000e, "4" )
PORT_DIPSETTING( 0x0002, "5" )
PORT_DIPSETTING( 0x000a, "6" )
PORT_DIPSETTING( 0x0006, "7" )
PORT_DIPNAME( 0x0030, 0x0010, "Damage" )
PORT_DIPSETTING( 0x0020, "Lowest" )
PORT_DIPSETTING( 0x0030, "Low" )
PORT_DIPSETTING( 0x0010, "Medium" )
PORT_DIPSETTING( 0x0000, "High" )
PORT_DIPNAME( 0x00c0, 0x0040, "Max Rounds" )
PORT_DIPSETTING( 0x0000, "1" )
PORT_DIPSETTING( 0x0040, "3" )
PORT_DIPSETTING( 0x0080, "5" )
PORT_DIPNAME( 0xf000, 0xf000, DEF_STR( Coin_A ) )
PORT_DIPSETTING( 0x8000, DEF_STR( 8C_1C ) )
PORT_DIPSETTING( 0x9000, DEF_STR( 7C_1C ) )
PORT_DIPSETTING( 0xa000, DEF_STR( 6C_1C ) )
PORT_DIPSETTING( 0xb000, DEF_STR( 5C_1C ) )
PORT_DIPSETTING( 0xc000, DEF_STR( 4C_1C ) )
PORT_DIPSETTING( 0xd000, DEF_STR( 3C_1C ) )
PORT_DIPSETTING( 0xe000, DEF_STR( 2C_1C ) )
PORT_DIPSETTING( 0xf000, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x0000, DEF_STR( Free_Play ) ) /* Set both for Free Play*/
PORT_DIPNAME( 0x0f00, 0x0f00, DEF_STR( Coin_B ) )
PORT_DIPSETTING( 0x0800, DEF_STR( 8C_1C ) )
PORT_DIPSETTING( 0x0900, DEF_STR( 7C_1C ) )
PORT_DIPSETTING( 0x0a00, DEF_STR( 6C_1C ) )
PORT_DIPSETTING( 0x0b00, DEF_STR( 5C_1C ) )
PORT_DIPSETTING( 0x0c00, DEF_STR( 4C_1C ) )
PORT_DIPSETTING( 0x0d00, DEF_STR( 3C_1C ) )
PORT_DIPSETTING( 0x0e00, DEF_STR( 2C_1C ) )
PORT_DIPSETTING( 0x0f00, DEF_STR( 1C_1C ) )
#define FUUKI32_DSW1_HIGH \
PORT_DIPNAME( 0x0030, 0x0030, "Timer" ) /* SW1:5,6 */ \
PORT_DIPSETTING( 0x0000, "Slow" ) \
PORT_DIPSETTING( 0x0030, "Medium" ) \
PORT_DIPSETTING( 0x0010, "Fast" ) \
PORT_DIPSETTING( 0x0020, "Very Fast" ) \
PORT_DIPNAME( 0x00c0, 0x0000, "Coinage Mode" ) /* SW1:7,8 */ \
PORT_DIPSETTING( 0x00c0, "Split" ) \
PORT_DIPSETTING( 0x0000, "Joint" ) \
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED ) /* SW2, not used by these games */
/* the coin settings $0000 and $7000 are not listed: $0000 is 1 coin 1 credit,
or Free Play when both Coin A and Coin B are set to it; $7000 is shown as
"Error" in the service mode and causes graphics issues */
#define FUUKI32_DSW2 \
PORT_START /* IN3 - $890000.w/$890002.w*/ \
PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Flip_Screen ) ) /* SW3:1 */ \
PORT_DIPSETTING( 0x0001, DEF_STR( Off ) ) \
PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) \
PORT_DIPNAME( 0x000e, 0x000e, "Difficulty" ) /* SW3:2,3,4 - AKA Computer Level, see @ 0917CC*/ \
PORT_DIPSETTING( 0x0000, "Easiest" ) /* Level 1 */ \
PORT_DIPSETTING( 0x0008, "Very Easy" ) /* Level 2 */ \
PORT_DIPSETTING( 0x0004, "Easier" ) /* Level 3 */ \
PORT_DIPSETTING( 0x000c, "Easy" ) /* Level 4 */ \
PORT_DIPSETTING( 0x000e, "Normal" ) /* Level 5 */ \
PORT_DIPSETTING( 0x0002, "Hard" ) /* Level 6 */ \
PORT_DIPSETTING( 0x000a, "Very Hard" ) /* Level 7 */ \
PORT_DIPSETTING( 0x0006, "Hardest" ) /* Level 8 */ \
PORT_DIPNAME( 0x0030, 0x0030, "Damage" ) /* SW3:5,6 */ \
PORT_DIPSETTING( 0x0020, "75%" ) \
PORT_DIPSETTING( 0x0030, "100%" ) \
PORT_DIPSETTING( 0x0010, "125%" ) \
PORT_DIPSETTING( 0x0000, "150%" ) \
PORT_DIPNAME( 0x00c0, 0x00c0, "Max Rounds" ) /* SW3:7,8 - $0040 is shown as "Error" in the service mode */ \
PORT_DIPSETTING( 0x0000, "1" ) \
PORT_DIPSETTING( 0x00c0, "3" ) \
PORT_DIPSETTING( 0x0080, "5" ) \
PORT_DIPNAME( 0xf000, 0xf000, DEF_STR( Coin_A ) ) /* SW4:1,2,3,4 - shown as Player 2 in the service mode */ \
PORT_DIPSETTING( 0x8000, DEF_STR( 8C_1C ) ) \
PORT_DIPSETTING( 0x9000, DEF_STR( 7C_1C ) ) \
PORT_DIPSETTING( 0xa000, DEF_STR( 6C_1C ) ) \
PORT_DIPSETTING( 0xb000, DEF_STR( 5C_1C ) ) \
PORT_DIPSETTING( 0xc000, DEF_STR( 4C_1C ) ) \
PORT_DIPSETTING( 0xd000, DEF_STR( 3C_1C ) ) \
PORT_DIPSETTING( 0xe000, DEF_STR( 2C_1C ) ) \
PORT_DIPSETTING( 0xf000, DEF_STR( 1C_1C ) ) \
PORT_DIPSETTING( 0x6000, DEF_STR( 1C_2C ) ) \
PORT_DIPSETTING( 0x5000, DEF_STR( 1C_3C ) ) \
PORT_DIPSETTING( 0x4000, DEF_STR( 1C_4C ) ) \
PORT_DIPSETTING( 0x3000, DEF_STR( 1C_5C ) ) \
PORT_DIPSETTING( 0x2000, "2C Start / 1C Continue" ) \
PORT_DIPSETTING( 0x0000, DEF_STR( Free_Play ) ) /* Set both for Free Play*/ \
PORT_DIPNAME( 0x0f00, 0x0f00, DEF_STR( Coin_B ) ) /* SW4:5,6,7,8 - shown as Player 1 in the service mode */ \
PORT_DIPSETTING( 0x0800, DEF_STR( 8C_1C ) ) \
PORT_DIPSETTING( 0x0900, DEF_STR( 7C_1C ) ) \
PORT_DIPSETTING( 0x0a00, DEF_STR( 6C_1C ) ) \
PORT_DIPSETTING( 0x0b00, DEF_STR( 5C_1C ) ) \
PORT_DIPSETTING( 0x0c00, DEF_STR( 4C_1C ) ) \
PORT_DIPSETTING( 0x0d00, DEF_STR( 3C_1C ) ) \
PORT_DIPSETTING( 0x0e00, DEF_STR( 2C_1C ) ) \
PORT_DIPSETTING( 0x0f00, DEF_STR( 1C_1C ) ) \
PORT_DIPSETTING( 0x0600, DEF_STR( 1C_2C ) ) \
PORT_DIPSETTING( 0x0500, DEF_STR( 1C_3C ) ) \
PORT_DIPSETTING( 0x0400, DEF_STR( 1C_4C ) ) \
PORT_DIPSETTING( 0x0300, DEF_STR( 1C_5C ) ) \
PORT_DIPSETTING( 0x0200, "2C Start / 1C Continue" ) \
PORT_DIPSETTING( 0x0000, DEF_STR( Free_Play ) ) /* Set both for Free Play*/
INPUT_PORTS_START( asurabld )
FUUKI32_INPUTS( IPT_UNKNOWN )
FUUKI32_DSW1_LOW
PORT_DIPNAME( 0x000c, 0x000c, "Demo Sounds & Music" ) /* SW1:3,4 - Tested @ 0917AC*/
PORT_DIPSETTING( 0x000c, "Both On" )
PORT_DIPSETTING( 0x0008, "Music Off" )
PORT_DIPSETTING( 0x0004, "Both Off" ) /* $0000 is the same */
FUUKI32_DSW1_HIGH
FUUKI32_DSW2
INPUT_PORTS_END
INPUT_PORTS_START( asurabus )
FUUKI32_INPUTS( IPT_UNKNOWN )
FUUKI32_DSW1_LOW
PORT_DIPNAME( 0x000c, 0x000c, "Demo Sounds & Music" ) /* SW1:3,4 */
PORT_DIPSETTING( 0x000c, "Both On" )
PORT_DIPSETTING( 0x0008, "Sounds Off" )
PORT_DIPSETTING( 0x0004, "Music Off" )
PORT_DIPSETTING( 0x0000, "Both Off" )
FUUKI32_DSW1_HIGH
FUUKI32_DSW2
INPUT_PORTS_END
INPUT_PORTS_START( asurabusa )
FUUKI32_INPUTS( IPT_BUTTON4 )
FUUKI32_DSW1_LOW
PORT_DIPNAME( 0x000c, 0x000c, "Demo Sounds & Music" ) /* SW1:3,4 */
PORT_DIPSETTING( 0x000c, "Both On" )
PORT_DIPSETTING( 0x0008, "Sounds Off" )
PORT_DIPSETTING( 0x0004, "Music Off" )
PORT_DIPSETTING( 0x0000, "Both Off" )
FUUKI32_DSW1_HIGH
FUUKI32_DSW2
INPUT_PORTS_END
@@ -524,7 +571,7 @@ static struct YMF278B_interface ymf278b_interface =
static struct YMF262interface ymf262_interface =
{
1, /* 1 chip */
14318180, /* X1 ? */
14260547, /* the FM part of the YMF278B: 33.8688MHz / 2.375, as in MAME 0.143u3 */
{ YAC512_VOL(50,MIXER_PAN_LEFT,50,MIXER_PAN_RIGHT) }, /* channels A and B */
{ YAC512_VOL(50,MIXER_PAN_LEFT,50,MIXER_PAN_RIGHT) }, /* channels C and D */
{ irqhandler }, /* irq */
@@ -607,11 +654,50 @@ ROM_END
/***************************************************************************
Asura Buster - Eternal Warriors (Japan)
Asura Buster - Eternal Warriors
Fuuki, 2000 Consists of a FG-3J MAIN-J mainboard & FG-3J ROM-J combo
The sets only differ in the program ROMs. "asurabusjr" is a review build
for the ARCADIA magazine: P1 button 4 pauses the game.
***************************************************************************/
ROM_START( asurabus )
ROM_REGION( 0x200000, REGION_CPU1, 0 ) /* M68020 */
ROM_LOAD32_BYTE( "uspgm3.u1", 0x000000, 0x80000, CRC(e152cec9) SHA1(af1d93bdabc6732c0ff53972826d67a3753ef785) ) /* hand written labels */
ROM_LOAD32_BYTE( "uspgm2.u2", 0x000001, 0x80000, CRC(b19787db) SHA1(3d6757f38f297c1ee89003173567319b5dae8000) )
ROM_LOAD32_BYTE( "uspgm1.u3", 0x000002, 0x80000, CRC(6588e51a) SHA1(9ab978c80d8ece447697557c8000be95760306f3) )
ROM_LOAD32_BYTE( "uspgm0.u4", 0x000003, 0x80000, CRC(981e6ff1) SHA1(088d26a3cbd2361ffc756c3da8a67b94ae7bbd65) )
ROM_REGION( 0x090000, REGION_CPU2, 0 ) /* Z80 */
ROM_LOAD( "srom.u7", 0x00000, 0x80000, CRC(368da389) SHA1(1423b709da40bf3033c9032c4bd07658f1a969de) )
ROM_RELOAD( 0x10000, 0x80000) /* for banks */
ROM_REGION( 0x2000000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "sp01.u13", 0x0000000, 0x400000, CRC(5edea463) SHA1(22a780912f060bae0c9a403a7bfd4d27f25b76e3) )
ROM_LOAD( "sp23.u14", 0x0400000, 0x400000, CRC(91b1b0de) SHA1(341367966559ef2027415b673eb0db704680c81f) )
ROM_LOAD( "sp45.u15", 0x0800000, 0x400000, CRC(96c69aac) SHA1(cf053523026651427f884b9dd7c095af362dd24e) )
ROM_LOAD( "sp67.u16", 0x0c00000, 0x400000, CRC(7c3d83bf) SHA1(7188dd923c6c7eb6aee3323e7ab54aa240c35ea3) )
ROM_LOAD( "sp89.u17", 0x1000000, 0x400000, CRC(cb1e14f8) SHA1(941cea1887d7ceb52222adcf1d6913969e6163aa) )
ROM_LOAD( "spab.u18", 0x1400000, 0x400000, CRC(e5a4608d) SHA1(b8e39f53e0b7ad1e16ae9c3726597776b404be1c) )
ROM_LOAD( "spcd.u19", 0x1800000, 0x400000, CRC(99bfbe32) SHA1(926a8afc4a175874f22f53300e76f59331d3b9ba) )
ROM_LOAD( "spef.u20", 0x1c00000, 0x400000, CRC(c9c799cc) SHA1(01373316700d8688deeea2e9e8f831d5f86c7f17) )
ROM_REGION( 0x0800000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "bg1012.u22", 0x0000000, 0x400000, CRC(e3fb9af0) SHA1(11900cc2873337692f66fb4f1eb9c574e5a967de) )
ROM_LOAD( "bg1113.u23", 0x0400000, 0x400000, CRC(5f8657e6) SHA1(7c2854dc5d2d4efe55bda01e329da051350e0031) )
ROM_REGION( 0x0800000, REGION_GFX3, ROMREGION_DISPOSE )
ROM_LOAD( "bg2022.u25", 0x0000000, 0x400000, CRC(f46eda52) SHA1(46530016b32a164bd76c4f53e7b53b2beb28db06) )
ROM_LOAD( "bg2123.u24", 0x0400000, 0x400000, CRC(c4ebb86b) SHA1(a7093e6e02b64566d277cbbd5fa90cd430e7c8a0) )
ROM_REGION( 0x200000, REGION_GFX4, ROMREGION_DISPOSE ) /* background tiles*/
ROM_LOAD( "map.u5", 0x00000, 0x200000, CRC(bd179dc5) SHA1(ce3fcac573b14fd5365eb5dcec3257e439d2c129) )
ROM_REGION( 0x400000, REGION_SOUND1, 0 ) /* OPL4 samples*/
ROM_LOAD( "opm.u6", 0x00000, 0x400000, CRC(31b05be4) SHA1(d0f4f387f84a74591224b0f42b7f5c538a3dc498) )
ROM_END
ROM_START( asurabusj )
ROM_REGION( 0x200000, REGION_CPU1, 0 ) /* M68020 */
ROM_LOAD32_BYTE( "pgm3.u1", 0x000000, 0x80000, CRC(2c6b5271) SHA1(188371f1f003823ac719e962e048719d76696b2f) )
ROM_LOAD32_BYTE( "pgm2.u2", 0x000001, 0x80000, CRC(8f8694ec) SHA1(3334df4aecc5ab2f8914ef6748c027a99b39ce26) )
@@ -647,6 +733,78 @@ ROM_START( asurabus )
ROM_LOAD( "opm.u6", 0x00000, 0x400000, CRC(31b05be4) SHA1(d0f4f387f84a74591224b0f42b7f5c538a3dc498) )
ROM_END
ROM_START( asurabusja )
ROM_REGION( 0x200000, REGION_CPU1, 0 ) /* M68020 */
ROM_LOAD32_BYTE( "pgm3_583a.u1", 0x000000, 0x80000, CRC(46ab3b0e) SHA1(2d6a57352891a484fe11cda9addbff5b3940c17c) ) /* hand written labels with checksums */
ROM_LOAD32_BYTE( "pgm2_0ff4.u2", 0x000001, 0x80000, CRC(fa7aa289) SHA1(6f82371274c45f889a19a4fdd859015fb6ea249a) )
ROM_LOAD32_BYTE( "pgm1_bac7.u3", 0x000002, 0x80000, CRC(67364e19) SHA1(959b896b201f103ef9189b537139c89bfc7144ea) )
ROM_LOAD32_BYTE( "pgm0_193a.u4", 0x000003, 0x80000, CRC(94d39c64) SHA1(95ca2aa3e19e64bed7add3170653fa3364530fde) )
ROM_REGION( 0x090000, REGION_CPU2, 0 ) /* Z80 */
ROM_LOAD( "srom.u7", 0x00000, 0x80000, CRC(368da389) SHA1(1423b709da40bf3033c9032c4bd07658f1a969de) )
ROM_RELOAD( 0x10000, 0x80000) /* for banks */
ROM_REGION( 0x2000000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "sp01.u13", 0x0000000, 0x400000, CRC(5edea463) SHA1(22a780912f060bae0c9a403a7bfd4d27f25b76e3) )
ROM_LOAD( "sp23.u14", 0x0400000, 0x400000, CRC(91b1b0de) SHA1(341367966559ef2027415b673eb0db704680c81f) )
ROM_LOAD( "sp45.u15", 0x0800000, 0x400000, CRC(96c69aac) SHA1(cf053523026651427f884b9dd7c095af362dd24e) )
ROM_LOAD( "sp67.u16", 0x0c00000, 0x400000, CRC(7c3d83bf) SHA1(7188dd923c6c7eb6aee3323e7ab54aa240c35ea3) )
ROM_LOAD( "sp89.u17", 0x1000000, 0x400000, CRC(cb1e14f8) SHA1(941cea1887d7ceb52222adcf1d6913969e6163aa) )
ROM_LOAD( "spab.u18", 0x1400000, 0x400000, CRC(e5a4608d) SHA1(b8e39f53e0b7ad1e16ae9c3726597776b404be1c) )
ROM_LOAD( "spcd.u19", 0x1800000, 0x400000, CRC(99bfbe32) SHA1(926a8afc4a175874f22f53300e76f59331d3b9ba) )
ROM_LOAD( "spef.u20", 0x1c00000, 0x400000, CRC(c9c799cc) SHA1(01373316700d8688deeea2e9e8f831d5f86c7f17) )
ROM_REGION( 0x0800000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "bg1012.u22", 0x0000000, 0x400000, CRC(e3fb9af0) SHA1(11900cc2873337692f66fb4f1eb9c574e5a967de) )
ROM_LOAD( "bg1113.u23", 0x0400000, 0x400000, CRC(5f8657e6) SHA1(7c2854dc5d2d4efe55bda01e329da051350e0031) )
ROM_REGION( 0x0800000, REGION_GFX3, ROMREGION_DISPOSE )
ROM_LOAD( "bg2022.u25", 0x0000000, 0x400000, CRC(f46eda52) SHA1(46530016b32a164bd76c4f53e7b53b2beb28db06) )
ROM_LOAD( "bg2123.u24", 0x0400000, 0x400000, CRC(c4ebb86b) SHA1(a7093e6e02b64566d277cbbd5fa90cd430e7c8a0) )
ROM_REGION( 0x200000, REGION_GFX4, ROMREGION_DISPOSE ) /* background tiles*/
ROM_LOAD( "map.u5", 0x00000, 0x200000, CRC(bd179dc5) SHA1(ce3fcac573b14fd5365eb5dcec3257e439d2c129) )
ROM_REGION( 0x400000, REGION_SOUND1, 0 ) /* OPL4 samples*/
ROM_LOAD( "opm.u6", 0x00000, 0x400000, CRC(31b05be4) SHA1(d0f4f387f84a74591224b0f42b7f5c538a3dc498) )
ROM_END
ROM_START( asurabusjr ) /* ARCADIA review build */
ROM_REGION( 0x200000, REGION_CPU1, 0 ) /* M68020 */
ROM_LOAD32_BYTE( "24-31.pgm3", 0x000000, 0x80000, CRC(cfcb9c75) SHA1(51e325d5e60d5bb058429f04a5170dcc17986b7d) )
ROM_LOAD32_BYTE( "16-23.pgm2", 0x000001, 0x80000, CRC(e4d07738) SHA1(c6c949c5b0cbc129917bb8c93707539adabbd336) )
ROM_LOAD32_BYTE( "8-15.pgm1", 0x000002, 0x80000, CRC(1dd67fe7) SHA1(3fd340ccd4a306783ba0ccd3343ae505c9de3a73) )
ROM_LOAD32_BYTE( "0-7.pgm0", 0x000003, 0x80000, CRC(3af08de3) SHA1(1ecc69804693cab6c2c36120acfc6ced094a16e4) )
ROM_REGION( 0x090000, REGION_CPU2, 0 ) /* Z80 */
ROM_LOAD( "srom.u7", 0x00000, 0x80000, CRC(368da389) SHA1(1423b709da40bf3033c9032c4bd07658f1a969de) )
ROM_RELOAD( 0x10000, 0x80000) /* for banks */
ROM_REGION( 0x2000000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "sp01.u13", 0x0000000, 0x400000, CRC(5edea463) SHA1(22a780912f060bae0c9a403a7bfd4d27f25b76e3) )
ROM_LOAD( "sp23.u14", 0x0400000, 0x400000, CRC(91b1b0de) SHA1(341367966559ef2027415b673eb0db704680c81f) )
ROM_LOAD( "sp45.u15", 0x0800000, 0x400000, CRC(96c69aac) SHA1(cf053523026651427f884b9dd7c095af362dd24e) )
ROM_LOAD( "sp67.u16", 0x0c00000, 0x400000, CRC(7c3d83bf) SHA1(7188dd923c6c7eb6aee3323e7ab54aa240c35ea3) )
ROM_LOAD( "sp89.u17", 0x1000000, 0x400000, CRC(cb1e14f8) SHA1(941cea1887d7ceb52222adcf1d6913969e6163aa) )
ROM_LOAD( "spab.u18", 0x1400000, 0x400000, CRC(e5a4608d) SHA1(b8e39f53e0b7ad1e16ae9c3726597776b404be1c) )
ROM_LOAD( "spcd.u19", 0x1800000, 0x400000, CRC(99bfbe32) SHA1(926a8afc4a175874f22f53300e76f59331d3b9ba) )
ROM_LOAD( "spef.u20", 0x1c00000, 0x400000, CRC(c9c799cc) SHA1(01373316700d8688deeea2e9e8f831d5f86c7f17) )
ROM_REGION( 0x0800000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "bg1012.u22", 0x0000000, 0x400000, CRC(e3fb9af0) SHA1(11900cc2873337692f66fb4f1eb9c574e5a967de) )
ROM_LOAD( "bg1113.u23", 0x0400000, 0x400000, CRC(5f8657e6) SHA1(7c2854dc5d2d4efe55bda01e329da051350e0031) )
ROM_REGION( 0x0800000, REGION_GFX3, ROMREGION_DISPOSE )
ROM_LOAD( "bg2022.u25", 0x0000000, 0x400000, CRC(f46eda52) SHA1(46530016b32a164bd76c4f53e7b53b2beb28db06) )
ROM_LOAD( "bg2123.u24", 0x0400000, 0x400000, CRC(c4ebb86b) SHA1(a7093e6e02b64566d277cbbd5fa90cd430e7c8a0) )
ROM_REGION( 0x200000, REGION_GFX4, ROMREGION_DISPOSE ) /* background tiles*/
ROM_LOAD( "map.u5", 0x00000, 0x200000, CRC(bd179dc5) SHA1(ce3fcac573b14fd5365eb5dcec3257e439d2c129) )
ROM_REGION( 0x400000, REGION_SOUND1, 0 ) /* OPL4 samples*/
ROM_LOAD( "opm.u6", 0x00000, 0x400000, CRC(31b05be4) SHA1(d0f4f387f84a74591224b0f42b7f5c538a3dc498) )
ROM_END
/***************************************************************************
@@ -657,5 +815,13 @@ ROM_END
***************************************************************************/
GAMEX( 1998, asurabld, 0, fuuki32, asurabld, 0, ROT0, "Fuuki", "Asura Blade - Sword of Dynasty", GAME_IMPERFECT_GRAPHICS )
GAMEX( 2000, asurabus, 0, fuuki32, asurabld, 0, ROT0, "Fuuki", "Asura Buster - Eternal Warriors", GAME_IMPERFECT_GRAPHICS|GAME_IMPERFECT_SOUND )
static DRIVER_INIT( fuuki32 )
{
state_save_register_UINT8("fuuki32", 0, "shared_ram", fuuki32_shared_ram, sizeof(fuuki32_shared_ram));
}
GAMEX( 1998, asurabld, 0, fuuki32, asurabld, fuuki32, ROT0, "Fuuki", "Asura Blade - Sword of Dynasty (Japan)", GAME_IMPERFECT_GRAPHICS )
GAMEX( 2001, asurabus, 0, fuuki32, asurabus, fuuki32, ROT0, "Fuuki", "Asura Buster - Eternal Warriors (USA)", GAME_IMPERFECT_GRAPHICS|GAME_IMPERFECT_SOUND )
GAMEX( 2000, asurabusj, asurabus, fuuki32, asurabus, fuuki32, ROT0, "Fuuki", "Asura Buster - Eternal Warriors (Japan, set 1)", GAME_IMPERFECT_GRAPHICS|GAME_IMPERFECT_SOUND )
GAMEX( 2000, asurabusja, asurabus, fuuki32, asurabus, fuuki32, ROT0, "Fuuki", "Asura Buster - Eternal Warriors (Japan, set 2)", GAME_IMPERFECT_GRAPHICS|GAME_IMPERFECT_SOUND )
GAMEX( 2000, asurabusjr, asurabus, fuuki32, asurabusa, fuuki32, ROT0, "Fuuki", "Asura Buster - Eternal Warriors (Japan) (ARCADIA review build)", GAME_IMPERFECT_GRAPHICS|GAME_IMPERFECT_SOUND )
src/drivers/gng.c
+538
View File
@@ -1233,6 +1233,525 @@ ROM_START( gngmaidentenh )
ROM_LOAD( "mm17maiden.4n", 0x000000, 0x004000, CRC(9fb0faaf) SHA1(903b926b0c22879721fdc8a551c1512dd0773802) )
ROM_END
ROM_START( gngprincess )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "mm_c_princess_04", 0x04000, 0x004000, CRC(3b6d9dcf) )
ROM_LOAD( "mm_c_princess_03", 0x08000, 0x008000, CRC(134db50c) )
ROM_LOAD( "mm_c_princess_05", 0x10000, 0x008000, CRC(d7e126e2) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "gg2.bin", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "gg1princess.bin", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "gg11.bin", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "gg10.bin", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "gg9.bin", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "gg8.bin", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "gg7.bin", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "gg6.bin", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "gg17princess.bin", 0x00000, 0x004000, CRC(e2043162) )
ROM_LOAD( "gg16princess.bin", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "gg15princess.bin", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "gg14princess.bin", 0x0c000, 0x004000, CRC(19847a61) )
ROM_LOAD( "gg13princess.bin", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "gg12princess.bin", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( gngprincessa )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "mjg_04princess.10n", 0x04000, 0x004000, CRC(1299e52b) )
ROM_LOAD( "mjg_03princess.8n", 0x08000, 0x008000, CRC(be9d1e56) )
ROM_LOAD( "mjg_05princess.12n", 0x10000, 0x008000, CRC(f5eb84e6) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "capsom_m5m23256p_p_62410p_mjg_02.14h", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "capsom_m5m23256p_p_616105_mjg_01p_princess.11e", 0x00000, 0x004000, CRC(4ef3637e) )
ROM_IGNORE( 0x004000 )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "capsom_m5m23256p_p_616105_mmg_08.3e", 0x00000, 0x008000, CRC(c09a716f) )
ROM_LOAD( "capsom_m5m23256p_p_61710z_mmg_07.3c", 0x08000, 0x008000, CRC(0b92b129) )
ROM_LOAD( "capsom_m5m23256p_p_616105_mmg_06.3b", 0x10000, 0x008000, CRC(830176af) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "capsom_m5m23256p_p_61710g_mjg_12p_princess.4n", 0x00000, 0x008000, CRC(f23401c4) )
ROM_LOAD( "capsom_m5m23256p_p_620108_mjg_11p_princess.3n", 0x08000, 0x008000, CRC(1ab10e35) )
ROM_LOAD( "capsom_m5m23256p_p_62410p_mjg_10p_princess.4l", 0x10000, 0x008000, CRC(3801cb66) )
ROM_LOAD( "capsom_m5m23256p_p_61710g_mjg_09p_princess.3l", 0x18000, 0x008000, CRC(e9edb4bc) )
ROM_END
ROM_START( gngprincessaenh )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "mjg_04princess.10n", 0x04000, 0x004000, CRC(1299e52b) )
ROM_LOAD( "mjg_03princess.8n", 0x08000, 0x008000, CRC(81cb0d2a) )
ROM_LOAD( "mjg_05princess.12n", 0x10000, 0x008000, CRC(2caa03e3) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "capsom_m5m23256p_p_62410p_mjg_02.14h", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "capsom_m5m23256p_p_616105_mjg_01p_princess.11e", 0x00000, 0x004000, CRC(4ef3637e) )
ROM_IGNORE( 0x004000 )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "capsom_m5m23256p_p_616105_mmg_08.3e", 0x00000, 0x008000, CRC(c09a716f) )
ROM_LOAD( "capsom_m5m23256p_p_61710z_mmg_07.3c", 0x08000, 0x008000, CRC(0b92b129) )
ROM_LOAD( "capsom_m5m23256p_p_616105_mmg_06.3b", 0x10000, 0x008000, CRC(830176af) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "capsom_m5m23256p_p_61710g_mjg_12p_princess.4n", 0x00000, 0x008000, CRC(f23401c4) )
ROM_LOAD( "capsom_m5m23256p_p_620108_mjg_11p_princess.3n", 0x08000, 0x008000, CRC(1ab10e35) )
ROM_LOAD( "capsom_m5m23256p_p_62410p_mjg_10p_princess.4l", 0x10000, 0x008000, CRC(3801cb66) )
ROM_LOAD( "capsom_m5m23256p_p_61710g_mjg_09p_princess.3l", 0x18000, 0x008000, CRC(e9edb4bc) )
ROM_END
ROM_START( gngprincessb )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "gg4princess.bin", 0x04000, 0x004000, CRC(1299e52b) )
ROM_LOAD( "gg3princess.bin", 0x08000, 0x008000, CRC(be9d1e56) )
ROM_LOAD( "gg5princess.bin", 0x10000, 0x008000, CRC(f5eb84e6) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "gg2.bin", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "gg1princess.bin", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "gg11.bin", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "gg10.bin", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "gg9.bin", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "gg8.bin", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "gg7.bin", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "gg6.bin", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "gg17princess.bin", 0x00000, 0x004000, CRC(e2043162) )
ROM_LOAD( "gg16princess.bin", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "gg15princess.bin", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "gg14princess.bin", 0x0c000, 0x004000, CRC(19847a61) )
ROM_LOAD( "gg13princess.bin", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "gg12princess.bin", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( gngprincessbenh )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "gg4princess.bin", 0x04000, 0x004000, CRC(1299e52b) )
ROM_LOAD( "gg3princess.bin", 0x08000, 0x008000, CRC(81cb0d2a) )
ROM_LOAD( "gg5princess.bin", 0x10000, 0x008000, CRC(2caa03e3) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "gg2.bin", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "gg1princess.bin", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "gg11.bin", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "gg10.bin", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "gg9.bin", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "gg8.bin", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "gg7.bin", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "gg6.bin", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "gg17princess.bin", 0x00000, 0x004000, CRC(e2043162) )
ROM_LOAD( "gg16princess.bin", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "gg15princess.bin", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "gg14princess.bin", 0x0c000, 0x004000, CRC(19847a61) )
ROM_LOAD( "gg13princess.bin", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "gg12princess.bin", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( gngprincessc )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "gngprincess.n10", 0x04000, 0x004000, CRC(36e043ad) )
ROM_LOAD( "gng.n9", 0x08000, 0x004000, CRC(b6b91cfb) )
ROM_LOAD( "gngprincess.n8", 0x0c000, 0x004000, CRC(bd17085c) )
ROM_LOAD( "gng.n13", 0x10000, 0x004000, CRC(fd9a8dda) )
ROM_LOAD( "gngprincess.n12", 0x14000, 0x004000, CRC(5199ea50) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "gg2.bin", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "gg1princess.bin", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "gg11.bin", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "gg10.bin", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "gg9.bin", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "gg8.bin", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "gg7.bin", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "gg6.bin", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "gg17princess.bin", 0x00000, 0x004000, CRC(e2043162) )
ROM_LOAD( "gg16princess.bin", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "gg15princess.bin", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "gg14princess.bin", 0x0c000, 0x004000, CRC(19847a61) )
ROM_LOAD( "gg13princess.bin", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "gg12princess.bin", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( gngprincesscenh )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "gngprincess.n10", 0x04000, 0x004000, CRC(36e043ad) )
ROM_LOAD( "gngprincess.n9", 0x08000, 0x004000, CRC(3632f7f5) )
ROM_LOAD( "gngprincess.n8", 0x0c000, 0x004000, CRC(393780fd) )
ROM_LOAD( "gng.n13", 0x10000, 0x004000, CRC(fd9a8dda) )
ROM_LOAD( "gngprincess.n12", 0x14000, 0x004000, CRC(98ce9232) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "gg2.bin", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "gg1princess.bin", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "gg11.bin", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "gg10.bin", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "gg9.bin", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "gg8.bin", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "gg7.bin", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "gg6.bin", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "gg17princess.bin", 0x00000, 0x004000, CRC(e2043162) )
ROM_LOAD( "gg16princess.bin", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "gg15princess.bin", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "gg14princess.bin", 0x0c000, 0x004000, CRC(19847a61) )
ROM_LOAD( "gg13princess.bin", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "gg12princess.bin", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( gngprincessenh )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "mm_c_princess_04", 0x04000, 0x004000, CRC(3b6d9dcf) )
ROM_LOAD( "mm_c_princess_03", 0x08000, 0x008000, CRC(a5921aeb) )
ROM_LOAD( "mm_c_princess_05", 0x10000, 0x008000, CRC(d1542dec) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "gg2.bin", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "gg1princess.bin", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "gg11.bin", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "gg10.bin", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "gg9.bin", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "gg8.bin", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "gg7.bin", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "gg6.bin", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "gg17princess.bin", 0x00000, 0x004000, CRC(e2043162) )
ROM_LOAD( "gg16princess.bin", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "gg15princess.bin", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "gg14princess.bin", 0x0c000, 0x004000, CRC(19847a61) )
ROM_LOAD( "gg13princess.bin", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "gg12princess.bin", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( gngprincesst )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "mmt04dprincess.10n", 0x04000, 0x004000, CRC(11dd8836) )
ROM_LOAD( "mmt03dprincess.8n", 0x08000, 0x008000, CRC(9ff8665c) )
ROM_LOAD( "mmt05dprincess.13n", 0x10000, 0x008000, CRC(7e06e90f) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "mm02.14h", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "mm01princess.11e", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "mm11.3e", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "mm10.1e", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "mm09.3c", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "mm08.1c", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "mm07.3b", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "mm06.1b", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "mm17princess.4n", 0x00000, 0x004000, CRC(e2043162) )
ROM_LOAD( "mm16princess.3n", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "mm15princess.1n", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "mm14princess.4l", 0x0c000, 0x004000, CRC(19847a61) )
ROM_LOAD( "mm13princess.3l", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "mm12princess.1l", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( gngprincesstenh )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "mmt04dprincess.10n", 0x04000, 0x004000, CRC(11dd8836) )
ROM_LOAD( "mmt03dprincess.8n", 0x08000, 0x008000, CRC(b57e52d7) )
ROM_LOAD( "mmt05dprincess.13n", 0x10000, 0x008000, CRC(e4ee3423) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "mm02.14h", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "mm01princess.11e", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "mm11.3e", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "mm10.1e", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "mm09.3c", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "mm08.1c", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "mm07.3b", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "mm06.1b", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "mm17princess.4n", 0x00000, 0x004000, CRC(e2043162) )
ROM_LOAD( "mm16princess.3n", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "mm15princess.1n", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "mm14princess.4l", 0x0c000, 0x004000, CRC(19847a61) )
ROM_LOAD( "mm13princess.3l", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "mm12princess.1l", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( makprincess )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "10nprincess.rom", 0x04000, 0x004000, CRC(49dc2d12) )
ROM_LOAD( "8nprincess.rom", 0x08000, 0x008000, CRC(ff005be0) )
ROM_LOAD( "12nprincess.rom", 0x10000, 0x008000, CRC(7c2064ca) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "gg2.bin", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "gg1princess.bin", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "gg11.bin", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "gg10.bin", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "gg9.bin", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "gg8.bin", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "gg7.bin", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "gg6.bin", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "gng13princess.n4", 0x00000, 0x004000, CRC(07c9138a) )
ROM_LOAD( "gg16princess.bin", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "gg15princess.bin", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "gng16princess.l4", 0x0c000, 0x004000, CRC(3cc87995) )
ROM_LOAD( "gg13princess.bin", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "gg12princess.bin", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( makprincessb )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "mj04bprincess.10n", 0x04000, 0x004000, CRC(3084ed7d) )
ROM_LOAD( "mj03bprincess.8n", 0x08000, 0x008000, CRC(b80cae7a) )
ROM_LOAD( "mj05bprincess.12n", 0x10000, 0x008000, CRC(6f8d3556) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "mm02.14h", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "mj01princess.11e", 0x00000, 0x004000, CRC(824ae0fc) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "mm11.3e", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "mm10.1e", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "mm09.3c", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "mm08.1c", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "mm07.3b", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "mm06.1b", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "mj17princess.4n", 0x00000, 0x004000, CRC(07c9138a) )
ROM_LOAD( "mj16princess.3n", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "mj15princess.1n", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "mj14princess.4l", 0x0c000, 0x004000, CRC(3cc87995) )
ROM_LOAD( "mj13princess.3l", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "mj12princess.1l", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( makprincessbenh )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "mj04bprincess.10n", 0x04000, 0x004000, CRC(3084ed7d) )
ROM_LOAD( "mj03bprincess.8n", 0x08000, 0x008000, CRC(de44ac2d) )
ROM_LOAD( "mj05bprincess.12n", 0x10000, 0x008000, CRC(7aefa8a0) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "mm02.14h", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "mj01princess.11e", 0x00000, 0x004000, CRC(824ae0fc) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "mm11.3e", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "mm10.1e", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "mm09.3c", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "mm08.1c", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "mm07.3b", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "mm06.1b", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "mj17princess.4n", 0x00000, 0x004000, CRC(07c9138a) )
ROM_LOAD( "mj16princess.3n", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "mj15princess.1n", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "mj14princess.4l", 0x0c000, 0x004000, CRC(3cc87995) )
ROM_LOAD( "mj13princess.3l", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "mj12princess.1l", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( makprincessc )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "mj04cprincess.bin", 0x04000, 0x004000, CRC(daada743) )
ROM_LOAD( "mj03cprincess.bin", 0x08000, 0x008000, CRC(7d0909cf) )
ROM_LOAD( "mj05cprincess.bin", 0x10000, 0x008000, CRC(0c9ed2e0) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "gg2.bin", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "gg1princess.bin", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "gg11.bin", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "gg10.bin", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "gg9.bin", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "gg8.bin", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "gg7.bin", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "gg6.bin", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "gng13princess.n4", 0x00000, 0x004000, CRC(07c9138a) )
ROM_LOAD( "gg16princess.bin", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "gg15princess.bin", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "gng16princess.l4", 0x0c000, 0x004000, CRC(3cc87995) )
ROM_LOAD( "gg13princess.bin", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "gg12princess.bin", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( makprincesscenh )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "mj04cprincess.bin", 0x04000, 0x004000, CRC(daada743) )
ROM_LOAD( "mj03cprincess.bin", 0x08000, 0x008000, CRC(16fe9d4a) )
ROM_LOAD( "mj05cprincess.bin", 0x10000, 0x008000, CRC(0547b319) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "gg2.bin", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "gg1princess.bin", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "gg11.bin", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "gg10.bin", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "gg9.bin", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "gg8.bin", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "gg7.bin", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "gg6.bin", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "gng13princess.n4", 0x00000, 0x004000, CRC(07c9138a) )
ROM_LOAD( "gg16princess.bin", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "gg15princess.bin", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "gng16princess.l4", 0x0c000, 0x004000, CRC(3cc87995) )
ROM_LOAD( "gg13princess.bin", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "gg12princess.bin", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( makprincessenh )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "10nprincess.rom", 0x04000, 0x004000, CRC(49dc2d12) )
ROM_LOAD( "8nprincess.rom", 0x08000, 0x008000, CRC(b526a64b) )
ROM_LOAD( "12nprincess.rom", 0x10000, 0x008000, CRC(1abdbe3e) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "gg2.bin", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "gg1princess.bin", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "gg11.bin", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "gg10.bin", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "gg9.bin", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "gg8.bin", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "gg7.bin", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "gg6.bin", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "gng13princess.n4", 0x00000, 0x004000, CRC(07c9138a) )
ROM_LOAD( "gg16princess.bin", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "gg15princess.bin", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "gng16princess.l4", 0x0c000, 0x004000, CRC(3cc87995) )
ROM_LOAD( "gg13princess.bin", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "gg12princess.bin", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( makprincessg )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "mj04gprincess.bin", 0x04000, 0x004000, CRC(bd45de21) )
ROM_LOAD( "mj03gprincess.bin", 0x08000, 0x008000, CRC(e6bbe084) )
ROM_LOAD( "mj05gprincess.bin", 0x10000, 0x008000, CRC(cd6ce99c) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "gg2.bin", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "gg1princess.bin", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "gg11.bin", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "gg10.bin", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "gg9.bin", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "gg8.bin", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "gg7.bin", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "gg6.bin", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "gng13princess.n4", 0x00000, 0x004000, CRC(07c9138a) )
ROM_LOAD( "gg16princess.bin", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "gg15princess.bin", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "gng16princess.l4", 0x0c000, 0x004000, CRC(3cc87995) )
ROM_LOAD( "gg13princess.bin", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "gg12princess.bin", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( makprincessgenh )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "mj04gprincess.bin", 0x04000, 0x004000, CRC(bd45de21) )
ROM_LOAD( "mj03gprincess.bin", 0x08000, 0x008000, CRC(20b5aeeb) )
ROM_LOAD( "mj05gprincess.bin", 0x10000, 0x008000, CRC(21288a1b) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "gg2.bin", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "gg1princess.bin", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "gg11.bin", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "gg10.bin", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "gg9.bin", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "gg8.bin", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "gg7.bin", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "gg6.bin", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "gng13princess.n4", 0x00000, 0x004000, CRC(07c9138a) )
ROM_LOAD( "gg16princess.bin", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "gg15princess.bin", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "gng16princess.l4", 0x0c000, 0x004000, CRC(3cc87995) )
ROM_LOAD( "gg13princess.bin", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "gg12princess.bin", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( gngknight )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "mm_c_knight_03", 0x08000, 0x008000, CRC(57f4f653) SHA1(7fce045ccffd4274edb75ebd726e42c2cb797dcb) )
@@ -2022,6 +2541,25 @@ GAME( 2026, gngmaidenc, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Gobl
GAME( 2026, gngmaidencenh, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Maiden Artoria Edition (Enhanced) (World? 4)" )
GAME( 2026, gngmaident, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Maiden Artoria Edition (US)" )
GAME( 2026, gngmaidentenh, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Maiden Artoria Edition (Enhanced) (US)" )
GAME( 2026, gngprincess, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Princess Prin Prin Edition (World? 1)" )
GAME( 2026, gngprincessa, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Princess Prin Prin Edition (World? 2)" )
GAME( 2026, gngprincessaenh, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Princess Prin Prin Edition (Enhanced) (World? 2)" )
GAME( 2026, gngprincessb, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Princess Prin Prin Edition (World? 3)" )
GAME( 2026, gngprincessbenh, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Princess Prin Prin Edition (Enhanced) (World? 3)" )
GAME( 2026, gngprincessc, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Princess Prin Prin Edition (World? 4)" )
GAME( 2026, gngprincesscenh, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Princess Prin Prin Edition (Enhanced) (World? 4)" )
GAME( 2026, gngprincessenh, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Princess Prin Prin Edition (Enhanced) (World? 1)" )
GAME( 2026, gngprincesst, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Princess Prin Prin Edition (US)" )
GAME( 2026, gngprincesstenh, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Princess Prin Prin Edition (Enhanced) (US)" )
GAME( 2026, makprincess, gng, gng, makaimur, 0, ROT0, "GoodLuckTrying", "Makaimura - Princess Prin Prin Edition" )
GAME( 2026, makprincessb, gng, gng, makaimur, 0, ROT0, "GoodLuckTrying", "Makaimura - Princess Prin Prin Edition (Japan revision B)" )
GAME( 2026, makprincessbenh, gng, gng, makaimur, 0, ROT0, "GoodLuckTrying", "Makaimura - Princess Prin Prin Edition (Enhanced) (Japan revision B)" )
GAME( 2026, makprincessc, gng, gng, makaimur, 0, ROT0, "GoodLuckTrying", "Makaimura - Princess Prin Prin Edition (Japan revision C)" )
GAME( 2026, makprincesscenh, gng, gng, makaimur, 0, ROT0, "GoodLuckTrying", "Makaimura - Princess Prin Prin Edition (Enhanced) (Japan revision C)" )
GAME( 2026, makprincessenh, gng, gng, makaimur, 0, ROT0, "GoodLuckTrying", "Makaimura - Princess Prin Prin Edition (Enhanced)" )
GAME( 2026, makprincessg, gng, gng, makaimur, 0, ROT0, "GoodLuckTrying", "Makaimura - Princess Prin Prin Edition (Japan revision G)" )
GAME( 2026, makprincessgenh, gng, gng, makaimur, 0, ROT0, "GoodLuckTrying", "Makaimura - Princess Prin Prin Edition (Enhanced) (Japan revision G)" )
GAME( 2026, gngknight, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Knight Artoria Edition (World? 1)" )
GAME( 2026, gngknightenh, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Knight Artoria Edition (Enhanced) (World? 1)" )
GAME( 2026, gngknighta, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Knight Artoria Edition (World? 2)" )
src/drivers/grchamp.c
+1 -1
View File
@@ -137,7 +137,7 @@ READ_HANDLER( PC3259_2_r )
}
if( grchamp_collision&2 )
{
result = rand()&0xff; /* OBJECT crash*/
result = mame_rand_int()&0xff; /* OBJECT crash*/
}
return result;
}
src/drivers/hitme.c
+4 -4
View File
@@ -190,10 +190,10 @@ static READ_HANDLER ( hitme_port_0_r )
{
if ((timer_get_time() - timeout_time) > (timeout_counter * tock))
{
return input_port_0_r (offset) - ((rand()%2) << 2) - 0x80;
return input_port_0_r (offset) - ((mame_rand_int()%2) << 2) - 0x80;
}
else
return input_port_0_r (offset) - ((rand()%2) << 2);
return input_port_0_r (offset) - ((mame_rand_int()%2) << 2);
}
static READ_HANDLER ( hitme_port_1_r )
@@ -210,10 +210,10 @@ static READ_HANDLER ( hitme_port_2_r )
{
if ((timer_get_time() - timeout_time) > (timeout_counter * tock))
{
return input_port_2_r (offset) - ((rand()%2) << 2) - 0x80;
return input_port_2_r (offset) - ((mame_rand_int()%2) << 2) - 0x80;
}
else
return input_port_2_r (offset) - ((rand()%2) << 2);
return input_port_2_r (offset) - ((mame_rand_int()%2) << 2);
}
static READ_HANDLER ( hitme_port_3_r )
src/drivers/hvyunit.c
+1171
View File
File diff suppressed because it is too large. Load diff
src/drivers/inufuku.c
+236 -4
View File
@@ -75,6 +75,8 @@ TODO:
VIDEO_UPDATE( inufuku );
VIDEO_START( inufuku );
void dunk_buffer_sprites(void);
int inufuku_is_dunk;
data16_t *inufuku_bg_videoram;
data16_t *inufuku_bg_rasterram;
@@ -104,17 +106,19 @@ static WRITE16_HANDLER( inufuku_soundcommand_w )
if (ACCESSING_LSB) {
/* hack... sound doesn't work otherwise */
if (data == 0x08) return;
if (!inufuku_is_dunk && data == 0x08) return;
pending_command = 1;
soundlatch_w(0, data & 0xff);
cpu_set_irq_line(1, IRQ_LINE_NMI, PULSE_LINE);
cpu_set_irq_line(1, IRQ_LINE_NMI, inufuku_is_dunk ? ASSERT_LINE : PULSE_LINE);
}
}
static WRITE_HANDLER( pending_command_clear_w )
{
pending_command = 0;
if (inufuku_is_dunk)
cpu_set_irq_line(1, IRQ_LINE_NMI, CLEAR_LINE);
}
static WRITE_HANDLER( inufuku_soundrombank_w )
@@ -133,15 +137,27 @@ static WRITE_HANDLER( inufuku_soundrombank_w )
static MACHINE_INIT( inufuku )
{
;
if (inufuku_is_dunk)
{
pending_command = 0;
inufuku_soundrombank_w(0, 0);
cpu_set_irq_line(1, IRQ_LINE_NMI, CLEAR_LINE);
}
}
static DRIVER_INIT( inufuku )
{
inufuku_is_dunk = 0;
pending_command = 1;
inufuku_soundrombank_w(0, 0);
}
static DRIVER_INIT( dunk )
{
inufuku_is_dunk = 1;
pending_command = 0;
inufuku_soundrombank_w(0, 0);
}
/******************************************************************************
@@ -223,6 +239,50 @@ static MEMORY_WRITE16_START( inufuku_writemem )
{ 0xfd0000, 0xfdffff, MWA16_RAM }, /* work ram*/
MEMORY_END
static MEMORY_READ16_START( dunk_readmem )
{ 0x000000, 0x0fffff, MRA16_ROM }, /* main rom*/
{ 0x180000, 0x180001, input_port_0_word_r },
{ 0x180002, 0x180003, input_port_1_word_r },
{ 0x180004, 0x180005, input_port_2_word_r },
{ 0x180006, 0x180007, input_port_3_word_r },
{ 0x180008, 0x180009, inufuku_eeprom_r }, /* eeprom + input_port_4_word_r*/
{ 0x18000a, 0x18000b, input_port_5_word_r },
{ 0x300000, 0x301fff, MRA16_RAM }, /* palette ram*/
{ 0x400000, 0x401fff, inufuku_bg_videoram_r }, /* bg ram*/
{ 0x402000, 0x403fff, inufuku_text_videoram_r },/* text ram*/
{ 0x404000, 0x40ffff, MRA16_RAM },
{ 0x580000, 0x581fff, MRA16_RAM }, /* sprite table + sprite attribute*/
{ 0x600000, 0x61ffff, MRA16_RAM }, /* cell table*/
{ 0x800000, 0xbfffff, MRA16_ROM }, /* data rom*/
{ 0xfd0000, 0xfdffff, MRA16_RAM }, /* work ram*/
MEMORY_END
static MEMORY_WRITE16_START( dunk_writemem )
{ 0x000000, 0x0fffff, MWA16_ROM }, /* main rom*/
{ 0x100000, 0x100007, MWA16_NOP }, /* ?*/
{ 0x200000, 0x200001, inufuku_eeprom_w }, /* eeprom*/
{ 0x280000, 0x280001, inufuku_soundcommand_w }, /* sound command*/
{ 0x300000, 0x301fff, paletteram16_xGGGGGBBBBBRRRRR_word_w, &paletteram16 }, /* palette ram*/
{ 0x380000, 0x3801ff, MWA16_RAM, &inufuku_bg_rasterram }, /* bg raster ram*/
{ 0x400000, 0x401fff, inufuku_bg_videoram_w, &inufuku_bg_videoram }, /* bg ram*/
{ 0x402000, 0x403fff, inufuku_text_videoram_w, &inufuku_text_videoram }, /* text ram*/
{ 0x404000, 0x40ffff, MWA16_RAM },
{ 0x580000, 0x581fff, MWA16_RAM, &inufuku_spriteram1, &inufuku_spriteram1_size }, /* sprite table + sprite attribute*/
{ 0x600000, 0x61ffff, MWA16_RAM, &inufuku_spriteram2 }, /* cell table*/
{ 0x780000, 0x780013, inufuku_palettereg_w }, /* bg & text palettebank register*/
{ 0x7a0000, 0x7a0023, inufuku_scrollreg_w }, /* bg & text scroll register*/
{ 0x7e0000, 0x7e0001, MWA16_NOP }, /* ?*/
{ 0x800000, 0xbfffff, MWA16_ROM }, /* data rom*/
{ 0xfd0000, 0xfdffff, MWA16_RAM }, /* work ram*/
MEMORY_END
/******************************************************************************
@@ -329,6 +389,70 @@ INPUT_PORTS_START( inufuku )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON4 | IPF_PLAYER3 )
INPUT_PORTS_END
INPUT_PORTS_START( dunk )
PORT_START /* 0*/
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_PLAYER1 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_PLAYER1 )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_PLAYER1 )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_PLAYER1 )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1 )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER1 )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER1 )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON4 | IPF_PLAYER1 )
PORT_START /* 1*/
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_PLAYER2 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_PLAYER2 )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_PLAYER2 )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_PLAYER2 )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2 )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER2 )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON4 | IPF_PLAYER2 )
PORT_START /* 2*/
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
PORT_SERVICE_NO_TOGGLE( 0x10, IP_ACTIVE_LOW )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_TILT )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START /* 3*/
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_PLAYER4 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_PLAYER4 )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_PLAYER4 )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_PLAYER4 )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER4 )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER4 )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER4 )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON4 | IPF_PLAYER4 )
PORT_START /* 4*/
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN3 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN4 )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START3 )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START4 )
PORT_DIPNAME( 0x10, 0x10, "3P/4P" )
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* pending sound command*/
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START /* 5*/
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_PLAYER3 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_PLAYER3 )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_PLAYER3 )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_PLAYER3 )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER3 )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER3 )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER3 )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON4 | IPF_PLAYER3 )
INPUT_PORTS_END
/******************************************************************************
@@ -360,6 +484,19 @@ static struct GfxLayout spritelayout =
128*8
};
static struct GfxLayout dunk_spritelayout =
{
16, 16,
RGN_FRAC(1, 1),
4,
{ 0, 1, 2, 3 },
{ 1*4, 0*4, 3*4, 2*4, 5*4, 4*4, 7*4, 6*4,
9*4, 8*4, 11*4, 10*4, 13*4, 12*4, 15*4, 14*4 },
{ 0*64, 1*64, 2*64, 3*64, 4*64, 5*64, 6*64, 7*64,
8*64, 9*64, 10*64, 11*64, 12*64, 13*64, 14*64, 15*64 },
128*8
};
static struct GfxDecodeInfo inufuku_gfxdecodeinfo[] =
{
{ REGION_GFX1, 0, &tilelayout, 0, 256*16 }, /* bg*/
@@ -368,6 +505,14 @@ static struct GfxDecodeInfo inufuku_gfxdecodeinfo[] =
{ -1 } /* end of array */
};
static struct GfxDecodeInfo dunk_gfxdecodeinfo[] =
{
{ REGION_GFX1, 0, &tilelayout, 0, 256*16 }, // bg
{ REGION_GFX2, 0, &tilelayout, 0, 256*16 }, // text
{ REGION_GFX3, 0, &dunk_spritelayout, 0, 256*16 }, // sprite
{ -1 } /* end of array */
};
/******************************************************************************
@@ -435,6 +580,62 @@ static MACHINE_DRIVER_START( inufuku )
MACHINE_DRIVER_END
static INTERRUPT_GEN( dunk_interrupt )
{
/* Latch the completed list before the IRQ lets the main CPU rewrite it. */
dunk_buffer_sprites();
irq1_line_hold();
}
static struct YM2610interface dunk_ym2610_interface =
{
1,
32000000/4, /* 8.00 MHz */
{ 50 },
{ 0 },
{ 0 },
{ 0 },
{ 0 },
{ irqhandler },
{ REGION_SOUND2 },
{ REGION_SOUND1 },
{ YM3012_VOL(25, MIXER_PAN_CENTER, 25, MIXER_PAN_CENTER) }
};
static MACHINE_DRIVER_START( dunk )
/* basic machine hardware */
MDRV_CPU_ADD(M68000, 32000000/2) /* 16.00 MHz */
MDRV_CPU_MEMORY(dunk_readmem, dunk_writemem)
MDRV_CPU_VBLANK_INT(dunk_interrupt, 1)
MDRV_CPU_ADD(Z80, 32000000/4) /* 8.00 MHz */
MDRV_CPU_FLAGS(CPU_AUDIO_CPU)
MDRV_CPU_MEMORY(inufuku_readmem_sound, inufuku_writemem_sound)
MDRV_CPU_PORTS(inufuku_readport_sound, inufuku_writeport_sound)
/* IRQs are triggered by the YM2610 */
MDRV_FRAMES_PER_SECOND(60)
MDRV_VBLANK_DURATION(2300)
MDRV_MACHINE_INIT(inufuku)
MDRV_NVRAM_HANDLER(93C46)
/* video hardware */
MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER)
MDRV_SCREEN_SIZE(2048, 256)
MDRV_VISIBLE_AREA(0, 319, 0, 223)
MDRV_GFXDECODE(dunk_gfxdecodeinfo)
MDRV_PALETTE_LENGTH(4096)
MDRV_VIDEO_START(inufuku)
MDRV_VIDEO_UPDATE(inufuku)
/* sound hardware */
MDRV_SOUND_ADD(YM2610, dunk_ym2610_interface)
MACHINE_DRIVER_END
/******************************************************************************
ROM definitions
@@ -466,6 +667,36 @@ ROM_START( inufuku )
ROM_LOAD( "lhmn5ku6.u53", 0x0000000, 0x400000, CRC(b320c5c9) SHA1(7c99da2d85597a3c008ed61a3aa5f47ad36186ec) )
ROM_END
ROM_START( 3on3dunk )
ROM_REGION( 0x0c00000, REGION_CPU1, 0 )
ROM_LOAD16_WORD_SWAP( "prog0_2_4_usa.u147", 0x0000000, 0x080000, CRC(957924ab) SHA1(6fe8ca711d11239310d58188e9d6d28cd27bc5af) )
ROM_LOAD16_WORD_SWAP( "prog1_2_4_usa.u146", 0x0080000, 0x080000, CRC(2479e236) SHA1(729e6c85d34d6925c8d6557b138e2bed43e1de6a) )
ROM_LOAD16_WORD_SWAP( "lh535l5y.u148", 0x0800000, 0x400000, CRC(aa33e02a) SHA1(86381ecf18fba9065cbc02112751c435bbf8b8b4) )
ROM_REGION( 0x0030000, REGION_CPU2, 0 )
ROM_LOAD( "sound_prog_97_1_13.u107", 0x0000000, 0x020000, CRC(d9d42805) SHA1(ab5cb7c141d9c9ed5121ba4dbc1d0fa187bd9f68) )
ROM_RELOAD( 0x010000, 0x020000 )
ROM_REGION( 0x0400000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD16_WORD_SWAP( "lh525kwy.u40", 0x0000000, 0x400000, CRC(aaa426d1) SHA1(2f9a2981f336caf3188baec9a34f61452dee2203) )
ROM_REGION( 0x0400000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD16_WORD_SWAP( "lh537nn4.u8", 0x0000000, 0x200000, CRC(2b7be1d8) SHA1(aac274a8f4028db7429478601a1761e61ab4f9a2) )
ROM_REGION( 0x2000000, REGION_GFX3, ROMREGION_DISPOSE )
ROM_LOAD( "lh535kwz.u34", 0x0000000, 0x400000, CRC(7372ce78) SHA1(ed2a861986357fad7ef983750cd906c3d722b862) )
ROM_LOAD( "lh535kv0.u36", 0x0400000, 0x400000, CRC(247e5741) SHA1(8d71d964791fb4b86e390bcdf7744f616d6357b1) )
ROM_LOAD( "lh535kv2.u38", 0x0800000, 0x400000, CRC(76449b1e) SHA1(b63d50c6f0dc91dc94dbcdda9842598529c1c26e) )
ROM_LOAD( "lh537nn5.u20", 0x0c00000, 0x200000, CRC(f457cd3b) SHA1(cc13f5dc44e4675c1074a365b10f34e684817d81) )
ROM_LOAD( "lh536pnm.u32", 0x1000000, 0x400000, CRC(bc39e449) SHA1(5aea90b66ee03c70797ddc42dbcb064d83ce8cc7) )
ROM_REGION( 0x0400000, REGION_SOUND1, 0 )
ROM_LOAD( "lh5388r1.u53", 0x0000000, 0x100000, CRC(765d892f) SHA1(9b078c879d0437d1669bf4301fd52a768aa4d293) )
ROM_REGION( 0x0400000, REGION_SOUND2, 0 )
ROM_LOAD( "lh536pkl.u51", 0x0000000, 0x300000, CRC(e4919abf) SHA1(d6af4b9c6ff62f92216c9927027d3b2376416bae) )
ROM_END
/******************************************************************************
@@ -473,4 +704,5 @@ ROM_END
******************************************************************************/
GAMEX( 1998, inufuku, 0, inufuku, inufuku, inufuku, ROT0, "Video System Co.", "Quiz and Variety Sukusuku Inufuku (Japan)", GAME_NO_COCKTAIL )
GAMEX( 1998, inufuku, 0, inufuku, inufuku, inufuku, ROT0, "Video System Co.", "Quiz and Variety Sukusuku Inufuku (Japan)", GAME_NO_COCKTAIL )
GAMEX( 1996, 3on3dunk, 0, dunk, dunk, dunk, ROT0, "Video System Co.", "3 On 3 Dunk Madness (US, prototype? 1997/02/04)", GAME_NO_COCKTAIL | GAME_IMPERFECT_GRAPHICS )
src/drivers/itech32.c
+2 -2
View File
@@ -571,7 +571,7 @@ static NVRAM_HANDLER( itech32 )
mame_fread(file, main_ram, main_ram_size);
else
for (i = 0x80; i < main_ram_size; i++)
((UINT8 *)main_ram)[i] = rand();
((UINT8 *)main_ram)[i] = mame_rand_int();
}
@@ -585,7 +585,7 @@ static NVRAM_HANDLER( itech020 )
mame_fread(file, nvram, nvram_size);
else
for (i = 0; i < nvram_size; i++)
((UINT8 *)nvram)[i] = rand();
((UINT8 *)nvram)[i] = mame_rand_int();
}
src/drivers/itech8.c
+1 -1
View File
@@ -616,7 +616,7 @@ static NVRAM_HANDLER( itech8 )
mame_fread(file, main_ram, main_ram_size);
else
for (i = 0; i < main_ram_size; i++)
main_ram[i] = rand();
main_ram[i] = mame_rand_int();
}
src/drivers/kopunch.c
+3 -3
View File
@@ -37,9 +37,9 @@ static READ_HANDLER( kopunch_in_r )
{
/* port 31 + low 3 bits of port 32 contain the punch strength */
if (offset == 0)
return rand();
return mame_rand_int();
else
return (rand() & 0x07) | input_port_1_r(0);
return (mame_rand_int() & 0x07) | input_port_1_r(0);
}
static WRITE_HANDLER( kopunch_lamp_w )
@@ -76,7 +76,7 @@ MEMORY_END
static READ_HANDLER( pip_r )
{
return rand();
return mame_rand_int();
}
static PORT_READ_START( readport )
Loaded 100 of 316 files, more files were not shown because too many files have changed in this diff. Show more