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1546 Commits

Author SHA1 Message Date
Michal Schulz
8751115a2e Honour direction bit in fmove instruction (#1709) 
Co-authored-by: Michal Schulz <michal@Michals-iMac-Pro.local>
 2020-12-03 16:12:56 +08:00
Anton Kochkov
6a8406aff6 M680X - remove unused s_cpu_type (#1695) 2020-10-29 12:29:49 +08:00
Richard Henderson
e34cd5475b Two RISC-V fixes (#1682) 
* RISCV: Check CS_MODE_RISCVC in getFeatureBits

Enable compressed instruction extension with RISCVC.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

* RISCV: Fix skipdata_size for CS_MODE_RISCVC

RISC-V compressed instructions are 2 bytes, not 1.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2020-09-16 17:04:18 +08:00
Maxim Poliakovski
46e4a405da M68K: fix MOVEC operand transfer direction. (#1663) 2020-07-19 17:06:08 +08:00
Nicolas Derumigny
e46d8c49c7 Correcting X86 Imm Size 2020-07-02 16:39:15 +02:00
cyanpencil
b99a991a9b Fix cmp register access on aarch64 2020-07-01 16:04:06 +02:00
Daniel Collin
83d817339e Fixed incorrect read of 32-bit imm for bsr (#1644) 2020-06-12 23:00:47 +08:00
Antonio Flores Montoya
78a897ee12 fix bug in displacement offset (#1600) 2020-05-11 02:20:13 +08:00
Eric Kilmer
c0d5f4e280 Add more cases for LD1 instruction immediate fixups (#1632) 2020-05-10 10:03:52 +08:00
el poto rico
b818c6bdd0 ARM64: Populate implicitly used/modified registers and map ARM64_GRP_CALL to BL* (#1610) 
This commit adds some registers to the list of implicit used registers and
implicit modified registers for several AArch64 instructions.

This commit also maps the `ARM64_GRP_CALL` group to the BL* instruction family.
It should fix issue #1606.
 2020-05-10 01:46:55 +08:00
Nguyen Anh Quynh
73bbf84432 arm64: some POST instructions miss IMM operand. this fixes issue #1627 2020-05-10 01:39:57 +08:00
elp0t0r1c0
0e759ed68e Add ARM64_GRP_PAC group for Pointer Authentication (#1607) 
* Add ARM64_GRP_PAC group for Pointer Authentication

* Lowercase the group's name
 2020-03-30 08:37:11 +08:00
Xiaozhu Meng
088163d897 Update x86 operand access information 2020-03-18 10:32:51 -05:00
Nicolas Derumigny
d9b9900250 Bug solved: SSE variant of MOVSD incorrectly decoded as REPNE MOVSD (#1540) 2020-02-21 09:58:32 +08:00
DarkaMaul
0e90045ddc fix: Remove wrong write in ARM_t2STMDB_UPD instruction (#1588) 2020-02-21 09:56:35 +08:00
Richard Henderson
936dca0e2d Constify backends (#1549) 
* Constify registerinfo.py output

Remove two conditionals separating identical bits of code.
Add "const" markup to MCRegisterDesc and MCRegisterClass.

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify instrinfo-arch.py output

In this case, do not actively strip const.

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the AArch64 backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the EVM backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify M680X backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify M68K backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the Mips backend

The Mips backend has not been regenerated from LLVM recently,
and there are more fixups required than I'd like.  Just apply
the fixes to the tables by hand for now.

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the Sparc backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the TMS320C64x backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the X86 backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the XCore backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify systemregister.py output

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the ARM backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the PowerPC backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the MOS65XX backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the SystemZ backend

The mapping of system register to indexes is easy to
generate read-only.  Since we know the indexes are
between 0 and 31, use uint8_t instead of unsigned.

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the WASM backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify cs.c

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the BPF backend

Signed-off-by: Richard Henderson <rth@twiddle.net>
 2019-12-23 20:30:57 +08:00
Nguyen Anh Quynh
d3c521e0a5 MOS65XX: C90 compatibility 2019-12-16 00:41:34 +08:00
Jiayi Zhao
b29dca2cf7 systemz: fix base/index printing (#1561) 
- In cases where base is 0 but index is not, Capstone doesn't print anything
 2019-11-05 11:48:06 +08:00
naq
43040603d7 systemz: fix truncated 64bit imm operand in issue #1515 2019-07-10 17:32:46 +08:00
keenk
c609731e38 Undo rollback of 3 movbe instruction's operand access fixes (#1512) 
* Fix a few registry access mode mappings

* Fix rollback of operand access changes

Re-fix operand access of three mov instructions
 2019-07-01 10:36:51 +08:00
Nguyen Anh Quynh
29c7012025 fix some compilation issues when DIET mode is on 2019-06-24 12:52:38 +08:00
naq
30bffad2d4 x86: fix a race condition made by a static variable initialization. bug reported by Xiaozhu Meng 2019-06-19 10:44:13 +08:00
naq
2c015c75b3 x86: printf64m should print qword ptr by default. TODO: fix related cases in tablegen instead 2019-06-09 01:58:03 +08:00
naq
b1038743c1 x86: checkPrefix() does not set prefix0 in repne case 2019-06-09 01:13:22 +08:00
naq
dcd3e99022 x86: fix missing opcode byte in #1505 2019-06-08 12:21:50 +08:00
Catena cyber
834359fdbf Fixes MOS groups count (#1503) 2019-06-05 10:32:19 +08:00
ksherlock
41e5f629ce updated 6502 support. (#1498) 
* updated 6502 support. some improvements to the base 6502 support but also adds support for 65c02, w65c02, and 65816.

* add CS_OPT_SYNTAX_MOTOROLA.

This will use "$" as a hex prefix instead of "0x"

* remove excess blank lines
 2019-06-03 23:20:51 +08:00
Travis Finkenauer
750ba01466 [RISCV] Use CS_ASSERT (#1493) 
* makefile: set CAPSTONE_DEBUG for debug build

Also fix long longs

* riscv: replace assert with CS_ASSERT

* cmake: add CAPSTONE_DEBUG option
 2019-05-23 08:25:36 +07:00
Wolfgang Schwotzer
37b8ecbb41 [M680X] Fix #1483: errors logged to stderr, using abort (2) (#1489) 
- This is not suitable for an application framework
  especially for kernel code.
- All these error conditions do not occur under normal conditions.
  They only can occur if a maintainer (in the future) would make
  inappropriate changes to the M680X code base.
- Added CS_ASSERT macro which allows to use assertions when debugging
  by defining CAPSTONE_DEBUG.
- Updated compiler documenation
 2019-05-20 10:22:27 +07:00
Nguyen Anh Quynh
d169f3fff5 ppc: mnemonic with dot postfix should update CR0. issue #1478 2019-05-17 11:50:11 +08:00
Nguyen Anh Quynh
afc8550d2a ppc: add missing condition registers of BDNZT. fixes issue #970 2019-05-17 11:36:55 +08:00
Nguyen Anh Quynh
cf6d808274 ppc: fix bdnzflr operand 2 missing. issue #969 2019-05-17 09:56:03 +08:00
Nguyen Anh Quynh
ea1b4537b8 arm: printAliasInstr() properly handle memory operands (similar to the last commit for ARM64 2019-05-16 21:34:39 +08:00
Nguyen Anh Quynh
94aa224272 arm64: LDR operands[1] is memory operand. fix issue #1481 2019-05-16 21:29:51 +08:00
Nguyen Anh Quynh
baf70c9755 ppc: BDZLA is absolute branch. fix issue #968 2019-05-16 11:06:24 +08:00
Nguyen Anh Quynh
41fdced346 ppc: fix TBEGIN decoder. issue #1478 2019-05-16 10:42:43 +08:00
Nguyen Anh Quynh
fe2e7eb00f arm64: fix a segfault. issue #1480 2019-05-15 21:04:13 +08:00
Ammar
9382c9ad54 x86: fix call/jmp access mode of mem operand (#1479) 
sets CS_AC_READ for memory operand of call and jmp instructions
 2019-05-14 23:11:32 +08:00
Nguyen Anh Quynh
c12f4e4118 cstest: add tests for xacquire/xrelease xchg 2019-05-14 10:59:07 +08:00
Nguyen Anh Quynh
ea30457f9e x86: recognize xacquire/xrelease for XCHG 2019-05-14 10:49:27 +08:00
Nguyen Anh Quynh
f3ca9a28b9 x86: recognize xrelease lock 2019-05-14 09:59:23 +08:00
Nguyen Anh Quynh
a1796341cb x86: recognize xacquire prefix. issue #1477 2019-05-13 22:27:05 +08:00
Nguyen Anh Quynh
90c0e6206b Merge branch 'next' of github.com:aquynh/capstone into next 2019-05-13 13:52:09 +08:00
Nguyen Anh Quynh
709aba4789 ppc: add JUMP group for some branch instructions 2019-05-11 11:52:43 +08:00
Nguyen Anh Quynh
287987a8a1 ppc: fix target address of bdnz. issue #1468 2019-05-11 10:18:36 +08:00
Nguyen Anh Quynh
946d55b781 synctools: fix genall-arch.sh for Arm & Arm64 2019-05-10 16:39:36 +08:00
Nguyen Anh Quynh
8f1021e117 ppc: cleanup 2019-05-10 14:43:01 +08:00
Nguyen Anh Quynh
bb6b2c137e ppc: fix target address for bdnzt 2019-05-10 14:38:51 +08:00
Nguyen Anh Quynh
71c59fce93 ppc: cleanup debug code 2019-05-10 01:06:47 +08:00
Nguyen Anh Quynh
ea538571e9 ppc: alias for Bcc instructions. issue #1468 2019-05-10 00:57:03 +08:00
Nguyen Anh Quynh
d7e9aa90c3 Merge branch 'next' of github.com:aquynh/capstone into next 2019-05-09 22:20:48 +08:00
Nguyen Anh Quynh
37dda9d4b7 ppc: proper map internal register ID to public register ID 2019-05-09 18:26:45 +08:00
Nguyen Anh Quynh
63c07ba724 ppc: fix some mappings in PPCMappingInsn.inc 2019-05-09 18:08:08 +08:00
Nguyen Anh Quynh
12c830172e ppc: indentation 2019-05-09 12:34:06 +08:00
Nguyen Anh Quynh
2a9e171e3c ppc: print condition register bits. issue #1469 2019-05-08 13:56:40 +08:00
Nguyen Anh Quynh
0ebcc815cf ppc: fix target address of B. issue #1468 2019-05-07 16:08:45 +08:00
Nguyen Anh Quynh
89251f3c61 x86: LOCK prefix for 16bit case of ADC/ADD/AND/OR/XOR/SUB in issue #1472 2019-05-06 17:39:44 +08:00
Nguyen Anh Quynh
d0f65d9756 x86: update tablegen to fix MOV CRx/DRx, TEST & LOCK prefix in #1456 & #1472 2019-05-06 17:28:37 +08:00
Nguyen Anh Quynh
f2f3829f27 x86: handle MOV CRx/DRx & LOCK prefix in issues #1456 & #1472 2019-05-06 16:18:45 +08:00
Nguyen Anh Quynh
055b02dbd9 x86: lock adc is valid. issue #1472 2019-05-06 12:44:09 +08:00
Nguyen Anh Quynh
8a32a553f0 ppc: fix mapping of CRXOR. issue #1469 2019-04-30 17:13:54 +08:00
Nguyen Anh Quynh
9ad613a2af ppc: add some new .inc files 2019-04-30 13:52:23 +08:00
Nguyen Anh Quynh
b543c345ca ppc: sync with llvm 7.0.1 2019-04-30 13:50:42 +08:00
Catena cyber
dc082bc374 Aarch64 set operand in printSVERegOp (#1462) 2019-04-28 22:22:46 +07:00
Nguyen Anh Quynh
663e5fcee9 x86: fix xmmword ptr issue in #1456 (TODO: better fix) 2019-04-17 20:39:21 +08:00
Nguyen Anh Quynh
788f3e5dc5 arm: fix printPKHASRShiftImm() - issue #1456 2019-04-17 00:48:12 +08:00
Nguyen Anh Quynh
79e30283ef arm: fix printAliasInstr() for wfe.w - issue #1456 2019-04-17 00:34:45 +08:00
Nguyen Anh Quynh
f9f22b2925 x86: improve EIZ check 2019-04-16 23:55:18 +08:00
Nguyen Anh Quynh
3acc6e9275 x86: do not print EIZ register - issue #1456 2019-04-16 23:36:40 +08:00
Nguyen Anh Quynh
e8ec9863d2 arm64: fix imm value of MOV - issue #1456 2019-04-16 20:28:53 +08:00
Nguyen Anh Quynh
0a2fd07f67 arm64: fix more mapping instructions in AArch64MappingInsn.inc 2019-04-16 13:12:00 +08:00
Nguyen Anh Quynh
d6cbfa6f34 arm64: fix more mapping instructions in AArch64MappingInsn.inc 2019-04-16 13:04:20 +08:00
Nguyen Anh Quynh
67cc59c8d1 arm64: fix more mapping instructions in AArch64MappingInsn.inc 2019-04-16 13:01:59 +08:00
Nguyen Anh Quynh
f2787286e2 arm64: fix more instruction ID for ORR, BFI & BFXIL - issue #1456 2019-04-16 09:59:26 +08:00
Nguyen Anh Quynh
55b149f60a arm: alias LDR [sp], 4 to POP 2019-04-16 00:01:54 +08:00
Nguyen Anh Quynh
f099e00832 ppc: fix mapping of PPC_BCTRL8_LDinto_toc to PPC_INS_BCTRL 2019-04-15 20:45:04 +08:00
Nguyen Anh Quynh
59324a71ea arm64: fix some wrong mapping instruction ID - issue #1456 2019-04-15 20:44:37 +08:00
Nguyen Anh Quynh
88d5c390eb arm: fix the missing third operand of LSR - issue #1456 2019-04-15 07:47:04 +08:00
Nguyen Anh Quynh
af867a3fe1 arm: fix wrong order of operand with shift - issue #1456 2019-04-15 00:04:40 +08:00
Nguyen Anh Quynh
dde6867f06 arm64: fix lookupExactFPImmByEnum() leading to a crash (reported by OSS Fuzz) 2019-04-13 00:22:22 +08:00
Nguyen Anh Quynh
f18c6a5bf8 arm64: more fix for imm of MOV instruction. issue #1456 2019-04-12 23:49:42 +08:00
Nguyen Anh Quynh
8cbf967f67 arm64: fix imm of MOV instruction. issue 1456 2019-04-12 23:33:49 +08:00
Nguyen Anh Quynh
99d00fee14 x86: fix ATT syntax print immediate < 9 for MOV - issue #1456 2019-04-12 23:15:20 +08:00
Nguyen Anh Quynh
c976250b9b arm64: fix some ID mapping 2019-04-12 13:15:09 +08:00
Nguyen Anh Quynh
38d181d148 x86: quick fix for RCRm1 instruction - issue #1456 2019-04-12 00:38:23 +08:00
Nguyen Anh Quynh
3d50d2cffd arm: fix opcode of ASR/LSL/LSR/ROR/RRX - issue #1456 2019-04-12 00:08:04 +08:00
Nguyen Anh Quynh
e024477065 arm: fix some wrong insn mapping - issue #1456 2019-04-11 23:56:50 +08:00
Nguyen Anh Quynh
48cd47e4eb x86: fix BOUND instruction in issue #1456 2019-04-11 01:24:43 +08:00
Nguyen Anh Quynh
d5050f76ac arm: fix cstest 2019-04-11 00:46:12 +08:00
Nguyen Anh Quynh
a5b2d2a70a arm: fix mapping of ARM_SUBri (issue #1456) 2019-04-11 00:18:25 +08:00
Nguyen Anh Quynh
4754471262 merge next-arm64 to next 2019-04-10 17:46:07 +08:00
Nguyen Anh Quynh
f0a5df2504 arm64 & arm: fix some warnings 2019-04-10 17:33:41 +08:00
Nguyen Anh Quynh
e0f960e3e7 arm64: some bug fixes 2019-04-10 17:24:56 +08:00
Nguyen Anh Quynh
afeda44c90 arm64: fix crashes on some alias instructions 2019-04-10 16:07:40 +08:00
Nguyen Anh Quynh
7c07225170 arm64: cleanup 2019-04-10 14:22:23 +08:00
Nguyen Anh Quynh
f407e94249 arm64: sync with LLVM 7.0.1 2019-04-10 14:17:08 +08:00
Travis Finkenauer
adff6c21e5 tms320c64x: remove extra indent (#1426) 2019-04-03 11:38:10 +08:00
Nguyen Anh Quynh
dea98fa870 x86: CMPXCHG read AL/AX/EAX/RAX registers (issue #1454) 2019-03-29 23:29:35 +08:00
Nguyen Anh Quynh
69bf4dda42 Merge branch 'next' of github.com:aquynh/capstone into next 2019-03-24 12:17:20 +08:00
Nguyen Anh Quynh
586bef3168 arm64: set operand 0 in cmeq to IMM type (issue #1443) 2019-03-24 12:17:03 +08:00