RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-07 20:04:03 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity
34,714 Commits 4 Branches 5 Tags 634 MiB
cc317de0f5
Commit Graph

7487 Commits

Author SHA1 Message Date
Christopher Lamb
7196f0d724 Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled. 
llvm-svn: 41007
 2007-08-10 21:18:25 +00:00
Rafael Espindola
b20b9e985a propagate struct size and alignment of byval arguments to the DAG 
llvm-svn: 40986
 2007-08-10 14:44:42 +00:00
Bill Wendling
d0bee665d3 For kicks, I though it would be fun to use the correct opcode. 
llvm-svn: 40985
 2007-08-10 09:00:17 +00:00
Bill Wendling
55c3dc2409 Adding SSSE3 intrinsics. 
llvm-svn: 40982
 2007-08-10 06:22:27 +00:00
Evan Cheng
3fae8e1c4a Temporarily backing out this change until we know why some dejagnu tests are failing. 
llvm-svn: 40973
 2007-08-09 22:25:35 +00:00
Evan Cheng
a58ebc46dd divb / mulb outputs to ah. Under x86-64 it's not legal to read ah if the instruction requires a rex prefix (i.e. outputs to r8b, etc.). So issue shift right by 8 on AX and then truncate it to 8 bits instead. 
llvm-svn: 40972
 2007-08-09 21:59:35 +00:00
Evan Cheng
a822456bed GR16_ sub-register class should be GR8_, not GR8. That is, it should only be 8-bit registers in 32-bit mode. Ditto for GR32_. 
llvm-svn: 40970
 2007-08-09 18:05:17 +00:00
Dale Johannesen
79551baaad long double 9 of N. This finishes up the X86-32 bits 
(constants are still not handled).  Adds ConvertActions
to control fp-to-fp conversions (these are currently
defaulted for all other targets, so no changes there).

llvm-svn: 40958
 2007-08-09 01:04:01 +00:00
Dale Johannesen
6c8f73eac6 Fix arguments for some Altivec instructions. From SWB. 
llvm-svn: 40957
 2007-08-09 00:49:19 +00:00
Dale Johannesen
0ea7df37c4 Fix spelling of mtvscr and mfvscr. 
llvm-svn: 40908
 2007-08-07 23:08:00 +00:00
Dale Johannesen
6b8e91e7e3 Long double patch 8 of N: make it partially work in 
SSE mode (all but conversions <-> other FP types, I think):
>>Do not mark all-80-bit operations as "Requires[FPStack]"
(which really means "not SSE").
>>Refactor load-and-extend to facilitate this.
>>Update comments.
>>Handle long double in SSE when computing FP_REG_KILL.

llvm-svn: 40906
 2007-08-07 20:29:26 +00:00
Evan Cheng
8c896cc115 Initial JIT support for ARM by Raul Fernandes Herbster. 
llvm-svn: 40887
 2007-08-07 01:37:15 +00:00
Dale Johannesen
2c35d56edd Long double patch 7 of N, unless I lost count:). 
Last x87 bits for full functionality (not
thoroughly tested, and long doubles do not work
in SSE modes at all - use -mcpu=i486 for now)

llvm-svn: 40886
 2007-08-07 01:17:37 +00:00
Dale Johannesen
92be0d49fb Replace 4-line function with 10-line version per review comment. 
llvm-svn: 40881
 2007-08-06 22:10:35 +00:00
Dale Johannesen
4df87d9305 Move lengthy conditional down 1 level per review comment. 
llvm-svn: 40878
 2007-08-06 21:48:35 +00:00
Dale Johannesen
3ea9879011 Get X86 long double calling convention to work 
(on Darwin, anyway).  Fix some table omissions for
LD arithmetic.

llvm-svn: 40877
 2007-08-06 21:31:06 +00:00
Dale Johannesen
e3f1d06ca0 Make 80-bit store maintain simulated FP stack correctly. 
llvm-svn: 40868
 2007-08-06 19:50:32 +00:00
Reid Spencer
3e54e72ef1 Fix minor doxygen nits. 
llvm-svn: 40854
 2007-08-05 20:06:04 +00:00
Dale Johannesen
a85f11d870 Long double patch 4 of N: initial x87 implementation. 
Lots of problems yet but some simple things work.

llvm-svn: 40847
 2007-08-05 18:49:15 +00:00
Chandler Carruth
00e56b0e81 This is the patch to provide clean intrinsic function overloading support in LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future. 
This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported.

llvm-svn: 40807
 2007-08-04 01:51:18 +00:00
Dale Johannesen
c8462173c5 Make x86 long double alignment 32 for everything but 
Darwin (which makes size within a struct==96)

llvm-svn: 40796
 2007-08-03 22:46:15 +00:00
Dale Johannesen
4b91728849 long double patch 2 of N. Handle it in TargetData. 
(I've tried to get the info right for all targets,
but I'm not expert on all of them - check yours.)

llvm-svn: 40792
 2007-08-03 20:20:50 +00:00
Chris Lattner
a9026e5f12 add an observation 
llvm-svn: 40772
 2007-08-03 00:17:42 +00:00
Dan Gohman
352de5aeb9 More explicit keywords. 
llvm-svn: 40757
 2007-08-02 21:21:54 +00:00
Dan Gohman
1afde4166e Fix the alignment requirements of several unpck and shuf instructions. 
Generalize isPSHUFDMask and add a unary SHUFPD pattern so that SHUFPD's
memory operand alignment can be tested as well, with a fix to avoid
breaking MMX's use of isPSHUFDMask.

llvm-svn: 40756
 2007-08-02 21:17:01 +00:00
Dan Gohman
7d1e35e6d1 Fix pastos in vector arithmetic intrinsics. 
llvm-svn: 40754
 2007-08-02 21:06:40 +00:00
Dan Gohman
a599a813d5 Mark the SSE and MMX load instructions that 
X86InstrInfo::isReallyTriviallyReMaterializable knows how to handle
with the isReMaterializable flag so that it is given a chance to handle
them. Without hoisting constant-pool loads from loops this isn't very
visible, though it does keep CodeGen/X86/constant-pool-remat-0.ll from
making a copy of the constant pool on the stack.

llvm-svn: 40736
 2007-08-02 14:27:55 +00:00
Evan Cheng
3163814591 Switch some multiplication instructions over to the new scheme for testing. 
llvm-svn: 40723
 2007-08-02 05:48:35 +00:00
Evan Cheng
019ecf3b91 Can't handle offset and scale if rip-relative addressing is to be used. 
llvm-svn: 40703
 2007-08-01 23:46:47 +00:00
Evan Cheng
69bbf3ed2a Mac OS X X86-64 low 4G address not available. 
llvm-svn: 40702
 2007-08-01 23:46:10 +00:00
Evan Cheng
0fa6cdbff5 Mac OS X X86-64 low 4G address not available. 
llvm-svn: 40701
 2007-08-01 23:45:51 +00:00
Evan Cheng
b050c17b31 Some out operands were incorrectly specified as input operands. 
llvm-svn: 40697
 2007-08-01 23:07:38 +00:00
Evan Cheng
defb3b8389 Missing Requires. 
llvm-svn: 40691
 2007-08-01 21:42:24 +00:00
Evan Cheng
fb587a3851 Be more precise. 
llvm-svn: 40689
 2007-08-01 20:22:37 +00:00
Dan Gohman
8e7234519e Change a .size directive to use a tab instead of a space, for consistency. 
llvm-svn: 40672
 2007-08-01 14:42:30 +00:00
Evan Cheng
ab0a826b88 Indexed loads each has 2 outputs. 
llvm-svn: 40658
 2007-08-01 00:12:08 +00:00
Dan Gohman
e3464e6bec Change the x86 assembly output to use tab characters to separate the 
mnemonics from their operands instead of single spaces. This makes the
assembly output a little more consistent with various other compilers
(f.e. GCC), and slightly easier to read. Also, update the regression
tests accordingly.

llvm-svn: 40648
 2007-07-31 20:11:57 +00:00
Evan Cheng
3493ec0ce1 Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load ) 
llvm-svn: 40628
 2007-07-31 08:04:03 +00:00
Evan Cheng
e90ad40aa1 This isn't safe when there are uses of load's chain result. 
llvm-svn: 40617
 2007-07-31 06:21:44 +00:00
Dan Gohman
32ff2ca8a0 Use tabs more consistently in assembler pseudo-ops. 
llvm-svn: 40594
 2007-07-30 15:08:02 +00:00
Dan Gohman
23f9a3ad3b Fix the comment for getClosestTargetForJIT to reflect the fact that 
it does not have a Module parameter.

llvm-svn: 40590
 2007-07-30 14:58:59 +00:00
Dan Gohman
75473b49ea More explicit keywords. 
llvm-svn: 40589
 2007-07-30 14:51:59 +00:00
Evan Cheng
ff50061170 Vector fneg must be expanded into fsub -0.0, X. 
llvm-svn: 40586
 2007-07-30 07:51:22 +00:00
Christopher Lamb
919ce03da6 Change the x86 backend to use extract_subreg for truncation operations. Passes DejaGnu, SingleSource and MultiSource. 
llvm-svn: 40578
 2007-07-29 01:24:57 +00:00
Christopher Lamb
4120412f3e Add register info needed to use subreg sets on X86. 
llvm-svn: 40572
 2007-07-28 19:03:30 +00:00
Duncan Sands
35a77d857b Trampoline codegen support for X86-32. 
llvm-svn: 40566
 2007-07-27 20:02:49 +00:00
Dan Gohman
0252aa07ee Re-apply 40504, but with a fix for the segfault it caused in oggenc: 
Make the alignedload and alignedstore patterns always require 16-byte
alignment. This way when they are used in the "Fs" instructions, in which
a vector instruction is used for a scalar purpose, they can still require
the full vector alignment. And add a regression test for this.

llvm-svn: 40555
 2007-07-27 17:16:43 +00:00
Duncan Sands
e8bb2c6d32 Support for trampolines, except for X86 codegen which is 
still under discussion.

llvm-svn: 40549
 2007-07-27 12:58:54 +00:00
Evan Cheng
cb8f08ebca Reverting 40504 for now. It's breaking oggenc. 
llvm-svn: 40547
 2007-07-27 01:37:47 +00:00
Evan Cheng
ffa8cbd22b Make sure epilogue esp adjustment is placed before any terminator and pop instructions. 
llvm-svn: 40538
 2007-07-26 17:45:41 +00:00
Evan Cheng
ea037bffd2 Don't pollute the meaning of isUnpredicatedTerminator. 
llvm-svn: 40537
 2007-07-26 17:32:14 +00:00
Evan Cheng
9802b13b38 Minor bug. 
llvm-svn: 40535
 2007-07-26 17:02:45 +00:00
Dan Gohman
d3a062f01b In the .loc directive, print the fields as "debug" fields, so they 
don't get decorated as if for immediate fields for instructions.

llvm-svn: 40529
 2007-07-26 15:24:15 +00:00
Dan Gohman
1bfc3f0d09 Fix a whitespace difference between CMPSSrr and CMPSDrr. 
llvm-svn: 40528
 2007-07-26 15:11:50 +00:00
Christopher Lamb
9a0d88efde Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350 
llvm-svn: 40518
 2007-07-26 07:48:21 +00:00
Evan Cheng
413d222576 Same goes for constantpool, etc. 
llvm-svn: 40517
 2007-07-26 07:35:15 +00:00
Christopher Lamb
73c3cd47cc Add selection DAG nodes for subreg insert/extract. PR1350 
llvm-svn: 40516
 2007-07-26 07:34:40 +00:00
Dan Gohman
513dcba4f8 Remove X86ISD::LOAD_PACK and X86ISD::LOAD_UA and associated code from the 
x86 target, replacing them with the new alignment attributes on memory
references.

llvm-svn: 40504
 2007-07-26 00:31:09 +00:00
Evan Cheng
9588231d34 Mac OS X x86-64 lower 4G address is not available. 
llvm-svn: 40502
 2007-07-25 23:41:36 +00:00
Evan Cheng
75b396c3c9 Mac OS X should use 0x90 to fill in gaps to satisfy function alignment requirements. 
llvm-svn: 40501
 2007-07-25 23:36:05 +00:00
Evan Cheng
f34a0509c2 Functions with LinkOnce and weak linkage still need to be aligned. Doh. 
llvm-svn: 40499
 2007-07-25 22:28:16 +00:00
Dan Gohman
0fc4e0cf47 Don't ignore the return value of AsmPrinter::doInitialization and 
AsmPrinter::doFinalization.

llvm-svn: 40487
 2007-07-25 19:33:14 +00:00
Nick Lewycky
608fe6cf68 Fix debug info and globals filled with zeros. 
llvm-svn: 40483
 2007-07-25 03:48:45 +00:00
Anton Korobeynikov
e0344393bb Minor cleanup: 
- Split EH and debug infiormation
 - Make DwarfWriter more verbose in some cases

llvm-svn: 40481
 2007-07-25 00:06:28 +00:00
Dan Gohman
1444c5840b Add const to CanBeFoldedBy, CheckAndMask, and CheckOrMask. 
llvm-svn: 40480
 2007-07-24 23:00:27 +00:00
Dan Gohman
a2e07a38bc Use movaps to load a v4f32 build_vector of all-constant values into a 
register instead of loading each element individually.

llvm-svn: 40478
 2007-07-24 22:55:08 +00:00
Anton Korobeynikov
e8170a07f8 Heal EH handling stuff by emitting correct offsets to callee-saved registers. 
Pretty hackish, but code itself is dirty mess, so we won't make anything worse. :)

llvm-svn: 40472
 2007-07-24 21:07:39 +00:00
Dan Gohman
54b8032d64 Fix some uses of dyn_cast to be uses of cast. 
llvm-svn: 40443
 2007-07-23 20:24:29 +00:00
Dan Gohman
e2dcfd1516 Delete the svn:executable property on these files, which aren't executable. 
llvm-svn: 40441
 2007-07-23 19:26:08 +00:00
Bill Wendling
97342a9b0c Add missing SSE builtins: 
__builtin_ia32_cvtss2si64
    __builtin_ia32_cvttss2si64
    __builtin_ia32_cvtsi642ss
    __builtin_ia32_cvtsd2si64
    __builtin_ia32_cvttsd2si64
    __builtin_ia32_cvtsi642sd

llvm-svn: 40411
 2007-07-23 03:07:27 +00:00
Evan Cheng
53cb03b583 No more noResults. 
llvm-svn: 40132
 2007-07-21 00:34:19 +00:00
Evan Cheng
cdb4e7949f Added -print-emitted-asm to print out JIT generated asm to cerr. 
llvm-svn: 40123
 2007-07-20 21:56:13 +00:00
Evan Cheng
ac92a8149e Because we promote SSE logical ops and loads to v2i64, we often end up generate 
code that cross integer / floating point domains (e.g. generate pxor / pand for
logical ops on floating point value, movdqa to load / store floating point SSE
values). Given that, it's better to use movaps instead of movdqa and movups
instead of movdqu. They have the same latency but the "aps" variants are one
byte shorter.
If the domain crossing problem is a real performance issue, then we will have to
fix it with dynamic programming based isel.

llvm-svn: 40076
 2007-07-20 00:27:43 +00:00
Evan Cheng
f8d66a1eec Oops. These stores actually produce results. 
llvm-svn: 40074
 2007-07-20 00:20:46 +00:00
Evan Cheng
ba990bbc3f Fix custom lowering of SSE FXOR. 
llvm-svn: 40071
 2007-07-19 23:36:01 +00:00
Evan Cheng
f11cf2cad8 Fix patterns so we isel the xorps, etc. for floating pt logical SSE ops. DAG combiner may fold away the (bit_convert (load)). 
llvm-svn: 40070
 2007-07-19 23:34:10 +00:00
Evan Cheng
8312ed6f77 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
 2007-07-19 01:14:50 +00:00
Evan Cheng
45eb268032 Only adjust esp around calls in presence of alloca. 
llvm-svn: 40030
 2007-07-19 00:42:58 +00:00
Evan Cheng
30e121adf6 Only adjust esp around calls in presence of alloca. 
llvm-svn: 40028
 2007-07-19 00:42:05 +00:00
Evan Cheng
6a4fb5d62b Use MOV instead of LEA to restore ESP if callee-saved frame size is 0; if previous instruction updates esp, fold it in. 
llvm-svn: 40018
 2007-07-18 21:26:06 +00:00
Dan Gohman
2fc9d5171e Implement initial memory alignment awareness for SSE instructions. Vector loads 
and stores that have a specified alignment of less than 16 bytes now use
instructions that support misaligned memory references.

llvm-svn: 40015
 2007-07-18 20:23:34 +00:00
Evan Cheng
cee32b53a4 New entry. 
llvm-svn: 39998
 2007-07-18 08:21:49 +00:00
Evan Cheng
cf0fdbc249 Fold prologue esp update when possible. 
llvm-svn: 39984
 2007-07-17 21:26:42 +00:00
Evan Cheng
26f6d71d26 Make sure not to break eh_return. 
llvm-svn: 39978
 2007-07-17 18:40:47 +00:00
Evan Cheng
70b79bfa0e Update. 
llvm-svn: 39977
 2007-07-17 18:39:45 +00:00
Evan Cheng
46a48c5c3e Missed the case where alloca is used but the stack size (not including callee-saved portion) is zero. Thanks Dan. 
llvm-svn: 39974
 2007-07-17 18:03:34 +00:00
Evan Cheng
532b73311e Use push / pop for prologues and epilogues. 
llvm-svn: 39967
 2007-07-17 07:59:08 +00:00
Chris Lattner
71e2481181 no email addrs in file headers 
llvm-svn: 39962
 2007-07-17 05:56:43 +00:00
Dan Gohman
0ba554c0c8 Fix comments about vectors to use the current wording. 
llvm-svn: 39921
 2007-07-16 14:29:03 +00:00
Anton Korobeynikov
5635277c36 Long live the exception handling! 
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.

In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.

After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be 
thought as 'finished': I expect many small and not so small glitches
everywhere.

llvm-svn: 39855
 2007-07-14 14:06:15 +00:00
Evan Cheng
260a390840 Fix for PR1540: Specify F0, F1 are sub-registers of D0, etc. 
llvm-svn: 39843
 2007-07-13 23:55:50 +00:00
Dale Johannesen
469ed8e17e Skeleton of post-RA scheduler; doesn't do anything yet. 
Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.

llvm-svn: 39816
 2007-07-13 17:13:54 +00:00
Chris Lattner
7cba3578aa Fix CodeGen/Generic/print-arith-fp.ll on sparc (PR1551) 
llvm-svn: 39813
 2007-07-13 16:24:10 +00:00
Dale Johannesen
eb2c2823e3 ARM: make branch folder remove unconditional branches 
following jump tables that it earlier inserted.  This
would be OK on other targets but is needed for correctness
only on ARM (constant islands needs to find jump tables).

llvm-svn: 39782
 2007-07-12 16:45:35 +00:00
Chris Lattner
7eea439048 another missed SSE optimization 
llvm-svn: 39772
 2007-07-12 06:31:38 +00:00
Bruno Cardoso Lopes
27f5beafb2 Added support for Mips specific GAS directives 
Fixed print immediate 
Fixed Identation on MipsISelDAGToDAG.cpp

llvm-svn: 39764
 2007-07-11 23:24:41 +00:00
Bruno Cardoso Lopes
e21704313d Added support for framepointer 
Prologue/Epilogue support fp,ra save/restore and use the stack frame the right
way!

llvm-svn: 39763
 2007-07-11 23:21:31 +00:00
Bruno Cardoso Lopes
0ba66ea1dc Now that stack is represented the right way, LOA starts at 0 
llvm-svn: 39761
 2007-07-11 23:17:41 +00:00
Bruno Cardoso Lopes
be14b3c16c Fixed AddLiveOut issues 
FI's created the write way to represent Mips stack

llvm-svn: 39760
 2007-07-11 23:16:16 +00:00
Bruno Cardoso Lopes
bc1b534410 Removed unused immediate PatLeaf, fixed lui instruction 
llvm-svn: 39759
 2007-07-11 22:47:02 +00:00
Bruno Cardoso Lopes
a851ed6989 Added MipsMachineFunction class, to hold Mips dinamic stack info when inserting Prologue/Epilog 
llvm-svn: 39758
 2007-07-11 22:44:21 +00:00
Lauro Ramos Venancio
0ad4cde600 Handle packed structs in the CBackend. 
llvm-svn: 39752
 2007-07-11 19:56:53 +00:00
Dale Johannesen
cacc6dbeb6 Fix hang compiling TimberWolf (allow for islands 
of size other than 4).

llvm-svn: 39743
 2007-07-11 18:32:38 +00:00
Lauro Ramos Venancio
18fc770fd0 Assert when TLS is not implemented. 
llvm-svn: 39737
 2007-07-11 17:19:51 +00:00
Chris Lattner
ef484ab964 Fix an oversight: for modules with no other identifying target info, 
the sparc backend should be preferred when running on sparcs.

llvm-svn: 39142
 2007-07-11 16:32:10 +00:00
Evan Cheng
f6d010e93d Didn't mean the last commit. Revert. 
llvm-svn: 38515
 2007-07-10 22:00:16 +00:00
Dale Johannesen
ecef839eaa Fix fp_constant_op failure. 
llvm-svn: 38514
 2007-07-10 21:53:30 +00:00
Evan Cheng
05c784cc30 Update. 
llvm-svn: 38513
 2007-07-10 21:49:47 +00:00
Dale Johannesen
7325a82196 fix 80 columnn violations, increasing the world's 
pedantic satisfaction level.

llvm-svn: 38512
 2007-07-10 20:53:41 +00:00
Chris Lattner
abcdeef610 add a note 
llvm-svn: 38507
 2007-07-10 20:03:50 +00:00
Evan Cheng
abcf3842bb Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. 
llvm-svn: 38501
 2007-07-10 18:08:01 +00:00
Evan Cheng
0ab209fa54 Remove clobbersPred. 
llvm-svn: 38500
 2007-07-10 18:07:08 +00:00
Dan Gohman
928144b051 Define non-intrinsic instructions for vector min, max, sqrt, rsqrt, and rcp, 
in addition to the intrinsic forms. Add spill-folding entries for these new
instructions, and for the scalar min and max instrinsic instructions which
were missing. And add some preliminary ISelLowering code for using the new
non-intrinsic vector sqrt instruction, and fneg and fabs.

llvm-svn: 38478
 2007-07-10 00:05:58 +00:00
Dan Gohman
81cfdc2f19 Change getCopyToParts and getCopyFromParts to always use target-endian 
register ordering, for both physical and virtual registers. Update the PPC
target lowering for calls to expect registers for the call result to
already be in target order.

llvm-svn: 38471
 2007-07-09 20:59:04 +00:00
Chris Lattner
4810c53b05 The various "getModuleMatchQuality" implementations should return 
zero if they see a target triple they don't understand.

llvm-svn: 38463
 2007-07-09 17:25:29 +00:00
Evan Cheng
d9d3be078c No need for ccop anymore. 
llvm-svn: 37965
 2007-07-06 23:34:09 +00:00
Evan Cheng
92e624a6f7 Incorrect check. 
llvm-svn: 37962
 2007-07-06 23:23:19 +00:00
Evan Cheng
3b1b3eba6a Do away with ImmutablePredicateOperand. 
llvm-svn: 37961
 2007-07-06 23:22:46 +00:00
Evan Cheng
88acbacd35 isUnpredicatedTerminator should treat conditional branches as unpredicated terminator. 
llvm-svn: 37960
 2007-07-06 23:22:03 +00:00
Evan Cheng
776d4d6e11 Do away with ImmutablePredicateOperand. 
llvm-svn: 37959
 2007-07-06 23:21:02 +00:00
Rafael Espindola
7b3de98989 Add the byval attribute 
llvm-svn: 37940
 2007-07-06 10:57:03 +00:00
Evan Cheng
721b83bbe6 Print the s bit if the instruction is toggled to its CPSR setting form. 
llvm-svn: 37932
 2007-07-06 01:01:34 +00:00
Evan Cheng
c2c0b495ed PredicateDefOperand -> OptionalDefOperand. 
llvm-svn: 37931
 2007-07-06 01:00:49 +00:00
Evan Cheng
0adaea7381 Add OptionalDefOperand to stand for optionally defined result. 
llvm-svn: 37930
 2007-07-06 01:00:16 +00:00
Evan Cheng
96254545ae Initial ARM JIT support by Raul Fernandes Herbster. 
llvm-svn: 37926
 2007-07-05 21:15:40 +00:00
Anton Korobeynikov
e8215d1780 Proper flag __alloca call 
llvm-svn: 37923
 2007-07-05 20:36:08 +00:00
Evan Cheng
25450e48ca Doh 
llvm-svn: 37917
 2007-07-05 17:21:33 +00:00
Evan Cheng
04d3ebc699 Unbreak the build. 
llvm-svn: 37915
 2007-07-05 17:13:56 +00:00
Evan Cheng
a59422068f Unbreak the build. 
llvm-svn: 37914
 2007-07-05 17:13:19 +00:00
Gabor Greif
5f705671e4 Here is the bulk of the sanitizing. 
Almost all occurrences of "bytecode" in the sources have been eliminated.

llvm-svn: 37913
 2007-07-05 17:07:56 +00:00
Chris Lattner
ff6104f9d5 the arm backend is not building, temporarily disable it. 
llvm-svn: 37911
 2007-07-05 16:11:52 +00:00
Evan Cheng
be54fdf431 Reflects the chanegs made to PredicateOperand. 
llvm-svn: 37898
 2007-07-05 07:18:20 +00:00
Evan Cheng
3d2cfd8bb1 Added ARM::CPSR to represent ARM CPSR status register. 
llvm-svn: 37897
 2007-07-05 07:17:13 +00:00
Evan Cheng
2403cc41ea Unfortunately we now require C++ code to isel Bcc, conditional moves, etc. 
llvm-svn: 37896
 2007-07-05 07:15:27 +00:00
Evan Cheng
ef8a1bcbc3 Each ARM use predicate operand is now made up of two components. The new component is the CPSR register. 
llvm-svn: 37895
 2007-07-05 07:13:32 +00:00
Evan Cheng
4af116139b Added ARM::CPSR to represent ARM CPSR status register. 
llvm-svn: 37894
 2007-07-05 07:11:03 +00:00
Evan Cheng
9b7432c311 PPC conditional branch predicate does not change after isel. 
llvm-svn: 37893
 2007-07-05 07:09:50 +00:00
Evan Cheng
8b0cbaff08 - Added zero_reg def to stand for register 0. 
- Added two variants of PredicateOperand: ImmutablePredicateOperand, whose predicate does not change after isel; PredicateDefOperand, which represent a predicate defintion operand.

llvm-svn: 37892
 2007-07-05 07:09:09 +00:00
Evan Cheng
50367dfc3e Do not check isPredicated() on non-predicable instructions. 
llvm-svn: 37891
 2007-07-05 07:06:46 +00:00
Dale Johannesen
9072b65b0b Refactor X87 instructions. As a side effect, all 
their names are changed.

llvm-svn: 37876
 2007-07-04 21:07:47 +00:00
Bill Wendling
2e66551f22 Support generation of GR64 to MMX code in the JIT. 
llvm-svn: 37866
 2007-07-04 01:29:22 +00:00
Bill Wendling
3600c7a835 Allow a GR64 to be moved into an MMX register via the "movd" instruction. 
Still need to have JIT generate this code.

llvm-svn: 37863
 2007-07-04 00:19:54 +00:00
Dale Johannesen
0db4ba9f8a Some spacing fixes. Cosmetic. 
llvm-svn: 37853
 2007-07-03 17:07:33 +00:00
Dale Johannesen
7af19491d3 Fix for PR 1505 (and 1489). Rewrite X87 register 
model to include f32 variants.  Some factoring
improvments forthcoming.

llvm-svn: 37847
 2007-07-03 00:53:03 +00:00
Dan Gohman
eb46e6e629 Vector results may be returned in XMM0 and XMM1, not just XMM0. With 
the recent lowering changes, this allows types like <4 x double> to
be returned, using two vector registers.

llvm-svn: 37844
 2007-07-02 16:21:53 +00:00
John Criswell
57e5ed4b5a Convert .cvsignore files 
llvm-svn: 37801
 2007-06-29 16:35:07 +00:00
Evan Cheng
13b846b1ad Prevent PPC::BCC first operand, the PRED number, from being isel'd into a LI instruction. 
llvm-svn: 37790
 2007-06-29 01:25:06 +00:00
Evan Cheng
992f296a71 No vector fneg. 
llvm-svn: 37786
 2007-06-29 00:18:15 +00:00
Evan Cheng
e233ec5e46 Type of vector extract / insert index operand should be iPTR. 
llvm-svn: 37784
 2007-06-29 00:01:20 +00:00
Bill Wendling
cc1f4cafa2 Set implied features based upon the CPU's feature list. 
llvm-svn: 37768
 2007-06-27 23:34:06 +00:00
Dan Gohman
ce1bca0bf9 Remove a redundant newline in the asm output for ELF .rodata sections. 
llvm-svn: 37756
 2007-06-27 15:09:47 +00:00
Evan Cheng
5506831e5b Silence a warning. 
llvm-svn: 37737
 2007-06-26 18:31:22 +00:00
Dan Gohman
9cbc3fb1ab Revert the earlier change that removed the M_REMATERIALIZABLE machine 
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728
 2007-06-26 00:48:07 +00:00
Dan Gohman
354f02e03d Generalize MVT::ValueType and associated functions to be able to represent 
extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.

This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.

llvm-svn: 37719
 2007-06-25 16:23:39 +00:00
Dan Gohman
dc8a1730f7 Make minor adjustments to whitespace and comments to reduce differences 
between SSE1 instructions and their respective SSE2 analogues.

llvm-svn: 37718
 2007-06-25 15:44:19 +00:00
Dan Gohman
f40db01c32 Fix loadv2i32 to be loadv4i32, though it isn't actually used anywhere yet. 
llvm-svn: 37717
 2007-06-25 15:19:03 +00:00
Dan Gohman
d3b3703430 Say AT&T instead of Intel in the comments for AT&T support. 
llvm-svn: 37716
 2007-06-25 15:11:25 +00:00
Owen Anderson
89558a0db6 Fix the build. 
llvm-svn: 37705
 2007-06-22 16:59:54 +00:00
Dan Gohman
a62327ea40 Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from 
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.

llvm-svn: 37704
 2007-06-22 14:59:07 +00:00
Dale Johannesen
e1c767df50 Quote complex names for Darwin X86 and ARM. 
llvm-svn: 37700
 2007-06-22 00:54:56 +00:00
Evan Cheng
5da7b6f0fc Be more conservative of duplicating blocks. 
llvm-svn: 37669
 2007-06-19 23:55:02 +00:00
Evan Cheng
c49382e48f Allow predicated immediate ARM to ARM calls. 
llvm-svn: 37659
 2007-06-19 21:05:09 +00:00
Dan Gohman
485cb57eab Pass a SelectionDAG into SDNode::dump everywhere it's used, in prepration 
for needing the DAG node to print pre-legalize extended value types, and
to get better debug messages with target-specific nodes.

llvm-svn: 37656
 2007-06-19 14:13:56 +00:00
Chris Lattner
81e8a18e7c describe an argument, hide it. 
llvm-svn: 37650
 2007-06-19 05:46:06 +00:00
Dan Gohman
b60d8a92c9 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad 
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644
 2007-06-19 01:48:05 +00:00
Evan Cheng
12b3002673 Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit. 
llvm-svn: 37643
 2007-06-19 01:26:51 +00:00
Chris Lattner
e13fac05d7 If a function is vararg, never pass inreg arguments in registers. Thanks to 
Anton for half of this patch.

llvm-svn: 37641
 2007-06-19 00:13:10 +00:00
Evan Cheng
80f0d5ae45 Look for VECTOR_SHUFFLE that's identity operation on either LHS or RHS. This can happen before DAGCombiner catches it. 
llvm-svn: 37636
 2007-06-19 00:02:56 +00:00
Dan Gohman
bff1054303 Define the pushq instruction for x86-64. 
llvm-svn: 37625
 2007-06-18 14:12:56 +00:00
Bill Wendling
94f3474832 Revert patch. It regresses: 
define double @test2(i64 %A) {
   %B = bitcast i64 %A to double
   ret double %B
}

$ llvm-as < t.ll | llc -march=x86-64

before:

         .align  4
         .globl  _test2
_test2:
         movd %rdi, %xmm0
         ret

after:

_test2:
         subq $8, %rsp
         movq %rdi, (%rsp)
         movsd (%rsp), %xmm0
         addq $8, %rsp
         ret

llvm-svn: 37617
 2007-06-16 23:57:15 +00:00
Bill Wendling
a1f8f0aa97 Fix a failure to bit_convert from integer GPR to MMX register. 
llvm-svn: 37611
 2007-06-16 06:17:31 +00:00
Evan Cheng
e6d0631c68 Instructions with unique labels or embedded jumptables cannot be duplicated during ifcvt. 
llvm-svn: 37606
 2007-06-15 21:15:00 +00:00
Dan Gohman
2fd7d26df8 Rename MVT::getVectorBaseType to MVT::getVectorElementType. 
llvm-svn: 37579
 2007-06-14 22:58:02 +00:00
Dale Johannesen
62f49dd524 Do not treat FP_REG_KILL as terminator in branch analysis (X86). 
llvm-svn: 37578
 2007-06-14 22:03:45 +00:00
Dan Gohman
35f2b4d716 Add a target hook to allow loads from constant pools to be rematerialized, and an 
implementation for x86.

llvm-svn: 37576
 2007-06-14 20:50:44 +00:00
Dan Gohman
74c92798d8 Eliminate some redundant newlines in asm output. 
llvm-svn: 37574
 2007-06-14 15:00:27 +00:00
Christopher Lamb
68017d151b Add support to tablegen for specifying subregister classes on a per register class basis. 
llvm-svn: 37572
 2007-06-13 22:20:15 +00:00
Dale Johannesen
7e3253f115 Handle blocks with 2 unconditional branches in AnalyzeBranch. 
llvm-svn: 37571
 2007-06-13 17:59:52 +00:00
Chris Lattner
5f85da00bb fix x86-64 mmx calling convention for real, which passes in integer gprs. 
llvm-svn: 37534
 2007-06-09 05:08:10 +00:00
Chris Lattner
e965432273 fix mmx handling bug 
llvm-svn: 37533
 2007-06-09 05:01:50 +00:00
Evan Cheng
1a6c0341fd Add a utility routine to check for unpredicated terminator instruction. 
llvm-svn: 37528
 2007-06-08 21:59:56 +00:00
Lauro Ramos Venancio
ec8ae8443a Define AsmTransCBE for ARM. 
llvm-svn: 37527
 2007-06-08 21:06:23 +00:00
Evan Cheng
4c6df8ba37 Fix ARM condition code subsumission check. 
llvm-svn: 37517
 2007-06-08 09:14:47 +00:00
Evan Cheng
8eff719058 tBcc is not a barrier. 
llvm-svn: 37516
 2007-06-08 09:13:23 +00:00
Evan Cheng
9f23724d53 Stupid cut-n-paste bug caused me soooo much grief. Why wasn't there a compilation warning? I blame it on the FE folks. 
llvm-svn: 37484
 2007-06-07 01:37:54 +00:00
Evan Cheng
7b433a2954 Mark these instructions clobbersPred. They modify the condition code register. 
llvm-svn: 37468
 2007-06-06 10:17:05 +00:00
Evan Cheng
055d2fc508 Added clobbersPred. 
llvm-svn: 37466
 2007-06-06 10:15:28 +00:00
Bruno Cardoso Lopes
709699b8d3 Initial Mips support, here we go! =) 
- Modifications from the last patch included
  (issues pointed by Evan Cheng are now fixed).
- Added more MipsI instructions.
- Added more patterns to match branch instructions.

llvm-svn: 37461
 2007-06-06 07:42:06 +00:00
Evan Cheng
886c1f49ca Print predicate of the second instruction of the two-piece constant MI. 
llvm-svn: 37437
 2007-06-05 18:55:18 +00:00
Evan Cheng
820e352652 PIC label asm printing cosmetic changes. 
llvm-svn: 37434
 2007-06-05 07:36:38 +00:00
Evan Cheng
fdfe615197 Misuse of hasExternalLinkage(), should be checking isDeclaration(). 
llvm-svn: 37419
 2007-06-04 18:54:57 +00:00
Chris Lattner
8a38eebb69 update this entry, now that Anton implemented shift/and lowering for 
switches.  There is one really easy isel thing here with tst we are not
getting.

llvm-svn: 37400
 2007-06-02 18:45:14 +00:00
Evan Cheng
8a52b80cdf Opcode modifier s comes after condition code. e.g. addlts, not addslt. 
llvm-svn: 37388
 2007-06-01 20:51:29 +00:00
Evan Cheng
8589b95a33 Set ARM ifcvt duplication limit to 3 for now. 
llvm-svn: 37385
 2007-06-01 08:28:59 +00:00
Evan Cheng
c2fec89f4a Make jumptable non-predicable for now. 
llvm-svn: 37381
 2007-06-01 00:56:15 +00:00
Chris Lattner
72e07238ba Fix the asmprinter so that a globalvalue can specify an explicit alignment 
smaller than the preferred alignment, but so that the target can actually
specify a minimum alignment if needed.  This fixes some objc protocol
failures Devang tracked down.

llvm-svn: 37373
 2007-05-31 18:57:45 +00:00
Evan Cheng
3672d15956 For VFP2 fldm, fstm instructions, the condition code is printed after the address mode and size specifier. e.g. fstmiaseq, not fstmeqias. 
llvm-svn: 37351
 2007-05-29 23:34:19 +00:00
Evan Cheng
5df14b3451 For ldrb, strh, etc., the condition code is before the width specifier. e.g. streqh, not strheq. 
llvm-svn: 37349
 2007-05-29 23:32:06 +00:00
Evan Cheng
ff31eed2be Add missing const qualifiers. 
llvm-svn: 37342
 2007-05-29 18:42:18 +00:00
Evan Cheng
d8b25a2091 Add missing const qualifiers. 
llvm-svn: 37341
 2007-05-29 18:35:22 +00:00
Nicolas Geoffray
fff14eecb5 Implementation of compilation callback in PPC ELF32 
llvm-svn: 37340
 2007-05-29 16:33:18 +00:00
Dan Gohman
1b1932dda5 Add explicit qualification for namespace MVT members. 
llvm-svn: 37320
 2007-05-24 14:33:05 +00:00
Evan Cheng
80122ab529 Hooks for predication support. 
llvm-svn: 37308
 2007-05-23 07:22:05 +00:00
Evan Cheng
9f763bd3fd Rename a parameter. 
llvm-svn: 37307
 2007-05-23 07:21:11 +00:00
Dale Johannesen
738f94210c name change requested by review of previous patch 
llvm-svn: 37289
 2007-05-22 18:31:04 +00:00
Dale Johannesen
fe0fe14411 Make tail merging the default, except on powerPC. There was no prior art 
for a target-dependent default with a command-line override; this way
should be generally usable.

llvm-svn: 37285
 2007-05-22 17:14:46 +00:00
Bill Wendling
26eb9fb1e0 We only need to specify the most-implied feature for an architecture. 
llvm-svn: 37275
 2007-05-22 05:15:37 +00:00
Evan Cheng
f448047ec2 Fix some -march=thumb regressions. tBR_JTr is not predicable. 
llvm-svn: 37272
 2007-05-21 23:17:32 +00:00
Dale Johannesen
f01566b705 Use AXI3 not AXI2 for appropriate PIC PC-relative loads and stores. Cosmetic. 
llvm-svn: 37271
 2007-05-21 22:42:04 +00:00
Dale Johannesen
8f484d16b0 Add some patterns for PIC PC-relative loads and stores. 
llvm-svn: 37269
 2007-05-21 22:14:33 +00:00
Evan Cheng
d173398eee BlockHasNoFallThrough() now returns true if block ends with a return instruction; AnalyzeBranch() should ignore predicated instructionsd. 
llvm-svn: 37268
 2007-05-21 18:56:31 +00:00
Evan Cheng
3f386274c0 BlockHasNoFallThrough() now returns true if block ends with a return instruction. 
llvm-svn: 37266
 2007-05-21 18:44:17 +00:00
Dan Gohman
875f6bde73 Apply this patch: 
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070514/049845.html

llvm-svn: 37240
 2007-05-18 23:21:46 +00:00
Chris Lattner
a7834d79a0 add a note 
llvm-svn: 37239
 2007-05-18 20:18:14 +00:00
Dan Gohman
ec87afe526 Use MVT::FIRST_VECTOR_VALUETYPE and MVT::LAST_VECTOR_VALUETYPE. 
llvm-svn: 37234
 2007-05-18 18:44:07 +00:00
Evan Cheng
e875732104 Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code. 
llvm-svn: 37199
 2007-05-18 01:53:54 +00:00
Evan Cheng
03349b0344 Silence some compilation warnings. 
llvm-svn: 37197
 2007-05-18 01:19:57 +00:00
Evan Cheng
2fc338fac1 Set ARM if-conversion block size threshold to 10 instructions for now. 
llvm-svn: 37194
 2007-05-18 00:19:34 +00:00
Evan Cheng
90b0ff05f6 RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. 
llvm-svn: 37193
 2007-05-18 00:18:17 +00:00
Evan Cheng
234aab208a RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. 
llvm-svn: 37192
 2007-05-18 00:05:48 +00:00
Dale Johannesen
f66c6b85f1 More effective breakdown of memcpy into repeated load/store. These are now 
in the order lod;lod;lod;sto;sto;sto which means the load-store optimizer
has a better chance of producing ldm/stm.  Ideally you would get cooperation
from the RA as well but this is not there yet.

llvm-svn: 37179
 2007-05-17 21:31:21 +00:00
Evan Cheng
1b4af5f975 Fix a bogus check that prevented folding VECTOR_SHUFFLE to UNDEF; add an optimization to fold VECTOR_SHUFFLE to a zero vector. 
llvm-svn: 37173
 2007-05-17 18:45:50 +00:00
Evan Cheng
9c4e69e6e5 Added missing patterns for UNPCKH* and PUNPCKH*. 
llvm-svn: 37172
 2007-05-17 18:44:37 +00:00
Chris Lattner
9a53871650 This is the correct fix for PR1427. This fixes mmx-shuffle.ll and doesn't 
cause other regressions.

llvm-svn: 37160
 2007-05-17 17:13:13 +00:00
Anton Korobeynikov
375cafc275 Revert patch for PR1427. It breaks almost all vector tests. 
llvm-svn: 37159
 2007-05-17 07:50:14 +00:00
Chris Lattner
a18b7d76b3 add support for 128-bit add/sub on ppc64 
llvm-svn: 37158
 2007-05-17 06:52:46 +00:00
Chris Lattner
307a29e831 add support for 128-bit integer add/sub 
llvm-svn: 37154
 2007-05-17 06:35:11 +00:00
Chris Lattner
f65fe1d931 Fix PR1427 and test/CodeGen/X86/mmx-shuffle.ll 
llvm-svn: 37141
 2007-05-17 03:29:42 +00:00
Evan Cheng
dc9e574073 Remove. Not needed. 
llvm-svn: 37139
 2007-05-17 00:11:35 +00:00
Evan Cheng
4fa2db30d9 Default implementation of TargetInstrInfo::getBlockSize(). 
llvm-svn: 37138
 2007-05-16 23:53:44 +00:00
Evan Cheng
b09bf9914f ARM::tB is also predicable. 
llvm-svn: 37125
 2007-05-16 21:53:43 +00:00
Evan Cheng
973f4a19cb PredicateInstruction returns true if the operation was successful. 
llvm-svn: 37124
 2007-05-16 21:53:07 +00:00
Evan Cheng
30f3168b7b Add default implementation of PredicateInstruction(). 
llvm-svn: 37123
 2007-05-16 21:20:37 +00:00
Evan Cheng
48f230dcb0 Move if-conversion after all passes that may use register scavenger. 
llvm-svn: 37120
 2007-05-16 20:52:46 +00:00
Evan Cheng
f7a017dfa7 Removed isPredicable(). 
llvm-svn: 37119
 2007-05-16 20:50:23 +00:00
Evan Cheng
d3f1a259db Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable. 
llvm-svn: 37118
 2007-05-16 20:50:01 +00:00
Evan Cheng
0aced52f41 Added isPredicable bit to class Instruction. 
llvm-svn: 37117
 2007-05-16 20:47:01 +00:00
Evan Cheng
6943cefdcd Conditional branch is not a barrier. 
llvm-svn: 37103
 2007-05-16 07:45:54 +00:00
Chris Lattner
e67947b38f implement the missing maskmovq mmx intrinsic that akor hit. 
llvm-svn: 37100
 2007-05-16 06:08:17 +00:00
Evan Cheng
c149ee9f00 Fix comment. 
llvm-svn: 37098
 2007-05-16 05:14:06 +00:00
Evan Cheng
34928ae31f Hooks for predication support. 
llvm-svn: 37093
 2007-05-16 02:01:49 +00:00
Chris Lattner
4861b958f1 fix some subtle inline asm selection issues 
llvm-svn: 37067
 2007-05-15 01:31:05 +00:00
Evan Cheng
9f0ffdf4b3 Add PredicateOperand to all ARM instructions that have the condition field. 
llvm-svn: 37066
 2007-05-15 01:29:07 +00:00
Chris Lattner
ce20a357f1 fix subtle bugs in inline asm operand selection 
llvm-svn: 37065
 2007-05-15 01:28:08 +00:00
Lauro Ramos Venancio
c9c5da3939 Fix previous patch. GOTOFF can be used only when the symbol has internal 
linkage or hidden visibility.

llvm-svn: 37055
 2007-05-14 23:20:21 +00:00
Lauro Ramos Venancio
3ff817509f Optimize PIC implementation. GOTOFF can be used when the symbol is defined 
and used in the same module.

llvm-svn: 37044
 2007-05-14 18:46:23 +00:00
Lauro Ramos Venancio
c6d71fb584 Enable aliases on arm-linux. 
llvm-svn: 37042
 2007-05-14 18:32:56 +00:00
Chris Lattner
ecc23415ad Fix PR1413 
llvm-svn: 37023
 2007-05-13 22:19:27 +00:00
Anton Korobeynikov
7daaf71b29 More DWARF-related things cleanup: 
1. Fix PR1380
2. Apply Duncan's patch from PR1410
3. Insert workaround for "one personality function per module" as noted in PR1414
4. Emit correct debug frames for x86/linux. This partly fixes DebugInfo/2006-11-06-StackTrace.cpp: stack trace is
shown correctly, but arguments for function on top of stack are displayed incorrectly.

llvm-svn: 37015
 2007-05-12 22:36:25 +00:00
Chris Lattner
96e9e88590 add some notes 
llvm-svn: 36965
 2007-05-10 00:08:04 +00:00