Commit Graph

107968 Commits

Author SHA1 Message Date
Bob Haarman
37ff1dce27 [support] allocate exact size required for mapping in Support/Windws/Path.inc
Summary:
zturner suggested that mapped_file_region::init() on Windows seems to
create mappings that are larger than they need to be: Offset+Size
instead of Size. Indeed, that appears to be the case. I confirmed that
tests pass with mappings of just Size bytes, and fail with Size-1
bytes, suggesting that Size is indeed the correct value.

Reviewers: amccarth, zturner

Reviewed By: zturner

Subscribers: hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D39876

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317850 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 00:17:31 +00:00
Easwaran Raman
2f88f54e97 Add a wrapper function to set branch weights metadata.
Summary:
This wrapper checks if there is at least one non-zero weight before
setting the metadata.

Reviewers: davidxl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D39872

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317845 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 22:52:20 +00:00
Paul Robinson
4c7c4551f2 Fix out-of-order stepping behavior in programs with hoisted constants.
When the Constant Hoisting pass moves expensive constants into a
common block, it would assign a debug location equal to the last use
of that constant. While this is certainly intuitive, it places the
constant in an out-of-order location, according to the debug location
information. This produces out-of-order stepping when debugging
programs affected by this pass.

This patch creates in-order stepping behavior by merging the debug
locations for hoisted constants, and the new insertion point.

Patch by Matthew Voss!

Differential Revision: https://reviews.llvm.org/D38088

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317827 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 20:01:31 +00:00
Adrian Prantl
13c8bc9216 Preserve debug info when DAG-combinging (zext (truncate x)) -> (and x, mask).
rdar://problem/27139077

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317825 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 19:50:20 +00:00
Zachary Turner
eef29544df [Support] Make llvm::Error and Expected faster.
Whenever LLVM_ENABLE_ABI_BREAKING_CHECKS is enabled, which
is usually the case for example when asserts are enabled,
Error's destructor does some additional checking to make sure
that that it does not represent an error condition and that it
was checked.

However, this is -- by definition -- not the likely codepath.
Some profiling shows that at least with some compilers, simply
calling assertIsChecked -- in a release build with full
optimizations -- can account for up to 15% of the entire
runtime of the program, even though this function should almost
literally be a no-op.

The problem is that the assertIsChecked function can be considered
too big to inline depending on the compiler's inliner.  Since it's
unlikely to ever need to failure path though, we can move it out
of line and force it to not be inlined, so that the fast path
can be inlined.

In my test (using lld to link clang with CMAKE_BUILD_TYPE=Release
and LLVM_ENABLE_ASSERTIONS=ON), this reduces link time from 27
seconds to 23.5 seconds, which is a solid 15% gain.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317824 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 19:31:52 +00:00
Alexey Bataev
9daf9c5c89 [SLP] Fix PR23510: Try to find best possible vectorizable stores.
Summary:
The analysis of the store sequence goes in straight order - from the
first store to the last. Bu the best opportunity for vectorization will
happen if we're going to use reverse order - from last store to the
first. It may be best because usually users have some initialization
part + further processing and this first initialization may confuse
SLP vectorizer.

Reviewers: RKSimon, hfinkel, mkuper, spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D39606

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317821 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 19:07:16 +00:00
Sanjay Patel
114cb60a37 [Reassociate] don't name values "tmp"; NFCI
The toxic stew of created values named 'tmp' and tests that already have
values named 'tmp' and CHECK lines looking for values named 'tmp' causes
bad things to happen in our test line auto-generation scripts because it
wants to use 'TMP' as a prefix for unnamed values. Use less 'tmp' to 
avoid that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317818 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 18:14:24 +00:00
Mandeep Singh Grang
d28baf6183 [GlobalMerge] Stable sort GlobalSets to fix non-deterministic sort order
Summary: This fixes failure in CodeGen/AArch64/global-merge-group-by-use.ll uncovered by D39245.

Reviewers: ab, asl

Reviewed By: ab

Subscribers: aemerson, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D39635

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317817 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 18:05:17 +00:00
Nuno Lopes
06f6588caf revert r317812 [BasicAA] fix build break by converting the previously introduced assert into an if stmt
The code has a bug, but some tests regress.
I'll discuss this further on the mailing list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317815 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 17:35:36 +00:00
Nuno Lopes
d90f53e14a [BasicAA] fix build break by converting the previously introduced assert into an if stmt
Apparently V1Size == -1 doest imply V2Size == -1, which is a bit surprising to me.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317812 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 17:06:42 +00:00
Ulrich Weigand
b9cdeecf25 [SystemZ] Add support for the "o" inline asm constraint
We don't really need any special handling of "offsettable"
memory addresses, but since some existing code uses inline
asm statements with the "o" constraint, add support for this
constraint for compatibility purposes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317807 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 16:31:57 +00:00
Nuno Lopes
b0957fa675 [BasicAA] add assertion for corner case in aliasGEP()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317803 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 16:16:46 +00:00
Simon Dardis
5be95c6164 [mips] Correct microMIP's jump and add unconditional branch pseudo
Correct the definition of 'j' as being unavailable for microMIPS32R6 and
provide the 'b' assembly idiom for codegen purposes for microMIPS32r3.

Provide the necessary 'br' pattern for microMIPS32R6 as it now longer
incorrectly uses the 'j' instruction.

Reviewers: atanasyan

Differential Revision: https://reviews.llvm.org/D39741


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317801 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 16:02:18 +00:00
Alex Bradbury
d99baa702c [RISCV] MC layer support for the standard RV32A instruction set extension
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317791 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 15:00:03 +00:00
Simon Pilgrim
2ef1ea6408 Fix 'not all control paths return a value' warning on MSVC builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317790 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 14:56:17 +00:00
Dave Lee
9a5be1f566 Reapply: Allow yaml2obj to order implicit sections for ELF
Summary:
This change allows yaml input to control the order of implicitly added sections
(`.symtab`, `.strtab`, `.shstrtab`). The order is controlled by adding a
placeholder section of the given name to the Sections field.

This change is to support changes in D39582, where it is desirable to control
the location of the `.dynsym` section.

This reapplied version fixes:
  1. use of a function call within an assert
  2. failing lld test which has an unnamed section
  3. incorrect section count when given an unnamed section

Additionally, one more test to cover the unnamed section failure.

Reviewers: compnerd, jakehehrlich

Reviewed By: jakehehrlich

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D39749

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317789 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 14:53:43 +00:00
Alex Bradbury
f8c0f51efe [RISCV] MC layer support for the standard RV32M instruction set extension
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317788 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 14:46:30 +00:00
Andrew V. Tischenko
a4b0c616f6 Sched model improving on btver2: JFPU01 resource, vtestp* for xmm.
Differential Revision: https://reviews.llvm.org/D39802


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317785 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 14:19:59 +00:00
Andrew V. Tischenko
a5b99ed522 Add -print-schedule scheduling comments to inline asm.
Differential Revision: https://reviews.llvm.org/D39728


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317782 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 12:45:40 +00:00
Craig Topper
8334286d71 [X86] Give priority to EVEX FMA instructions over FMA4 instructions.
No existing processor has both so it doesn't really matter what we do here. But we were previously just relying on pattern order which gave FMA4 priority.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317775 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 08:26:26 +00:00
Vitaly Buka
be9a0aff00 Fix "default label in switch which covers all enumeration values" warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317771 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 07:46:13 +00:00
Sanjoy Das
5a61b4ed92 [SectionMemoryManager] Abstract out mmap, munmap, mprotect even more ; NFC
Summary:
This will let ORC JIT clients plug in custom logic for the mmap, munmap and
mprotect paths.

Reviewers: loladiro, dblaikie

Subscribers: mcrosier, llvm-commits

Differential Revision: https://reviews.llvm.org/D39300

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317770 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 06:31:33 +00:00
Craig Topper
7595e4c402 [X86] Make X86ISD::FMADDS3 isel patterns commutable.
This was missed when FMADDS3 was split from X86ISD::FMADDS3_RND.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317769 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 06:17:05 +00:00
Serguei Katkov
9c3564018d [GVN PRE] Patch the source for Phi node in PRE
We must patch all existing incoming values of Phi node,
otherwise it is possible that we can see poison
where program does not expect to see it.

This is the similar what GVN does.

The added test test/Transforms/GVN/PRE/pre-jt-add.ll shows an
example of wrong optimization done by jump threading due to
GVN PRE did not patch existing incoming value.

Reviewers: mkazantsev, wmi, dberlin, davide
Reviewed By: dberlin
Subscribers: efriedma, llvm-commits
Differential Revision: https://reviews.llvm.org/D39637


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317768 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 06:02:18 +00:00
Vedant Kumar
f361756cf3 [Coverage] Use the wrapped segment when a line has entry segments
We've worked around bugs in the frontend by ignoring the count from
wrapped segments when a line has at least one region entry segment.
Those frontend bugs are now fixed, so it's time to regenerate the
checked-in covmapping files and remove the workaround.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317761 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 02:33:43 +00:00
Marek Olsak
9960086c11 AMDGPU: Merge BUFFER_STORE_DWORD_OFFEN/OFFSET into x2, x4
Summary:
Only 56 shaders (out of 48486) are affected.

Totals from affected shaders (changed stats only):
SGPRS: 2420 -> 2460 (1.65 %)
Spilled VGPRs: 94 -> 112 (19.15 %)
Scratch size: 524 -> 528 (0.76 %) dwords per thread
Code Size: 187400 -> 184992 (-1.28 %) bytes

One DiRT Showdown shader spills 6 more VGPRs.
One Grid Autosport shader spills 12 more VGPRs.

The other 54 shaders only have a decrease in code size.
(I'm ignoring the SGPR noise)

Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D39012

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317755 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 01:52:55 +00:00
Marek Olsak
aa75d4aeb0 AMDGPU: Lower buffer store and atomic intrinsics manually
Summary:
Without this, SIMemoryLegalizer inserts s_waitcnt vmcnt(0) before every
buffer store and atomic instruction.

Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D39060

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317754 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 01:52:48 +00:00
Marek Olsak
e79e4fb9f1 AMDGPU: Merge BUFFER_LOAD_DWORD_OFFSET into x2, x4
Summary: Only 3 (out of 48486) shaders are affected.

Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D38951

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317753 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 01:52:36 +00:00
Marek Olsak
79b91c25d7 AMDGPU: Merge BUFFER_LOAD_DWORD_OFFEN into x2, x4
Summary:
-9.9% code size decrease in affected shaders.

Totals (changed stats only):
SGPRS: 2151462 -> 2170646 (0.89 %)
VGPRS: 1634612 -> 1640288 (0.35 %)
Spilled SGPRs: 8942 -> 8940 (-0.02 %)
Code Size: 52940672 -> 51727288 (-2.29 %) bytes
Max Waves: 373066 -> 371718 (-0.36 %)

Totals from affected shaders:
SGPRS: 283520 -> 302704 (6.77 %)
VGPRS: 227632 -> 233308 (2.49 %)
Spilled SGPRs: 3966 -> 3964 (-0.05 %)
Code Size: 12203080 -> 10989696 (-9.94 %) bytes
Max Waves: 44070 -> 42722 (-3.06 %)

Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D38950

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317752 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 01:52:30 +00:00
Marek Olsak
1a1019d019 AMDGPU: Merge S_BUFFER_LOAD_DWORD_IMM into x2, x4
Summary:
Only constant offsets (*_IMM opcodes) are merged.
It reuses code for LDS load/store merging.
It relies on the scheduler to group loads.

The results are mixed, I think they are mostly positive. Most shaders are
affected, so here are total stats only:

 SGPRS: 2072198 -> 2151462 (3.83 %)
 VGPRS: 1628024 -> 1634612 (0.40 %)
 Spilled SGPRs: 7883 -> 8942 (13.43 %)
 Spilled VGPRs: 97 -> 101 (4.12 %)
 Scratch size: 1488 -> 1492 (0.27 %) dwords per thread
 Code Size: 60222620 -> 52940672 (-12.09 %) bytes
 Max Waves: 374337 -> 373066 (-0.34 %)

There is 13.4% increase in SGPR spilling, DiRT Showdown spills a few more
VGPRs (now 37), but 12% decrease in code size.

These are the new stats for SGPR spilling. We already spill a lot SGPRs,
so it's uncertain whether more spilling will make any difference since
SGPRs are always spilled to VGPRs:

 SGPR SPILLING APPS   Shaders SpillSGPR AvgPerSh
 alien_isolation         2938       100      0.0
 batman_arkham_origins    589         6      0.0
 bioshock-infinite       1769         4      0.0
 borderlands2            3968        22      0.0
 counter_strike_glob..   1142        60      0.1
 deus_ex_mankind_div..   1410        79      0.1
 dirt-showdown            533         4      0.0
 dirt_rally               364      1163      3.2
 divinity                1052         2      0.0
 dota2                   1747         7      0.0
 f1-2015                  776      1515      2.0
 grid_autosport          1767      1505      0.9
 hitman                  1413       273      0.2
 left_4_dead_2           1762         4      0.0
 life_is_strange         1296        26      0.0
 mad_max                  358        96      0.3
 metro_2033_redux        2670        60      0.0
 payday2                 1362        22      0.0
 portal                   474         3      0.0
 saints_row_iv           1704         8      0.0
 serious_sam_3_bfe        392      1348      3.4
 shadow_of_mordor        1418        12      0.0
 shadow_warrior          3956       239      0.1
 talos_principle          324      1735      5.4
 thea                     172        17      0.1
 tomb_raider             1449       215      0.1
 total_war_warhammer      242        56      0.2
 ue4_effects_cave         295        55      0.2
 ue4_elemental            572        12      0.0
 unigine_tropics          210        56      0.3
 unigine_valley           278       152      0.5
 victor_vran             1262        84      0.1
 yofrankie                 82         2      0.0

Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D38949

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317751 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 01:52:23 +00:00
Marek Olsak
c94ae749c0 AMDGPU: Fold immediate offset into BUFFER_LOAD_DWORD lowered from SMEM
Summary:
-5.3% code size in affected shaders.

Changed stats only:

48486 shaders in 30489 tests
Totals:
SGPRS: 2086406 -> 2072430 (-0.67 %)
VGPRS: 1626872 -> 1627960 (0.07 %)
Spilled SGPRs: 7865 -> 7912 (0.60 %)
Code Size: 60978060 -> 60188764 (-1.29 %) bytes
Max Waves: 374530 -> 374342 (-0.05 %)

Totals from affected shaders:
SGPRS: 299664 -> 285688 (-4.66 %)
VGPRS: 233844 -> 234932 (0.47 %)
Spilled SGPRs: 3959 -> 4006 (1.19 %)
Code Size: 14905272 -> 14115976 (-5.30 %) bytes
Max Waves: 46202 -> 46014 (-0.41 %)

Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D38915

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317750 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 01:52:17 +00:00
Craig Topper
c8d83c1c39 [X86] Make sure we don't read too many operands from X86ISD::FMADDS1/FMADDS3 nodes when doing FNEG combine.
r317453 added new ISD nodes without rounding modes that were added to an existing if/else chain. But all the previous nodes handled there included a rounding mode. The final code after this if/else chain expected an extra operand that isn't present for the new nodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317748 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 01:06:47 +00:00
Rui Ueyama
84a0f53bf0 [FileOutputBuffer] Move factory methods out of their classes.
InMemoryBuffer and OnDiskBuffer classes have both factory methods and
public constructors, and that looks a bit odd. This patch makes factory
methods non-member function to fix it.

Differential Revision: https://reviews.llvm.org/D39693

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317739 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-08 22:57:48 +00:00
Craig Topper
20c675a70a [X86] X86MaskedGatherSDNode shouldn't inherit from MaskedGatherScatterSDNode
The classof implementation in MaskedGatherScatterSDNode doesn't consider X86MaskedGatherSDNode so its misleading.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317733 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-08 22:26:41 +00:00
Craig Topper
606231c1dd [X86] Preserve memory refs when folding loads into divides.
This is similar to what we already do for multiplies. Without this we can't unfold and hoist an invariant load.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317732 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-08 22:26:39 +00:00
Craig Topper
965ee90b44 [X86] Remove an if check on the result of a cast. NFC
cast takes a non-null input and produces a non-null output. So this if can never fail.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317731 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-08 22:26:37 +00:00
Adrian Prantl
d6200f6d89 Let replaceVTableHolder accept any type.
In Rust, a trait can be implemented for any type, and if a trait
object pointer is used for the type, then a virtual table will be
emitted for that trait/type combination.

We would like debuggers to be able to inspect trait objects, which
requires finding the concrete type associated with a given vtable.

This patch changes LLVM so that any type can be passed to
replaceVTableHolder. This allows the Rust compiler to emit the needed
debug info -- associating a vtable with the concrete type for which it
was emitted.

This is a DWARF extension: DWARF only specifies the meaning of
DW_AT_containing_type in one specific situation. This style of DWARF
extension is routine, though, and LLVM already has one such case for
DW_AT_containing_type.

Patch by Tom Tromey!

Differential Revision: https://reviews.llvm.org/D39503

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317730 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-08 22:04:43 +00:00
Dan Gohman
b5e0bec282 Add an @llvm.sideeffect intrinsic
This patch implements Chandler's idea [0] for supporting languages that
require support for infinite loops with side effects, such as Rust, providing
part of a solution to bug 965 [1].

Specifically, it adds an `llvm.sideeffect()` intrinsic, which has no actual
effect, but which appears to optimization passes to have obscure side effects,
such that they don't optimize away loops containing it. It also teaches
several optimization passes to ignore this intrinsic, so that it doesn't
significantly impact optimization in most cases.

As discussed on llvm-dev [2], this patch is the first of two major parts.
The second part, to change LLVM's semantics to have defined behavior
on infinite loops by default, with a function attribute for opting into
potential-undefined-behavior, will be implemented and posted for review in
a separate patch.

[0] http://lists.llvm.org/pipermail/llvm-dev/2015-July/088103.html
[1] https://bugs.llvm.org/show_bug.cgi?id=965
[2] http://lists.llvm.org/pipermail/llvm-dev/2017-October/118632.html

Differential Revision: https://reviews.llvm.org/D38336


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317729 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-08 21:59:51 +00:00
Reid Kleckner
bfc1e953bc Revert "Correct dwarf unwind information in function epilogue for X86"
This reverts r317579, originally committed as r317100.

There is a design issue with marking CFI instructions duplicatable. Not
all targets support the CFIInstrInserter pass, and targets like Darwin
can't cope with duplicated prologue setup CFI instructions. The compact
unwind info emission fails.

When the following code is compiled for arm64 on Mac at -O3, the CFI
instructions end up getting tail duplicated, which causes compact unwind
info emission to fail:
  int a, c, d, e, f, g, h, i, j, k, l, m;
  void n(int o, int *b) {
    if (g)
      f = 0;
    for (; f < o; f++) {
      m = a;
      if (l > j * k > i)
        j = i = k = d;
      h = b[c] - e;
    }
  }

We get assembly that looks like this:
; BB#1:                                 ; %if.then
Lloh3:
	adrp	x9, _f@GOTPAGE
Lloh4:
	ldr	x9, [x9, _f@GOTPAGEOFF]
	mov	 w8, wzr
Lloh5:
	str		wzr, [x9]
	stp	x20, x19, [sp, #-16]!   ; 8-byte Folded Spill
	.cfi_def_cfa_offset 16
	.cfi_offset w19, -8
	.cfi_offset w20, -16
	cmp		w8, w0
	b.lt	LBB0_3
	b	LBB0_7
LBB0_2:                                 ; %entry.if.end_crit_edge
Lloh6:
	adrp	x8, _f@GOTPAGE
Lloh7:
	ldr	x8, [x8, _f@GOTPAGEOFF]
Lloh8:
	ldr		w8, [x8]
	stp	x20, x19, [sp, #-16]!   ; 8-byte Folded Spill
	.cfi_def_cfa_offset 16
	.cfi_offset w19, -8
	.cfi_offset w20, -16
	cmp		w8, w0
	b.ge	LBB0_7
LBB0_3:                                 ; %for.body.lr.ph

Note the multiple .cfi_def* directives. Compact unwind info emission
can't handle that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317726 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-08 21:31:14 +00:00
Alex Bradbury
81fd138d35 Set hasSideEffects=0 for PHI and fix affected passes
Previously, hasSideEffects was ? for TargetOpcode::PHI and would be inferred 
as 1. D37065 sets the previously inferred properties explicitly. This patch sets 
hasSideEffects=0 for PHI, as it is for G_PHI. MachineInstr::isSafeToMove has 
been updated so it still returns false for PHI.

Additionally, HexagonBitSimplify relied on a PHI node having the 
hasUnmodeledSideEffects property. This patch fixes that assumption.

Differential Revision: https://reviews.llvm.org/D37097


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317721 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-08 20:19:16 +00:00
Craig Topper
fb2f519709 [X86] Correct the implementation of BEXTR load folding to use the shift as the parent node and pass a separate root.
We were calling tryFoldLoad with the 'and' node was the root and parent node of the load. But the parent of the load should be the shift that proceeds the and. While the and node is correctly the root node.

To fix this I had to make tryFoldLoad take a separate use and root input. I've added a convenience version with the old signature to avoid updating the other call sites.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317720 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-08 20:17:33 +00:00
Sam Clegg
40ce9d17b1 [WebAssembly] Update test expectations
I believe these were fixed in rL317707

Differential Revision: https://reviews.llvm.org/D39813

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317718 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-08 20:14:06 +00:00
Teresa Johnson
dcf64df89b [ThinLTO] Ensure sanitizer passes are run
Summary:
In ThinLTO compilation, we exit populateModulePassManager early and
were not adding PM extension passes meant to run at the end of the
pipeline. This includes sanitizer passes. Add these passes before
the early exit.

A test will be added to projects/compiler-rt.

Reviewers: pcc

Subscribers: mehdi_amini, inglorion, llvm-commits

Differential Revision: https://reviews.llvm.org/D39565

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317714 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-08 19:45:52 +00:00
Craig Topper
9799e6facc [X86] Don't call validateInstruction from MatchAndEmitInstruction when MatchingInlineAsm is set. The MCInst won't be populated.
Without this we can't parse gather instructions in ms inline asm blocks. The validateInstruction function was introduced in r316700 to check gather constraints.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317713 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-08 19:38:48 +00:00
Craig Topper
ca3cf87eee [ValueTracking] Use APInt::isNullValue/isOneValue which are more efficient for large APInts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317712 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-08 19:38:45 +00:00
Dan Gohman
40486d7dcf [WebAssembly] Call signExtend to get sign extended register
Patch by Jatin Bhateja!

Differential Revision: https://reviews.llvm.org/D39529


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317710 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-08 19:24:21 +00:00
Dan Gohman
8e0d3d4cd7 [WebAssembly] Revise the strategy for inline asm.
Previously, an "r" constraint would mean the compiler provides a value
on WebAssembly's operand stack. This was tricky to use properly,
particularly since it isn't possible to declare a new local from within
an inline asm string.

With this patch, "r" provides the value in a WebAssembly local, and the
local index is provided to the inline asm string. This requires inline
asm to use get_local and set_local to read the register. This does
potentially result in larger code size, however inline asm should
hopefully be quite rare in WebAssembly.

This also means that the "m" constraint can no longer be supported, as
WebAssembly has nothing like a "memory operand" that includes an
implicit get_local.

This fixes PR34599 for the wasm32-unknown-unknown-wasm target (though
not for the ELF target).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317707 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-08 19:18:08 +00:00
Adrian McCarthy
cf89e1c2fe NFC: Rename MCSafeSEHFragment to MCSymbolIdFragment
Summary:
This fragment emits a symbol ID and will be useful for more than just Safe SEH
tables (e.g., I plan to re-use it for Control Flow Guard tables).  This is
simply a rename refactor.

Reviewers: rnk

Subscribers: llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D39770

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317703 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-08 18:57:02 +00:00
Adrian Prantl
27b6b3117f Handle inlined variables in SelectionDAGBuilder::EmitFuncArgumentDbgValue().
In 2010 a commit with no testcase and no further explanation
explicitly disabled the handling of inlined variables in
EmitFuncArgumentDbgValue(). I don't think there is a good reason for
this any more and re-enabling this adds debug locations for variables
associated with an LLVM function argument in functions that are
inlined into the first basic block. The only downside of doing this is
that we may insert a DBG_VALUE before the inlined scope, but (1) this
could be filtered out later, and (2) LiveDebugValues will not
propagate it into subsequent basic blocks if they don't dominate the
variable's lexical scope, so this seems like a small price to pay.

rdar://problem/26228128

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317702 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-08 18:27:13 +00:00
Alex Bradbury
da781c7295 [RISCV] Initial support for function calls
Note that this is just enough for simple function call examples to generate 
working code. Support for varargs etc follows in future patches.

Differential Revision: https://reviews.llvm.org/D29936


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317691 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-08 13:41:21 +00:00