Commit Graph

35631 Commits

Author SHA1 Message Date
Craig Topper
766278ea84 Replace dyn_cast with isa in places that weren't using the returned value for more than a boolean check. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253441 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-18 07:07:59 +00:00
Rafael Espindola
cfc74b78b1 Stop producing .data.rel sections.
If a section is rw, it is irrelevant if the dynamic linker will write to
it or not.

It looks like llvm implemented this because gcc was doing it. It looks
like gcc implemented this in the hope that it would put all the
relocated items close together and speed up the dynamic linker.

There are two problem with this:
* It doesn't work. Both bfd and gold will map .data.rel to .data and
  concatenate the input sections in the order they are seen.
* If we want a feature like that, it can be implemented directly in the
  linker since it knowns where the dynamic relocations are.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253436 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-18 06:02:15 +00:00
Quentin Colombet
9eaef59528 [ARM] Enable shrink-wrapping by default.
Differential Revision: http://reviews.llvm.org/D14357

rdar://problem/21942589


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253411 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-18 00:40:54 +00:00
Simon Pilgrim
5dff218941 [X86][AVX512] Added AVX512 SHUFP*/VPERMILP* shuffle decode comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253396 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-17 23:29:49 +00:00
Simon Pilgrim
ae2a51e7ef [X86][AVX512] Added support for AVX512 UNPCK shuffle decode comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253391 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-17 22:35:45 +00:00
Reid Kleckner
595419dcfa [WinEH] Move WinEHFuncInfo from MachineModuleInfo to MachineFunction
Summary:
Now that there is a one-to-one mapping from MachineFunction to
WinEHFuncInfo, we don't need to use a DenseMap to select the right
WinEHFuncInfo for the current funclet.

The main challenge here is that X86WinEHStatePass is an IR pass that
doesn't have access to the MachineFunction. I gave it its own
WinEHFuncInfo object that it uses to calculate state numbers, which it
then throws away. As long as nobody creates or removes EH pads between
this pass and SDAG construction, we will get the same state numbers.

The other thing X86WinEHStatePass does is to mark the EH registration
node. Instead of communicating which alloca was the registration through
WinEHFuncInfo, I added the llvm.x86.seh.ehregnode intrinsic.  This
intrinsic generates no code and simply marks the alloca in use.

Reviewers: JCTremoulet

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D14668

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253378 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-17 21:10:25 +00:00
Charlie Turner
7a016a152d [ARM] Don't pessimize i32 vselect.
The underlying issues surrounding codegen for 32-bit vselects have been resolved. The pessimistic costs for 64-bit vselects remain due to the bad
scalarization that is still happening there.

I tested this on A57 in T32, A32 and A64 modes. I saw no regressions, and some improvements.

From my benchmarks, I saw these improvements in A57 (T32)
spec.cpu2000.ref.177_mesa 5.95%
lnt.SingleSource/Benchmarks/Shootout/strcat 12.93%
lnt.MultiSource/Benchmarks/MiBench/telecomm-CRC32/telecomm-CRC32 11.89%

I also measured A57 A32, A53 T32 and A9 T32 and found no performance regressions. I see much bigger wins in third-party benchmarks with this change

Differential Revision: http://reviews.llvm.org/D14743



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253349 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-17 17:25:15 +00:00
Ahmed Bougacha
03629a3cf4 [AArch64] Promote f16 SELECT_CC CC operands when op is legal.
SELECT_CC has the nasty property of having operands with unrelated
types. So if you do something like:

  f32 = select_cc f16, f16, f32, f32, cc

You'd only look for the action for <select_cc, f32>, but never f16.
If the types are all legal, but the op isn't (as for f16 on AArch64,
or for f128 on x86_64/AArch64?), then you get into trouble.
For f128, we have softenSetCCOperands to handle this case.

Similarly, for f16, we can directly promote the CC operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253344 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-17 16:45:40 +00:00
Bradley Smith
50827137f2 [ARM] Default to ARMv4t in favour of adding Other to ARMArch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253335 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-17 13:38:29 +00:00
Charlie Turner
377cc21860 [ARM] Match VABDL from log2 shuffles.
Differential Revision: http://reviews.llvm.org/D14664



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253334 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-17 13:21:35 +00:00
Zlatko Buljan
3a6c5daba9 [mips][microMIPS] Implement EXTP, EXTPDP, EXTPDPV, EXTPV, EXTR[_RS].W, EXTR_S.H, EXTRV[_RS].W and EXTRV_S.H instructions
Differential Revision: http://reviews.llvm.org/D14174


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253332 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-17 12:54:15 +00:00
Bradley Smith
38bd0daf4d [ARM] Properly initialize ARMArch in the ARM subtarget
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253331 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-17 11:57:33 +00:00
Zlatko Buljan
affe4356e9 [mips][microMIPS] Implement SUBQ[_S].PH, SUBQ_S.W, SUBQH[_R].PH, SUBQH[_R].W, SUBU[_S].PH, SUBU[_S].QB and SUBUH[_R].QB instructions
Differential Revision: http://reviews.llvm.org/D14114


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253329 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-17 10:11:22 +00:00
Oliver Stannard
99ab11202f [Assembler] Make fatal assembler errors non-fatal
Currently, if the assembler encounters an error after parsing (such as an
out-of-range fixup), it reports this as a fatal error, and so stops after the
first error. However, for most of these there is an obvious way to recover
after emitting the error, such as emitting the fixup with a value of zero. This
means that we can report on all of the errors in a file, not just the first
one. MCContext::reportError records the fact that an error was encountered, so
we won't actually emit an object file with the incorrect contents.

Differential Revision: http://reviews.llvm.org/D14717



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253328 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-17 10:00:43 +00:00
Zlatko Buljan
e0d7dbe7db [mips][microMIPS] Implement PRECEQ.W.PHL, PRECEQ.W.PHR, PRECEQU.PH.QBL, PRECEQU.PH.QBLA, PRECEQU.PH.QBR, PRECEQU.PH.QBRA, PRECEU.PH.QBL, PRECEU.PH.QBLA, PRECEU.PH.QBR and PRECEU.PH.QBRA instructions
Differential Revision: http://reviews.llvm.org/D14279


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253326 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-17 09:43:29 +00:00
Jay Foad
6c42346ff4 Fix typos in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253324 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-17 08:54:53 +00:00
Rafael Espindola
8dcaa9fb08 Drop prelink support.
The way prelink used to work was

* The compiler decides if a given section only has relocations that
are know to point to the same DSO. If so, it names it
.data.rel.ro.local<something>.
* The static linker puts all of these together.
* The prelinker program assigns addresses to each library and resolves
the local relocations.

There are many problems with this:
* It is incompatible with address space randomization.
* The information passed by the compiler is redundant. The linker
knows if a given relocation is in the same DSO or not. If could sort
by that if so desired.
* There are newer ways of speeding up DSO (gnu hash for example).
* Even if we want to implement this again in the compiler, the previous
  implementation is pretty broken. It talks about relocations that are
  "resolved by the static linker". If they are resolved, there are none
  left for the prelinker. What one needs to track is if an expression
  will require only dynamic relocations that point to the same DSO.

At this point it looks like the prelinker is an historical curiosity.
For example, fedora has retired it because it failed to build for two
releases
(http://pkgs.fedoraproject.org/cgit/prelink.git/commit/?id=eb43100a8331d91c801ee3dcdb0a0bb9babfdc1f)

This patch removes support for it. That is, it stops printing the
".local" sections.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253280 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-17 00:51:23 +00:00
Derek Schuff
36eebaa409 [WebAssembly] Fix printing of global operands
This was regressed in r252656 which wasn't quite NFC. Instead of using a
custom instruction as before, use a pattern to select CONST_I32 for the
global addrs.

Differential Revision: http://reviews.llvm.org/D14587

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253276 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-17 00:20:44 +00:00
Simon Pilgrim
3305a140fd [X86][SSE] Merged BLEND shuffle decode comments. NFC.
Now that we can recognise different vector sizes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253268 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-16 23:03:18 +00:00
Simon Pilgrim
7dd95ec212 [X86][SSE] Merged ALIGNR/SLLDQ/SRLDQ shuffle decode comments. NFC.
Now that we can recognise different vector sizes - will make future AVX512 additions easier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253266 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-16 22:54:41 +00:00
Simon Pilgrim
f780acfa6b [X86][SSE] Merged SHUF/PERM shuffle decode comments. NFC.
Now that we can recognise different vector sizes - will make future AVX512 additions easier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253260 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-16 22:39:27 +00:00
Simon Pilgrim
e80993a4e4 [X86][SSE] Merged UNPCK shuffle decode comments. NFC.
Now that we can recognise different vector sizes - will make future AVX512 additions easier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253258 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-16 22:21:10 +00:00
Derek Schuff
1a4e019fc0 [WebAssembly] Fix function return type printing
Summary:
Previously return type information for a function was derived from
return dag nodes. But this didn't work for dags with != return node. So
instead compute it directly from the LLVM function as is done for imports.

Differential Revision: http://reviews.llvm.org/D14593

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253251 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-16 21:12:41 +00:00
Derek Schuff
8f9915e419 [WebAssembly] Reverse the order of operands for br_if
Summary: This is to match the new version in the spec

Reviewers: sunfish

Subscribers: jfb, llvm-commits, dschuff

Differential Revision: http://reviews.llvm.org/D14519

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253249 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-16 21:04:51 +00:00
Kit Barton
90858d35f8 Find available scratch register to use in function prologue and epilogue as part of shrink wrapping.
Phabricator: http://reviews.llvm.org/D13955

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253247 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-16 20:22:15 +00:00
Reid Kleckner
e689ed5002 [WinEH] Don't let UnwindHelp alias the return address
On top of that, don't bother allocating and initializing UnwindHelp if
we don't have any funclets. Currently we always use RBP as our frame
pointer when funclets are present, so this change makes it impossible to
come here without any fixed stack objects.

Fixes PR25533.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253245 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-16 18:47:25 +00:00
Reid Kleckner
0929f1339a Use the subtarget reference that we already have
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253244 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-16 18:47:12 +00:00
Vasileios Kalintiris
a90c8e5d67 [mips] Disable code generation through FastISel for MIPS32R6.
Reviewers: dsanders

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D14708

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253225 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-16 17:05:01 +00:00
Petr Pavlu
1890cef0c5 [ARM] Prevent use of a value pointed by end() iterator when placing a jump table
Function ARMConstantIslands::doInitialJumpTablePlacement() iterates over all
basic blocks in a machine function. It calls `MI = MBB.getLastNonDebugInstr()`
to get the last instruction in each block and then uses MI->getOpcode() to
decide what to do. If getLastNonDebugInstr() returns MBB.end() (for example,
when the block does not contain any instructions) then calling getOpcode() on
this value is incorrect. Avoid this problem by checking the result of
getLastNonDebugInstr().

Differential Revision: http://reviews.llvm.org/D14694


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253222 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-16 16:41:13 +00:00
Oliver Stannard
20bb042d74 [ARM,AArch64] Store source location of asm constant pool entries
Storing the source location of the expression that created a constant pool
entry allows us to emit better error messages if we later discover that the
expression cannot be represented by a relocation.

Differential Revision: http://reviews.llvm.org/D14646



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253220 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-16 16:25:47 +00:00
Oliver Stannard
1b10e7aa06 [ARM,AArch64] Store source location for values in assembly files
The MCValue class can store a SMLoc to allow better error messages to be
emitted if an error is detected after parsing. The ARM and AArch64 assembly
parsers were not setting this, so error messages did not have source
information.

Differential Revision: http://reviews.llvm.org/D14645



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253219 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-16 16:22:47 +00:00
Dan Gohman
e5484b4329 [WebAssembly] Prototype passes for register coloring and register stackifying.
These passes are not yet enabled by default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253217 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-16 16:18:28 +00:00
Artyom Skrobov
4c351fd4e8 Handle ARMv6KZ naming
Summary:
* ARMv6KZ is the "canonical" name, given in the ARMARM
* ARMv6Z is an "official abbreviation" for it, mentioned in the ARMARM
* ARMv6ZK is a popular misspelling, which we should support as an alias.

The patch corrects the handling of the names.

Functional changes:
* ARMv6Z no longer treated as an architecture in its own right
* ARMv6ZK renamed to ARMv6KZ, accepting ARMv6ZK as an alias
* arm1176jz-s and arm1176jzf-s recognized as ARMv6ZK, instead of ARMv6K
* default ARMv6K CPU changed to arm1176j-s

Reviewers: rengolin, logan, compnerd

Subscribers: aemerson, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D14568

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253206 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-16 14:05:32 +00:00
Bradley Smith
7c1b77248b [ARM] Introduce subtarget features per ARM architecture.
This allows for accurate architecture targeting as well as removing
duplicate information (hardcoded feature strings) from MCTargetDesc.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253196 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-16 11:10:19 +00:00
James Molloy
61639fb856 Properly check if a CMPZ node is in fact comparing against zero
This was left implicit and never ever checked, which means we could have a CMPZ against some non-zero value and we were carrying on with BFI conversion regardless.

Caught by Oliver Stannard using csmith; regression test added.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253195 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-16 10:49:25 +00:00
Oliver Stannard
f88d08f7c5 [AArch64] ldr= pseudo-instruction silently ignored if register invalid
The AArch64 assembler was silently ignoring instructions like this:
  ldr foo, =bar

AArch64AsmParser::parseOperand was returning true as the parse failed, but was
not calling AArch64AsmParser::Error to report this to the user, so the
instruction was ignored without printing an error message.

Differential Revision: http://reviews.llvm.org/D14651



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253193 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-16 10:25:19 +00:00
Igor Breger
99b62327bf AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP instructions.
Differential Revision: http://reviews.llvm.org/D14322

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253185 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-16 07:22:00 +00:00
Dan Gohman
284e00c04e [WebAssembly] Use tabs instead of spaces in assembly output.
This seems to be the most popular convention among the other backends.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253172 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-15 15:34:19 +00:00
Simon Pilgrim
8adc1eabfb [X86][SSE] Tidyup with implicit SDValue bool check. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253171 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-15 14:57:07 +00:00
Igor Breger
9b249d9b29 Revert r253160.
It broke layering violation. Reproducible with BUILD_SHARED_LIBS=ON.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253163 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-15 12:19:11 +00:00
Igor Breger
42aedb2949 AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP instructions.
Differential Revision: http://reviews.llvm.org/D14322

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253160 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-15 07:23:13 +00:00
Dan Gohman
1fbb445098 [WebAssembly] Minor code simplification. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253150 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-14 23:28:15 +00:00
Dan Gohman
ccb28273c8 [WebAssembly] Support signext, zeroext, and several other function attributes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253148 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-14 23:15:41 +00:00
Akira Hatanaka
55c0268714 Reduce the size of MCRelaxableFragment.
MCRelaxableFragment previously kept a copy of MCSubtargetInfo and
MCInst to enable re-encoding the MCInst later during relaxation. A copy
of MCSubtargetInfo (instead of a reference or pointer) was needed
because the feature bits could be modified by the parser.

This commit replaces the MCSubtargetInfo copy in MCRelaxableFragment
with a constant reference to MCSubtargetInfo. The copies of
MCSubtargetInfo are kept in MCContext, and the target parsers are now
responsible for asking MCContext to provide a copy whenever the feature
bits of MCSubtargetInfo have to be toggled.
 
With this patch, I saw a 4% reduction in peak memory usage when I
compiled verify-uselistorder.lto.bc using llc.

rdar://problem/21736951

Differential Revision: http://reviews.llvm.org/D14346


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253127 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-14 06:35:56 +00:00
Akira Hatanaka
ff528b6f03 [MCTargetAsmParser] Move the member varialbes that reference
MCSubtargetInfo in the subclasses into MCTargetAsmParser and define a
member function getSTI.

This is done in preparation for making changes to shrink the size of
MCRelaxableFragment. (see http://reviews.llvm.org/D14346).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253124 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-14 05:20:05 +00:00
Eric Christopher
d1b0795570 Add MMX to the 3dnow enum and propagate changes around. This makes
it somewhat more consistent with how the feature is used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253122 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-14 03:04:00 +00:00
Justin Bogner
2814318a45 AArch64: Default AArch64Subtarget::ReserveX18 to true on darwin
Darwin reserves x18, so it's never ABI compliant to generate code that
uses it. Set the default value based on the OS part of the triple
rather than forcing front-ends to set the +reserve-x18 target feature
in order to build correct code for Darwin.

This will make r243310 redundant, so I'll revert that shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253102 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-13 23:05:46 +00:00
Colin LeMahieu
3b47b1f0e2 [Hexagon] Fixing memory leak during relaxation by allocating MCInst in MCContext.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253090 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-13 21:45:50 +00:00
Reid Kleckner
c6477179dd [WinEH] Fix ESP management with 32-bit __CxxFrameHandler3
The C++ EH personality automatically restores ESP from the C++ EH
registration node after a catchret. I mistakenly thought it was like
SEH, which does not restore ESP.

It makes sense for C++ EH to differ from SEH here because SEH does not
use funclets for catches, and does not allow catching inside of finally.
C++ EH may need to unwind through multiple catch funclets and eventually
catchret to some outer funclet. Therefore, the runtime has to keep track
of which ESP to use with catchret, rather than having the compiler
reload it manually.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253084 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-13 21:27:00 +00:00
Dan Gohman
061211b22d [WebAssembly] Rename the Const instructions to be upper-case too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253072 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-13 20:27:45 +00:00