* Outside of 64b mode, EVEX.R', EVEX.R, EVEX.X and EVEX.B are
ignored. (handled in ILD C code). If not set, those fields are
zero.
* MASK_B ignores REXB (EVEX.B and VEX.B). It is used in EVEX and VEX
mask encodings. SDM(062) states EVEX.B is ignored but omits
mention of VEX.B.
* In 64b mode, VEX.vvvv[3] must be 1 for mask registers; EVEX.vvvv
is not used for mask registers. In non-64b mode VEX.vvvv[3] is
ignored for mask regs.
* VEX.R must be 1 for mask registers.
Change-Id: I209a62c7e27778ca0981e342cb3143f367409abf
(cherry picked from commit c41fb5e8f6b77524b94ee2e5860dd6c91a45b628)
* I was given bad information. Correcting that now.
Change-Id: I6676585bd040ae6b19062fdab6942389b3d1581e
(cherry picked from commit a1d8c5563806e9d985a9990fe37ca31527a56da1)
* decoder shows EIP if 67 used for rip rel in 64b mode.
looks nicer.
* encoder works with EIP (and emits 67) if used for encoding.
Change-Id: Ie3a63c7562c90ea8e48ac24e89d6ac5d8b20a1b8
* rIP() was effective address size (EASZ) sensitive and that was
wrong.
* some branch instructions have 64b mode only patterns. They now
use XED_REG_RIP.
* some branch instructions have not64 mode only patterns. They now
use XED_REG_EIP.
* some branch patterns use common patterns. They use rIP() but now
rIP() is mode-only sensitive. In 64b mode, RIP gets updated. And
in non64 modes, EIP gets updated. When EOSZ is 16b, the full 32b
EIP is updated, under a mask.
* Still to do: need to rebase the existing tests and add new ones.
More testing required.
Change-Id: Id6124cab3ec58db702c359b7621e3a17a9d39dfa
* Changed:
BEXTR_XOP
BLCFILL
BLSFILL
BLCS
TZMSK
BLCIC
BLSIC
T1MSKC
BLCMSK
BLCI
* Did not change the LPW instr; AMD docs were not as clear for those.
can revisit.
Change-Id: I984a683025d45e7b2b255ea207383826b77bda6f
* (I recently had to dig up the history of why I used "N" for that
field in VEX and then EVEX and XOP encodings. It was because the
extra operand was for "nondestructive" operations, at least
initially.)
Change-Id: I9abee3ec21a5b95eeeec910a65b4a29098c10c4b
(cherry picked from commit f34733e8c3d415d89167cf1a855b633bce12c135)
* covers the derived conditions for mask=0 and mask!=0.
xed3_operand_get_mask_not0()
xed3_operand_get_mask_zero()
* no need to have them in the datafiles dynamic code any more.
* guarded code by XED_SUPPORTS_AVX512.
Change-Id: Ibff9348a1409264dd349cd9423e7efdbe5f19ffc
(cherry picked from commit 713b5dc4fa038787bd46a769b729173de26047e7)
* SNB/IVB/HSW required VEX.L=0. BDW-onwards changed this
to LIG. Matching the "current" behavior.
* I could make a chip-based decode so that SNB/IVB/HSW XED chips
require VEX.L=0, but as those chips get older this issue is less
relevant.
Change-Id: I2f0abc2c05ecb253f092c9d9aa0b6553fc08f011
(cherry picked from commit 6f513163e757d61624b428d29772a1d56497a1bd)
* improved how sources are partitioned. no more messy subtraction.
it had issues with absolute vs relative paths for different kinds
of builds.
* using substring for filename removal rather than exact match
* partitioned nongenerated sources in to dec, enc, encdec, ild and
common subdirectories under "src"
Change-Id: I632543a548c9410518c708f936efcfc011c137df
(cherry picked from commit 6a3ea22e47d7f9fa94e935391882b622bdf34ff9)
* SNB required W0 in 32b mode for VPINSRD. IVB changed that to WIG
so the VPINSRQ encoding executes as VPINSRD. Same for VPEXTRQ/D. I
had changed VPEXTRQ/D a while ago.
Change-Id: I3e607d8d863f1b325415fb4fd66e268ab0283c88
(cherry picked from commit 82c743b0fb18824aec830668040265b101c0646f)
* had to disable a lot of future stuff that was baked
in to the default build.
Change-Id: I9aabbc8302a6a1b20a3538e832f1cca3a15ddcc8
(cherry picked from commit 44d962709958ba0a1688bd8bc9f386eafb8006e5)
* oc2 codes were originally the 2nd code that we'd get
out of the old SDM opcode map. It was for the type.
Things like ps,pd,d,q, etc.
* This commit ads {i,u}{8,16,32,64} and f{16,32,64} as oc2 types
that translate to themselves as the lower level element types
(xtypes).
Change-Id: I0080f676d29f42f68d82392b41fbf4de7c0195ad
(cherry picked from commit 4691aa01f0e5ff678df0391efc70ddbfaf2b4b80)
* adding PREFETCHW to silvermont and broadwell avoids issue with CPUID bit
referring to non-exising isa-set in --no-amd builds. PREFETCHW
opcode was previously a NOP on pentium-pro-and-later so no
chip-check violation.
* A little bit of a stroke of luck here: the ISA_SET PREFETCHW shows
up in the isa-set enum and in the chip hierarchy, but there are no
instructions in the PREFETCHW ISA_SET. The PREFETCHW instruction is
in the PREFETCH_NOP ISA_SET and is checked for validity that way.
The only major downside of this approach is that the cpuid bit for
PREFETCHW is not displayed properly when queried.
Change-Id: Ic20f9dc86d2a43367cc623794b21ce51811f91b0
(cherry picked from commit 2a030ad113265e3b71633c59dc0084d0bf609edd)
VMCALL in root operation can only be executed from CPL=0
but that is a less used aspect of the instruction.
Change-Id: I8046b1fa2fbf49e61ab5b5e3dc541de70bce91f1
(cherry picked from commit 9ee396ed5cc43d57bfcf18dd74d7cfd82d5b1159)
* These 3 instr ignore the 66/F2/F3 prefixes if present.
* Recently, I pushed a commit ( 5b29d2b ) based on erroneous
information I received, adding no_refining_prefixes to these 3
instr.
Change-Id: I7f32cef7670b48740f29a3bcf5f79cd83a0c4772
(cherry picked from commit 242e8ce888fd7332d0f39ba45f3f73b664155ce1)
* improves isa & chip enums when building --no-amd
Change-Id: I2d302595e540775b591f65d2429e35aa50c89f71
(cherry picked from commit 351e20aeeb9918d991ab1bea7f222057588d6a44)
