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c606f64f71
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8053 Commits

Author SHA1 Message Date
Unknown W. Brackets
c606f64f71 jit-ir: Add div/divu instructions. 2016-05-14 19:23:52 -07:00
Unknown W. Brackets
6413b44434 jit-ir: Enable IR for madd(u)/msub(u). 2016-05-14 19:23:51 -07:00
Unknown W. Brackets
a05ae2a0a6 Correct divide by zero HI/LO values a bit. 
Interpreter is now correct, but it's probably not all that important to
get right in jit.
 2016-05-14 19:23:50 -07:00
Unknown W. Brackets
4ac773e8b4 jit-ir: Implement bit reverse instruction. 2016-05-14 18:21:42 -07:00
Henrik Rydgård
8f430e9631 Merge pull request #8736 from unknownbrackets/ir-clear 
Clear emuhacks on IR block destroy and save state
 2016-05-14 18:51:39 +02:00
Unknown W. Brackets
1f28d802a3 FreeBSD buildfix. 
We need Common to have the right _M_SSE define.  Also, let's not define
SSE4 until we need it, since we might need ifs.
 2016-05-14 09:06:56 -07:00
Unknown W. Brackets
e37777648e jit-ir: Restore emuhacks before saving state. 
Let's just ask jit to do this, not its block cache directly.
 2016-05-14 08:59:44 -07:00
Unknown W. Brackets
b74df87db0 jit-ir: Clear emuhacks on block destroy. 2016-05-14 08:40:53 -07:00
Henrik Rydgard
0541fe36df Symbian buildfix, fix for fpu test 2016-05-14 15:26:43 +02:00
Henrik Rydgard
b612806ee4 Remove accidentally added file 2016-05-14 14:32:43 +02:00
Henrik Rydgard
64eda6a4ec IR: Split Syscall into Syscall and ExitToPC, so we can put ApplyRoundingMode in between. 2016-05-14 14:32:22 +02:00
Henrik Rydgard
91bc3c31a5 Warning fixes 2016-05-14 14:01:27 +02:00
Henrik Rydgard
7a7c3b9b9f More VFPU, vmmul thoughts 2016-05-14 14:00:01 +02:00
Unknown W. Brackets
efc8a8e353 Hack to make Symbian build. 2016-05-13 23:56:17 -07:00
Henrik Rydgard
b7091a8f5d Simplifications and fixes 2016-05-13 21:02:23 +02:00
Henrik Rydgard
5923013d65 Simple workaround for timing issue with coreState after syscall. 
Also fixes off by one in ForceCheck.
 2016-05-13 20:21:19 +02:00
Henrik Rydgard
5b2504120d Optimize some common prefixes 2016-05-13 20:15:20 +02:00
Henrik Rydgard
91a6cf5e44 Add a couple more passes (2-op, optimize f<->v fp moves) 2016-05-13 20:14:03 +02:00
Henrik Rydgard
f636b2a315 Minor build and other fixes 2016-05-13 19:31:27 +02:00
Unknown W. Brackets
066b0b7fdf jit-ir: Optimize out beql; break; sequences. 
These are often used following divs, and are harmless.  Things get a bit
easier if we just never compile them.
 2016-05-13 07:59:39 -07:00
Unknown W. Brackets
7b43e0e59d jit-ir: Add nan/inf compares. 
Without this, Gods Eater Burst crashes before going in game.
 2016-05-12 22:53:21 -07:00
Unknown W. Brackets
9e3572dc63 jit-ir: Improve vidt to handle more cases. 2016-05-12 22:40:26 -07:00
Unknown W. Brackets
f52120353b jit-ir: Apply prefixes for vector init ops. 
Without this, Gods Eater Burst is horribly broken.
 2016-05-12 22:29:31 -07:00
Unknown W. Brackets
c11c0465de jir-ir: Correct vftm SIMD regs. 2016-05-12 21:29:58 -07:00
Unknown W. Brackets
1ddb2fbfb9 jit-ir: Fix non-SSE Vec4Scale. 2016-05-12 21:02:56 -07:00
Unknown W. Brackets
57b3dbff7e jit-ir: Avoid flushing on a few Vec4 ops. 2016-05-12 21:01:46 -07:00
Unknown W. Brackets
a8126ca132 jit-ir: Add some missing CONDITIONAL_DISABLEs. 2016-05-12 20:56:47 -07:00
Unknown W. Brackets
29ed8d2201 jit-ir: ExitToReg doesn't write to registers. 2016-05-12 18:34:27 -07:00
Unknown W. Brackets
9f183c97ba jit-ir: Prevent reading ahead for each reg write. 2016-05-12 18:30:55 -07:00
Unknown W. Brackets
d06c6c080c jit-ir: Expand unused regs to regular GPRs. 2016-05-12 18:30:55 -07:00
Unknown W. Brackets
99468c6fc1 jit-ir: Optimize out unused temp regs. 
This way, if constants have made the temp obsolete (common with ins, for
example), it won't even get set anymore.
 2016-05-12 18:30:53 -07:00
Henrik Rydgard
7268abec61 IR: vcmp, vcmov, vhdp 2016-05-12 22:35:31 +02:00
Henrik Rydgard
1851458628 Bugfixes 2016-05-12 20:28:59 +02:00
Henrik Rydgard
c69a8c07dc Forgot this 2016-05-12 20:20:59 +02:00
Henrik Rydgard
850d0abc91 IR: More VFPU. Support normal fp compares. 2016-05-12 20:16:15 +02:00
Henrik Rydgard
182674cddf IR: SIMD another matrix orientation. Fix various issues. 2016-05-12 13:10:26 +02:00
Henrik Rydgard
cb251ea93f Crashfix in savestate (hmmmm...) 2016-05-12 12:18:12 +02:00
Henrik Rydgard
2cbfb192c4 IR: Lots more VFPU support, some with SIMD 2016-05-12 12:17:25 +02:00
Henrik Rydgard
219548b8e2 Prefix prep 2016-05-11 00:16:07 +02:00
Henrik Rydgard
b3dd36982f Prefix prep 2016-05-10 23:14:26 +02:00
Henrik Rydgard
db1d1ff9fd IR: Merge the FPU and VFPU instruction sets, no reason to keep them apart 2016-05-10 22:55:27 +02:00
Henrik Rydgard
45efcda6b1 IR: Some more VFPU 2016-05-10 21:50:08 +02:00
Henrik Rydgard
558bb197c7 More VFPU 2016-05-09 23:47:56 +02:00
Henrik Rydgard
a5d5c5ce2b Do the voffset remapping before the IR. This will let us easily add some virtual VFPU registers for the IR to the end, plus it's slightly faster. 2016-05-09 22:40:59 +02:00
Henrik Rydgard
28087a6088 IRFrontend shouldn't know about IRBlock 2016-05-09 20:18:22 +02:00
Henrik Rydgard
e711a47a75 Complete the separation of the IR compiler frontend from the "Jit" 2016-05-09 20:05:06 +02:00
Henrik Rydgard
e806c369b2 Separate the IR frontend from the IR "Jit" 2016-05-09 19:57:18 +02:00
Henrik Rydgard
6e44e97ffa Refactor prep: Split JitInterface into MIPSFrontendInterface and JitInterface 2016-05-09 19:41:39 +02:00
Henrik Rydgard
f50617d679 Skip const flush on set float constant 2016-05-09 18:47:53 +02:00
Unknown W. Brackets
eb6551d72a jit-ir: Correct downcount handling. 
Oops, was wrong - already accounted for delay slots.  Clear so we don't
double count when emitting a syscall.

Fixes FF4 utility msg flickering.
 2016-05-09 01:13:53 -07:00