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1b3e85d67c
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888 Commits

Author SHA1 Message Date
Craig Topper
1b3e85d67c [X86] Make the instructions that use AdSize16/32/64 co-exist together without using mode predicates. 
This is necessary to allow the disassembler to be able to handle AdSize32 instructions in 64-bit mode when address size prefix is used.

Eventually we should probably also support 'addr32' and 'addr16' in the assembler to override the address size on some of these instructions. But for now we'll just use special operand types that will lookup the current mode size to select the right instruction.

llvm-svn: 225075
 2015-01-02 07:02:25 +00:00
Craig Topper
ec0329dc7b [X86] Update disassembler tests for absolute move instructions to check the encodings. This provides testing for r225036. 64-bit mode is still broken. 
llvm-svn: 225037
 2014-12-31 07:24:23 +00:00
Colin LeMahieu
664727ddb9 [Hexagon] Adding accumulating add/sub, doubleword logic-not variants, doubleword bitfield extract, word parity, accumulating multiplies with saturation. 
llvm-svn: 225024
 2014-12-31 00:08:34 +00:00
Colin LeMahieu
ce5a9848a5 [Hexagon] Adding double-logic on predicate instructions. 
llvm-svn: 225018
 2014-12-30 23:22:39 +00:00
Colin LeMahieu
d9937c62e9 [Hexagon] Adding newvalue compare and jumps. 
llvm-svn: 225015
 2014-12-30 23:04:21 +00:00
Colin LeMahieu
4d12863d57 [Hexagon] Adding postincrement register newvalue stores. 
llvm-svn: 225010
 2014-12-30 22:34:08 +00:00
Colin LeMahieu
e11e421bc5 [Hexagon] Removing old newvalue store variants. Adding postincrement immediate newvalue stores. 
llvm-svn: 225009
 2014-12-30 22:28:31 +00:00
Colin LeMahieu
a76ddd9ae4 [Hexagon] Adding indexed store new-value variants. 
llvm-svn: 225007
 2014-12-30 22:00:26 +00:00
Colin LeMahieu
ef54aa0778 [Hexagon] Adding indexed store of immediates. 
llvm-svn: 225006
 2014-12-30 21:01:38 +00:00
Colin LeMahieu
4a47613bb1 [Hexagon] Adding indexed stores. 
llvm-svn: 225005
 2014-12-30 20:42:23 +00:00
Colin LeMahieu
be9ae58d93 [Hexagon] Adding reg-reg indexed load forms. 
llvm-svn: 224997
 2014-12-30 18:58:47 +00:00
Colin LeMahieu
c9924ffc90 [Hexagon] Adding compare byte/halfword reg-reg/reg-imm forms. Adding compare to general register reg-imm form. 
llvm-svn: 224991
 2014-12-30 17:39:24 +00:00
Colin LeMahieu
300c89d245 [Hexagon] Updating constant extender def, adding alu-not instructions, compare to general register, and inverted compares. 
llvm-svn: 224989
 2014-12-30 15:44:17 +00:00
Craig Topper
fdffa281dd Testcases for r224939. 
llvm-svn: 224976
 2014-12-30 02:35:56 +00:00
Colin LeMahieu
51cfbc91d9 [Hexagon] Adding allocframe, post-increment circular immediate stores, post-increment circular register stores, and bit reversed post-increment stores. 
llvm-svn: 224957
 2014-12-29 21:33:45 +00:00
Colin LeMahieu
d8726fd59b [Hexagon] Adding post-increment register form stores and register-immediate form stores with tests. 
llvm-svn: 224952
 2014-12-29 20:44:51 +00:00
Colin LeMahieu
d92e961fd1 [Hexagon] Replacing the remaining postincrement stores with versions that have encoding bits. 
llvm-svn: 224951
 2014-12-29 20:00:43 +00:00
Colin LeMahieu
bb631541eb [Hexagon] Renaming old multiclass for removal. Adding post-increment store classes and instruction defs. 
llvm-svn: 224949
 2014-12-29 19:42:14 +00:00
Colin LeMahieu
3c20022db5 [Hexagon] Adding auto-incrementing loads with and without byte reversal. 
llvm-svn: 224871
 2014-12-26 21:09:25 +00:00
Colin LeMahieu
9363870e8a [Hexagon] Adding locked loads. 
llvm-svn: 224870
 2014-12-26 20:42:27 +00:00
Colin LeMahieu
286196b24f [Hexagon] Adding deallocframe and circular addressing loads. 
llvm-svn: 224869
 2014-12-26 20:30:58 +00:00
Colin LeMahieu
80ca4bde69 [Hexagon] Adding remaining post-increment instruction variants. Removing unused classes. 
llvm-svn: 224868
 2014-12-26 19:31:46 +00:00
Colin LeMahieu
510942bba6 [Hexagon] Adding post-increment unsigned byte loads. 
llvm-svn: 224867
 2014-12-26 19:12:11 +00:00
Colin LeMahieu
e0aad91d5f [Hexagon] Adding post-increment signed byte loads with tests. 
llvm-svn: 224866
 2014-12-26 18:57:13 +00:00
Craig Topper
98caef7939 [X86] Add the debug registers DR8-DR15 so we can assemble and disassemble references to them. 
llvm-svn: 224862
 2014-12-26 18:20:05 +00:00
Craig Topper
955459673e [X86] Don't fail disassembly if REX.R/REX.B is used on an MMX register. Similar fix to not fail to disassembler CR9-CR15 references. 
llvm-svn: 224861
 2014-12-26 18:19:44 +00:00
Craig Topper
1568430176 Teach disassembler to handle illegal immediates on (v)cmpps/pd/ss/sd instructions. Instead of rejecting we'll just generate the _alt forms that don't try to alter the mnemonic. While I'm here, merge some common code in the Instruction printers for the condition code replacement and fix the mask on SSE to be 3-bits instead of 4. 
llvm-svn: 224846
 2014-12-26 06:36:28 +00:00
Colin LeMahieu
3a9d8a20be [Hexagon] Adding doubleword load. 
llvm-svn: 224787
 2014-12-23 20:44:59 +00:00
Colin LeMahieu
c8d82f0149 [Hexagon] Reapplying 224775 load words. 
llvm-svn: 224786
 2014-12-23 20:02:16 +00:00
Jozef Kolek
a7fba787ce [mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructions 
Differential Revision: http://reviews.llvm.org/D5204

llvm-svn: 224785
 2014-12-23 19:55:34 +00:00
Colin LeMahieu
240787f100 Reverting 224775 until mayLoad flag is addressed. 
llvm-svn: 224783
 2014-12-23 19:22:59 +00:00
Colin LeMahieu
9d1882c36f [Hexagon] Adding word loads. 
llvm-svn: 224775
 2014-12-23 18:06:56 +00:00
Colin LeMahieu
263816de1a [Hexagon] Adding signed halfword loads. 
llvm-svn: 224774
 2014-12-23 17:25:57 +00:00
Jozef Kolek
814723a8ed [mips][microMIPS] Implement LWSP and SWSP instructions 
Differential Revision: http://reviews.llvm.org/D6416

llvm-svn: 224771
 2014-12-23 16:16:33 +00:00
Colin LeMahieu
b1f14d473d [Hexagon] Adding memb instruction. Fixing whitespace in test from 224730. 
llvm-svn: 224735
 2014-12-22 21:40:43 +00:00
Colin LeMahieu
c88fff49c9 [Hexagon] Adding classes and load unsigned byte instruction, updating usages. 
llvm-svn: 224730
 2014-12-22 21:20:03 +00:00
Colin LeMahieu
4c325f2cef [Hexagon] Removing old variants of instructions and updating references. 
llvm-svn: 224612
 2014-12-19 20:29:29 +00:00
Colin LeMahieu
b1509fe128 [Hexagon] Adding bit extraction and table indexing instructions. 
llvm-svn: 224610
 2014-12-19 20:01:08 +00:00
Colin LeMahieu
7e0cce8462 [Hexagon] Adding bit insertion instructions. 
llvm-svn: 224609
 2014-12-19 19:54:38 +00:00
Colin LeMahieu
11b6034e2b [Hexagon] Adding more xtype shift instructions. 
llvm-svn: 224608
 2014-12-19 19:51:35 +00:00
Colin LeMahieu
b6c1e97753 [Hexagon] Adding xtype shift instructions. 
llvm-svn: 224604
 2014-12-19 19:34:50 +00:00
Colin LeMahieu
16013f08b8 [Hexagon] Adding transfers to and from control registers. 
llvm-svn: 224599
 2014-12-19 19:06:32 +00:00
Colin LeMahieu
ab28d2b2e6 [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions. 
llvm-svn: 224556
 2014-12-19 00:06:53 +00:00
Colin LeMahieu
069ff897d0 Reverting 224550, was not ready for commit. 
llvm-svn: 224552
 2014-12-18 23:36:15 +00:00
Colin LeMahieu
260ab2afbd [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions. 
llvm-svn: 224550
 2014-12-18 23:27:51 +00:00
Colin LeMahieu
55e21b6e4f [Hexagon] Updating doubleword shift usages to new versions. 
llvm-svn: 224391
 2014-12-16 23:36:15 +00:00
Colin LeMahieu
5cbdca29ae [Hexagon] Adding tstbit/bitclr/bitset instructions. 
llvm-svn: 224374
 2014-12-16 21:28:58 +00:00
Colin LeMahieu
bb5c698516 [Hexagon] Adding bit count and twiddling instructions. 
llvm-svn: 224367
 2014-12-16 20:57:56 +00:00
Colin LeMahieu
28f6e273c4 [Hexagon] Adding asr/lsr/asl reg/imm, asl with saturation, asr with rounding. Doubleword abs/neg/not. Interleave and deinterleave instructions. 
llvm-svn: 224365
 2014-12-16 20:40:23 +00:00
Colin LeMahieu
4932546e48 [Hexagon] Adding absolute value, and negate with saturation 
llvm-svn: 224346
 2014-12-16 17:44:49 +00:00