Commit Graph

129076 Commits

Author SHA1 Message Date
Mehdi Amini
d4501fffa8 Fix unittests: resize() -> reserve()
From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264029 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 07:35:51 +00:00
Mehdi Amini
ba3fe48d48 Rename DenseMap::resize() into DenseMap::reserve() (NFC)
This is more coherent with usual containers.

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264026 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 07:20:00 +00:00
Junmo Park
f04d589b26 Minor code cleanup. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264024 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 04:37:32 +00:00
Sanjoy Das
2576216f6c Appease the windows buildbots
The guess is that the stdout/stderr ordering may differ between windows
/ unix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264019 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 02:11:57 +00:00
Sanjoy Das
1ceb821951 Add "first class" lowering for deopt operand bundles
Summary:
After this change, deopt operand bundles can be lowered directly by
SelectionDAG into STATEPOINT instructions (which are then lowered to a
call or sequence of nop, with an associated __llvm_stackmaps entry0.
This obviates the need to round-trip deoptimization state through
gc.statepoint via RewriteStatepointsForGC.

Reviewers: reames, atrick, majnemer, JosephTremoulet, pgavlin

Subscribers: sanjoy, mcrosier, majnemer, llvm-commits

Differential Revision: http://reviews.llvm.org/D18257

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264015 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 00:59:13 +00:00
Mike Aizatsky
668a12461d [sancov] do not instrument nodes that are full pre-dominators
Summary:
Without tree pruning clang has 2,667,552 points.
Wiht only dominators pruning: 1,515,586.
With both dominators & predominators pruning: 1,340,534.

Resubmit of r262103.

Differential Revision: http://reviews.llvm.org/D18341

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264003 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 23:08:16 +00:00
Justin Lebar
9dd6a5392f [CUDA] Add documentation explaining how to detect clang vs nvcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264002 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 23:05:15 +00:00
Nicolai Haehnle
3f4c92194f AMDGPU: Fix dangling references introduced by r263982
Fixes Valgrind errors on the test cases that were reported as failing
by buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264000 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 22:54:02 +00:00
Simon Pilgrim
752e5f9178 [InstCombine] Ensure all undef operands are handled before binary instruction constant folding
As noted in PR18355, this patch makes it clear that all cases with undef operands have been handled before further constant folding is attempted.

Differential Revision: http://reviews.llvm.org/D18305

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263994 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 22:15:50 +00:00
Duncan P. N. Exon Smith
814be6ba00 Fix -Wdocumentation warnings from r263853
Thanks to chapuni for catching this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263993 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 22:13:44 +00:00
George Burgess IV
127a8ddf85 [MemorySSA] Consider def-only BBs for live-in calculations.
If we have a BB with only MemoryDefs, live-in calculations will ignore
it. This means we get results like this:

define void @foo(i8* %p) {
  ; 1 = MemoryDef(liveOnEntry)
  store i8 0, i8* %p
  br i1 undef, label %if.then, label %if.end

if.then:
  ; 2 = MemoryDef(1)
  store i8 1, i8* %p
  br label %if.end

if.end:
  ; 3 = MemoryDef(1)
  store i8 2, i8* %p
  ret void
}

...When there should be a MemoryPhi in the `if.end` BB.

This patch fixes that behavior.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263991 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 21:25:39 +00:00
Krzysztof Parzyszek
4a0d91478f Remove leftover options from multiline.ll
I added -march=hexagon to force using Hexagon target when testing
locally, and I forgot to take it out.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263990 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 21:25:01 +00:00
Rafael Espindola
5ba9f15845 Add a testcase that would have found the bug in r263971.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263988 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 21:09:38 +00:00
Rafael Espindola
05601d5da5 Revert "[llvm-objdump] Printing relocations in executable and shared object files. This partially reverts r215844 by removing test objdump-reloc-shared.test which stated GNU objdump doesn't print relocations, it does."
This reverts commit r263971.
It produces the wrong results for .rela.dyn. I will add a test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263987 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 20:59:15 +00:00
Krzysztof Parzyszek
5061f597c1 Unxfail test/DebugInfo/Generic/multiline.ll on Hexagon
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263986 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 20:55:59 +00:00
Nicolai Haehnle
739e4c8f8b AMDGPU: Coding style fixes
I meant to add these before committing r263982 as per the review,
but I forgot to squash.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263983 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 20:39:24 +00:00
Nicolai Haehnle
f0b7f107b9 AMDGPU: Add SIWholeQuadMode pass
Summary:
Whole quad mode is already enabled for pixel shaders that compute
derivatives, but it must be suspended for instructions that cause a
shader to have side effects (i.e. stores and atomics).

This pass addresses the issue by storing the real (initial) live mask
in a register, masking EXEC before instructions that require exact
execution and (re-)enabling WQM where required.

This pass is run before register coalescing so that we can use
machine SSA for analysis.

The changes in this patch expose a problem with the second machine
scheduling pass: target independent instructions like COPY implicitly
use EXEC when they operate on VGPRs, but this fact is not encoded in
the MIR. This can lead to miscompilation because instructions are
moved past changes to EXEC.

This patch fixes the problem by adding use-implicit operands to
target independent instructions. Some general codegen passes are
relaxed to work with such implicit use operands.

Reviewers: arsenm, tstellarAMD, mareko

Subscribers: MatzeB, arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D18162

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263982 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 20:28:33 +00:00
Krzysztof Parzyszek
3a1da81cd1 [Hexagon] Add handling fixups and instruction relaxation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263981 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 20:27:17 +00:00
Krzysztof Parzyszek
1608a747d5 [Hexagon] Properly encode registers in duplex instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263980 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 20:13:33 +00:00
Krzysztof Parzyszek
2be5a89f8e [Hexagon] Fix reserving emergency spill slots for register scavenger
- R10 and R11 are not reserved registers.
- Check for reserved registers when finding unused caller-saved registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263977 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 19:57:08 +00:00
Dan Gohman
c13556c771 [WebAssembly] Implement the eqz instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263976 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 19:54:41 +00:00
Chad Rosier
dc7ed9fc0a [SLP] Remove unnecessary member variables by using container APIs.
This changes the debug output, but still retains its usefulness.
Differential Revision: http://reviews.llvm.org/D18324

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263975 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 19:47:44 +00:00
Colin LeMahieu
bb93856810 [llvm-objdump] Printing relocations in executable and shared object files. This partially reverts r215844 by removing test objdump-reloc-shared.test which stated GNU objdump doesn't print relocations, it does.
In executable and shared object ELF files, relocations in the file contain the final virtual address rather than section offset so this is adjusted to display section offset.

Differential revision: http://reviews.llvm.org/D15965

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263971 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 19:14:50 +00:00
Tom Stellard
1f213b9b37 AMDGPU/SI: Fix threshold calculation for branching when exec is zero
Summary:
When control flow is implemented using the exec mask, the compiler will
insert branch instructions to skip over the masked section when exec is
zero if the section contains more than a certain number of instructions.

The previous code would only count instructions in successor blocks,
and this patch modifies the code to start counting instructions in all
blocks between the start and end of the branch.

Reviewers: nhaehnle, arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D18282

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263969 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 18:56:58 +00:00
Chad Rosier
9c1ab0ea68 [AArch64] Add a helpful assert. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263965 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 18:04:10 +00:00
Matt Arsenault
ea35ca49f2 AMDGPU: Remove SignBitIsZero for mubuf scratch offsets
These instructions do not have the same negative base
address problem that DS instructions do on SI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263964 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 18:02:18 +00:00
Peter Collingbourne
f24c9d47b6 ARM: Better codegen for 64-bit compares.
This introduces a custom lowering for ISD::SETCCE (introduced in r253572)
that allows us to emit a short code sequence for 64-bit compares.

Before:

	push	{r7, lr}
	cmp	r0, r2
	mov.w	r0, #0
	mov.w	r12, #0
	it	hs
	movhs	r0, #1
	cmp	r1, r3
	it	ge
	movge.w	r12, #1
	it	eq
	moveq	r12, r0
	cmp.w	r12, #0
	bne	.LBB1_2
@ BB#1:                                 @ %bb1
	bl	f
	pop	{r7, pc}
.LBB1_2:                                @ %bb2
	bl	g
	pop	{r7, pc}

After:

	push	{r7, lr}
	subs	r0, r0, r2
	sbcs.w	r0, r1, r3
	bge	.LBB1_2
@ BB#1:                                 @ %bb1
	bl	f
	pop	{r7, pc}
.LBB1_2:                                @ %bb2
	bl	g
	pop	{r7, pc}

Saves around 80KB in Chromium's libchrome.so.

Some notes on this patch:

- I don't much like the ARMISD::BRCOND and ARMISD::CMOV combines I
  introduced (nothing else needs them). However, they are necessary in
  order to avoid poor codegen, and they seem similar to existing combines
  in other backends (e.g. X86 combines (brcond (cmp (setcc Compare))) to
  (brcond Compare)).

- No support for Thumb-1. This is in principle possible, but we'd need
  to implement ARMISD::SUBE for Thumb-1.

Differential Revision: http://reviews.llvm.org/D15256

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263962 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 18:00:02 +00:00
Renato Golin
faf3d27a21 [ARM] Add Cortex-A32 support
Adding Cortex-A32 as an available target in the ARM backend.

Patch by Sam Parker.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263956 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 17:29:01 +00:00
Hemant Kulkarni
962167f0e2 [llvm-readobj] Impl GNU style symbols printing
Implements "readelf -sW and readelf -DsW"

Differential Revision: http://reviews.llvm.org/D18224

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263952 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 17:18:23 +00:00
Lang Hames
43f3f60fb4 [Orc] Switch RPC Procedure to take a function type, rather than an arg list.
No functional change, just a little more readable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263951 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 16:56:25 +00:00
Matt Arsenault
7c9226fea8 APFloat: Add frexp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263950 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 16:49:16 +00:00
Matt Arsenault
c8d042bec9 AMDGPU: Add frexp_mant intrinsic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263948 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 16:11:05 +00:00
Matt Arsenault
23f7a82592 Implement constant folding for bitreverse
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263945 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 15:00:35 +00:00
Chad Rosier
a4bb38c2a8 [AArch64] Fix a -Wdocumentation warning. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263942 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 13:43:58 +00:00
Silviu Baranga
872392e1a9 [IndVars] Fix PR26974: make sure replaceCongruentIVs doesn't break LCSSA
Summary:
replaceCongruentIVs can break LCSSA when trying to replace IV increments
since it tries to replace all uses of a phi node with another phi node
while both of the phi nodes are not necessarily in the processed loop.
This will cause an assert in IndVars.

To fix this, we add a check to make sure that the replacement maintains
LCSSA.

Reviewers: sanjoy

Subscribers: mzolotukhin, llvm-commits

Differential Revision: http://reviews.llvm.org/D18266

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263941 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 12:44:29 +00:00
Silviu Baranga
bec2ec108f [DAGCombine] Catch the case where extract_vector_elt can cause an any_ext while processing AND SDNodes
Summary:
extract_vector_elt can cause an implicit any_ext if the types don't
match. When processing the following pattern:

  (and (extract_vector_elt (load ([non_ext|any_ext|zero_ext] V))), c)

DAGCombine was ignoring the possible extend, and sometimes removing
the AND even though it was required to maintain some of the bits
in the result to 0, resulting in a miscompile.

This change fixes the issue by limiting the transformation only to
cases where the extract_vector_elt doesn't perform the implicit
extend.

Reviewers: t.p.northover, jmolloy

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D18247

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263935 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 11:43:46 +00:00
Elena Demikhovsky
ff9be37421 Fixed -mcpu flag
"core-avx" does not exist; I changed to "nehalem"


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263932 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 11:06:20 +00:00
Simon Pilgrim
9cba37e8d4 [X86][SSE] Add vector integer division by constant tests
Expanded tests and split into sdiv/srem and udiv/urem cases for 128 and 256 bit vectors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263917 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-20 21:46:58 +00:00
Jingyue Wu
eed77df1b6 [NVPTX] Adds a new address space inference pass.
Summary:
The old address space inference pass (NVPTXFavorNonGenericAddrSpaces) is unable
to convert the address space of a pointer induction variable. This patch adds a
new pass called NVPTXInferAddressSpaces that overcomes that limitation using a
fixed-point data-flow analysis (see the file header comments for details).

The new pass is experimental and not enabled by default. Users can turn
it on by setting the -nvptx-use-infer-addrspace flag of llc.

Reviewers: jholewinski, tra, jlebar

Subscribers: jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D17965

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263916 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-20 20:59:20 +00:00
Davide Italiano
443693f33a [gold] Emit a diagnostic in case we fail to remove a file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263914 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-20 20:12:33 +00:00
Simon Pilgrim
cdda81445a [X86][SSE] Tidyup setTargetShuffleZeroElements to match computeZeroableShuffleElements
Based on feedback for D14261

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263911 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-20 17:43:07 +00:00
Simon Pilgrim
21f68df4a2 [X86][SSE] Detect zeroable shuffle elements from different value types
Improve computeZeroableShuffleElements to be able to peek through bitcasts to extract zero/undef values from BUILD_VECTOR nodes of different element sizes to the shuffle mask.

Differential Revision: http://reviews.llvm.org/D14261

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263906 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-20 15:45:42 +00:00
Igor Breger
121e8b9361 AVX512BW: Enable v32i1/v64i1 BUILD_VECTOR
Differential Revision: http://reviews.llvm.org/D18211

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263898 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-20 13:09:43 +00:00
George Rimar
81a0c97314 [ELF] Update x86_64 relocations to 0.99.8 ABI
Added: R_X86_64_GOTPCRELX, R_X86_64_REX_GOTPCRELX


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263894 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-20 09:45:08 +00:00
Craig Topper
2e8d041188 Suppress a -Wunused-variable warning in release builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263892 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-20 01:17:54 +00:00
Michael Kuperstein
183d4c239a Use a range-based for loop. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263889 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-20 00:16:13 +00:00
Mehdi Amini
e6cda0e9bc Expose IRBuilder::CreateAtomicCmpXchg as LLVMBuildAtomicCmpXchg in the C API.
Summary: Also expose getters and setters in the C API, so that the change can be tested.

Reviewers: nhaehnle, axw, joker.eph

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D18260

From: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263886 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-19 21:28:28 +00:00
Mehdi Amini
14e4632794 Const-correctness in libLTO
Looks like I was sloppy when bridging to C.
Thanks D. Blaikie for noticing!

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263885 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-19 21:28:18 +00:00
Saleem Abdulrasool
b6275da485 CodeGen: use range based for loop
Convert a loop to use a range based style loop.  NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263884 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-19 16:35:32 +00:00
David Majnemer
649040b838 [SimplifyLibCalls] Only consider sinpi/cospi functions within the same function
The sinpi/cospi can be replaced with sincospi to remove unnecessary
computations.  However, we need to make sure that the calls are within
the same function!

This fixes PR26993.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263875 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-19 04:53:02 +00:00