Commit Graph

51506 Commits

Author SHA1 Message Date
Nick Lewycky
7912ef97ff Less template, more virtual! Refactoring suggested by Chris in code review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145014 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-20 19:37:06 +00:00
Nick Lewycky
173862e546 Refactor code to use new attribute getters on CallSite for NoCapture and ByVal.
Suggested in code review by Eli.

That code in InstCombine looks kinda suspicious.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145013 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-20 19:09:04 +00:00
Chandler Carruth
b0dadb9dd5 The logic for breaking the CFG in the presence of hot successors didn't
properly account for the *global* probability of the edge being taken.
This manifested as a very large number of unconditional branches to
blocks being merged against the CFG even though they weren't
particularly hot within the CFG.

The fix is to check whether the edge being merged is both locally hot
relative to other successors for the source block, and globally hot
compared to other (unmerged) predecessors of the destination block.

This introduces a new crasher on GCC single-source, but it's currently
behind a flag, and Ben has offered to work on the reduction. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145010 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-20 11:22:06 +00:00
Benjamin Kramer
13c3c75176 SCEV: Actually set overflow flags on add expressions.
setFlags doesn't modify its arguments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145007 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-20 10:24:36 +00:00
Craig Topper
0d86d462f8 Add code for lowering v32i8 shifts by a splat to AVX2 immediate shift instructions. Remove 256-bit splat handling from LowerShift as it was already handled by PerformShiftCombine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145005 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-20 00:12:05 +00:00
Craig Topper
745a86bac9 Use 256-bit vcmpeqd for creating an all ones vector when AVX2 is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-19 22:34:59 +00:00
Craig Topper
ba798c5e51 Remove some of the special classes that worked around an old tablegen limitation of not being able to remove redundant bitconverts from patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-19 21:01:54 +00:00
Craig Topper
98fc72940b Custom lower AVX2 variable shift intrinsics to shl/srl/sra nodes and remove the intrinsic patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144999 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-19 17:46:46 +00:00
Chandler Carruth
03300ecaee Move the handling of unanalyzable branches out of the loop-driven chain
formation phase and into the initial walk of the basic blocks. We
essentially pre-merge all blocks where unanalyzable fallthrough exists,
as we won't be able to update the terminators effectively after any
reorderings. This is quite a bit more principled as there may be CFGs
where the second half of the unanalyzable pair has some analyzable
predecessor that gets placed first. Then it may get placed next,
implicitly breaking the unanalyzable branch even though we never even
looked at the part that isn't analyzable. I've included a test case that
triggers this (thanks Benjamin yet again!), and I'm hoping to synthesize
some more general ones as I dig into related issues.

Also, to make this new scheme work we have to be able to handle branches
into the middle of a chain, so add this check. We always fallback on the
incoming ordering.

Finally, this starts to really underscore a known limitation of the
current implementation -- we don't consider broken predecessors when
merging successors. This can caused major missed opportunities, and is
something I'm planning on looking at next (modulo more bug reports).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144994 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-19 10:26:02 +00:00
Craig Topper
54f952afac Synthesize SSSE3/AVX 128-bit horizontal integer add/sub instructions from add/sub of appropriate shuffle vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144989 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-19 09:02:40 +00:00
Craig Topper
3113384a34 Collapse X86 PSIGNB/PSIGNW/PSIGND node types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144988 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-19 07:33:10 +00:00
Craig Topper
1666cb6d63 Extend VPBLENDVB and VPSIGN lowering to work for AVX2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144987 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-19 07:07:26 +00:00
Craig Topper
60d9a9206e Remove unused parameters from the AVX maskmov classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144985 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-19 04:49:22 +00:00
Andrew Trick
5865a8dfde Fix a corner case in updating LoopInfo after fully unrolling an outer loop.
The loop tree's inclusive block lists are painful and expensive to
update. (I have no idea why they're inclusive). The design was
supposed to handle this case but the implementation missed it and my
unit tests weren't thorough enough.

Fixes PR11335: loop unroll update.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144970 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-18 03:42:41 +00:00
Nadav Rotem
cbbe33fde4 Add AVX2 vpbroadcast support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144967 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-18 02:49:55 +00:00
Kostya Serebryany
5a3a9c9371 [asan] workaround for reg alloc bug 11395: don't instrument functions with large chunks of inline assembler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144962 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-18 01:41:06 +00:00
Chad Rosier
424fe0e422 Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work/dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144959 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-18 01:17:34 +00:00
Devang Patel
ce35d8b5a1 DISubrange supports unsigned lower/upper array bounds, so let's not fake it in the end while emitting DWARF. If a FE needs to encode signed lower/upper array bounds then we need to extend DISubrange or ad DISignedSubrange.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144937 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 23:43:15 +00:00
Kostya Serebryany
2e7fb2f736 quick fix: remove GlobalVariable::GlobalVariable mistakenly commited at r144933. For some reason this compiles on linux
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144936 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 23:37:53 +00:00
Andrew Trick
4f3052403c Fix an overly general check in SimplifyIndvar to handle useless phi cycles.
The right way to check for a binary operation is
cast<BinaryOperator>. The original check: cast<Instruction> &&
numOperands() == 2 would match phi "instructions", leading to an
infinite loop in extreme corner case: a useless phi with operands
[self, constant] that prior optimization passes failed to remove,
being used in the loop by another useless phi, in turn being used by an
lshr or udiv.

Fixes PR11350: runaway iteration assertion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144935 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 23:36:35 +00:00
Kostya Serebryany
7cf2a04361 fall back to explicit list of allowed linkages when instrumenting globals in asan; add a test check that asan does not touch linkonce_odr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144933 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 23:14:59 +00:00
Chad Rosier
944d82ba06 Add TODO comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144920 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 21:46:13 +00:00
Craig Topper
d90a191685 Fix SSE/AVX integer comparison patterns to understand that all integer vector loads are promoted to i64 vector loads so patterns need a bitconvert. Also slightly simplify the AVX2 variable shift patterns by using the predefined bitconvert pattern fragments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144896 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 07:49:38 +00:00
Chad Rosier
2fb82ce75d Dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144888 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 07:24:49 +00:00
Chad Rosier
478b06c980 When fast iseling a GEP, accumulate the offset rather than emitting a series of
ADDs.  MaxOffs is used as a threshold to limit the size of the offset. Tradeoffs
being: (1) If we can't materialize the large constant then we'll cause fast-isel
to bail. (2) Too large of an offset can't be directly encoded in the ADD
resulting in a MOV+ADD.  Generally not a bad thing because otherwise we would
have had ADD+ADD, but on Thumb this turns into a MOVS+MOVT+ADD. Working on a fix
for that. (3) Conversely, too low of a threshold we'll miss opportunities to 
coalesce ADDs.
rdar://10412592



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144886 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 07:15:58 +00:00
Craig Topper
ec43d1f553 Remove seemingly unnecessary duplicate VROUND definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144885 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 07:04:00 +00:00
Eli Friedman
9d434dbff3 Add support for custom names for library functions in TargetLibraryInfo. Add a custom name for fwrite and fputs on x86-32 OSX. Make SimplifyLibCalls honor the custom
names for fwrite and fputs.

Fixes <rdar://problem/9815881>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144876 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 01:27:36 +00:00
Chad Rosier
3bdb3c9b51 Don't unconditionally set the kill flag.
rdar://10456186


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144872 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 01:16:53 +00:00
Eli Friedman
d224c7879a Turn on vzeroupper insertion on call boundaries for AVX; it works as far as I know, and I'd like to see wider testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144867 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 00:21:52 +00:00
Eli Friedman
4db4addcd4 Make sure to replace the chain properly when DAGCombining a LOAD+EXTRACT_VECTOR_ELT into a single LOAD. Fixes PR10747/PR11393.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144863 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 23:50:22 +00:00
Michael J. Spencer
11ba26db13 Object/COFF: Support common symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144861 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 23:36:12 +00:00
Jim Grosbach
2abba8496c Generalize the fixup info for ARM mode.
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144852 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:48:37 +00:00
Akira Hatanaka
620db8947a Lower 64-bit constant pool node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144849 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:44:38 +00:00
Akira Hatanaka
9b944a8da2 Lower 64-bit block address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144847 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:42:10 +00:00
Jim Grosbach
b84acd2468 Fix encoding of NOP used for padding in ARM mode .align.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144842 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:40:25 +00:00
Akira Hatanaka
74c76347d3 Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpool
nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144841 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:39:56 +00:00
Akira Hatanaka
4fd40b3604 64-bit jump register instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144840 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:36:01 +00:00
Evan Cheng
2b89498979 Another missing X86ISD::MOVLPD pattern. rdar://10450317
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144839 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:24:44 +00:00
Jim Grosbach
40a86ee20f ARM assembly parsing for shifted register operands for MOV instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144837 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 21:50:05 +00:00
Jim Grosbach
efed3d1f58 Clean up debug printing of ARM shifted operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144836 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 21:46:50 +00:00
Chad Rosier
053e69ad57 Add fast-isel stats to determine who's doing all the work, the
target-independent selector or the target-specific selector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144833 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 21:05:28 +00:00
Chad Rosier
f91488cc10 Fix the stats collection for fast-isel. The failed count was only accounting
for a single miss and not all predecessor instructions that get selected by
the selection DAG instruction selector.  This is still not exact (e.g., over
states misses when folded/dead instructions are present), but it is a step in
the right direction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144832 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 21:02:08 +00:00
Jim Grosbach
b598b04409 ARM assmebly two operand forms for LSR, ASR, LSL, ROR register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144814 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 19:12:24 +00:00
Jim Grosbach
48b368bcd5 ARM assembly parsing for RRX mnemonic.
rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144812 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 19:05:59 +00:00
Pete Cooper
cd75e44173 Added missing comment about new custom lowering of DEC64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 19:03:23 +00:00
Evan Cheng
c3aa7c5c5a Disable expensive two-address optimizations at -O0. rdar://10453055
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144806 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 18:44:48 +00:00
Chad Rosier
508a1f4db1 Check to make sure we can select the instruction before trying to put the
operands into a register.  Otherwise, we may materialize dead code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144805 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 18:39:44 +00:00
Evan Cheng
14117c4477 Disable the assertion again. Looks like fastisel is still generating bad kill markers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144804 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 18:32:14 +00:00
Jim Grosbach
23f220705a ARM mode aliases for bitwise instructions w/ register operands.
rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144803 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 18:31:45 +00:00
Bob Wilson
d0405aaabc Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144798 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 17:09:59 +00:00
NAKAMURA Takumi
5c283e98c9 lib/Target/ARM/CMakeLists.txt: Disable optimization in ARMISelLowering.cpp also on MSC15(aka VS9). Seems miscompiled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144794 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 09:18:28 +00:00
Evan Cheng
b95fc31aa2 Sink codegen optimization level into MCCodeGenInfo along side relocation model
and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144788 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 08:38:26 +00:00
Bob Wilson
f1b41dd38d Record landing pads with a SmallSetVector to avoid multiple entries.
There may be many invokes that share one landing pad, and the previous code
would record the landing pad once for each invoke.  Besides the wasted
effort, a pair of volatile loads gets inserted every time the landing pad is
processed.  The rest of the code can get optimized away when a landing pad
is processed repeatedly, but the volatile loads remain, resulting in code like:

LBB35_18:
Ltmp483:
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r4, [r7, #-72]
        ldr     r2, [r7, #-68]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144787 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 07:57:21 +00:00
Craig Topper
12755b07ab Fix the execution domain on a bunch of SSE/AVX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144784 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 07:30:46 +00:00
Bob Wilson
20c918dfed Update the SP in the SjLj jmpbuf whenever it changes. <rdar://problem/10444602>
This same basic code was in the older version of the SjLj exception handling,
but it was removed in the recent revisions to that code.  It needs to be there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144782 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 07:12:00 +00:00
Bob Wilson
eaab6ef6eb Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602>
The EmitBasePointerRecalculation function has 2 problems, one minor and one
fatal.  The minor problem is that it inserts the code at the setjmp
instead of in the dispatch block.  The fatal problem is that at the point
where this code runs, we don't know whether there will be a base pointer,
so the entire function is a no-op.  The base pointer recalculation needs to
be handled as it was before, by inserting a pseudo instruction that gets
expanded late.

Most of the support for the old approach is still here, but it no longer
has any connection to the eh_sjlj_dispatchsetup intrinsic.  Clean up the
parts related to the intrinsic and just generate the pseudo instruction
directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144781 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 07:11:57 +00:00
Craig Topper
2713d045e3 Remove code to enable execution dependency fix pass on VR256. VR128 is sufficient after r144636.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144777 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 05:02:04 +00:00
Evan Cheng
0a405ae78a Revert r144568 now that r144730 has fixed the fast-isel kill marker bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144776 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 04:55:01 +00:00
Nick Lewycky
ae10dd2859 Merge isObjectPointerWithTrustworthySize with getPointerSize. Use it when
looking at the size of the pointee. Fixes PR11390!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144773 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 03:49:48 +00:00
Evan Cheng
9bad88a9de If the 2addr instruction has other kills, don't move it below any other uses since we don't want to extend other live ranges.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144772 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 03:47:42 +00:00
Evan Cheng
2bee6a8bb7 RescheduleKillAboveMI() must backtrack to before the rescheduled DBG_VALUE instructions. rdar://10451185
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144771 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 03:33:08 +00:00
Evan Cheng
ae7db7af44 Process all uses first before defs to accurately capture register liveness. rdar://10449480
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144770 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 03:05:12 +00:00
Eli Friedman
d577df8e5a CONCAT_VECTORS can have more than two operands. PR11389.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144768 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 02:52:39 +00:00
Eli Friedman
b91b6001a6 Add a couple asserts so it will be easier to debug if we accidentally pass indexed loads/stores to the legalizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144767 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 02:43:15 +00:00
Kostya Serebryany
800e03f598 AddressSanitizer, first commit (compiler module only)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144758 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 01:35:23 +00:00
Kostya Serebryany
a2a2d1fddd test commit to verify that commit access works (added blank line)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144748 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 01:14:38 +00:00
Owen Anderson
99aa14ff64 Rename MVT::untyped to MVT::Untyped to match similar nomenclature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144747 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 01:02:57 +00:00
Andrew Trick
79f0bfcc20 Fix SCEV overly optimistic back edge taken count for multi-exit loops.
Fixes PR11375: Different results for 'clang++ huh.cpp'...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144746 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 00:52:40 +00:00
Chad Rosier
f56c60b571 Add FIXME comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144743 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 00:32:20 +00:00
Jakob Stoklund Olesen
3805d85e38 Enable -widen-vmovs by default.
This will widen 32-bit register vmov instructions to 64-bit when
possible.  The 64-bit vmovd instructions can then be translated to NEON
vorr instructions by the execution dependency fix pass.

The copies are only widened if they are marked as clobbering the whole
D-register.

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2011-11-15 23:53:18 +00:00
Eric Christopher
8368f74c43 Stabilize the output of the dwarf accelerator tables. Fixes a comparison
failure during bootstrap with it turned on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144731 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 23:37:17 +00:00
Chad Rosier
22b34cce4d GEPs with all zero indices are trivially coalesced by fast-isel. For example,
%arrayidx135 = getelementptr inbounds [4 x [4 x [4 x [4 x i32]]]]* %M0, i32 0, i64 0
%arrayidx136 = getelementptr inbounds [4 x [4 x [4 x i32]]]* %arrayidx135, i32 0, i64 %idxprom134

Prior to this commit, the GEP instruction that defines %arrayidx136 thought that 
%arrayidx135 was a trivial kill.  The GEP that defines %arrayidx135 doesn't 
generate any code and thus %M0 gets folded into the second GEP.  Thus, we need
to look through GEPs with all zero indices.
rdar://10443319

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2011-11-15 23:34:05 +00:00
Jim Grosbach
e43862b6a6 ARM assembly parsing for register range syntax for VLD/VST register lists.
For example,
vld1.f64 {d2-d5}, [r2,:128]!

Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!

It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.

rdar://10451128


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2011-11-15 23:19:15 +00:00
Jim Grosbach
5b2fb2083c ARM assembly parsing for data type suffices on NEON VMOV aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144722 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 22:54:42 +00:00
Nadav Rotem
de631128d6 Fix MSVC warnings by adding a cast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144721 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 22:54:21 +00:00
Nadav Rotem
f8c10e5cb1 AVX: Add support for vbroadcast from BUILD_VECTOR and refactor some of the vbroadcast code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144720 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 22:50:37 +00:00
Jim Grosbach
9f302c4fb3 ARM assembly parsing two operand forms for shift instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144713 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 22:27:54 +00:00
Jim Grosbach
88d012a9c3 ARM VFP assembly parsing for VADD and VSUB two-operand forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144710 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 22:15:10 +00:00
Jim Grosbach
6cb4b08182 ARM accept an immediate offset in memory operands w/o the '#'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144709 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 22:14:41 +00:00
Pete Cooper
2d49689793 Added custom lowering for load->dec->store sequence in x86 when the EFLAGS registers is used
by later instructions.

Only done for DEC64m right now.

Fixes <rdar://problem/6172640>


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2011-11-15 21:57:53 +00:00
Jim Grosbach
5c984e451d ARM enclosing curly braces optional on one-register VLD/VST instruction lists.
'vld1.f32 d4, [r7]' should be parsed as equivalent to 'vld1.f32 {d4}, [r7]'

rdar://10450488.

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2011-11-15 21:45:55 +00:00
Jim Grosbach
eaf2056709 ARM size suffix on VFP single-precision 'vmov' is optional.
rdar://10435114

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2011-11-15 21:18:35 +00:00
Devang Patel
d2df64f569 Insert modified DBG_VALUE into LiveDbgValueMap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144696 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 21:03:58 +00:00
Jim Grosbach
25e0a87e91 Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144695 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 21:01:30 +00:00
Jim Grosbach
19885de61d ARM alternate size suffices for VTRN instructions.
rdar://10435076

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2011-11-15 20:49:46 +00:00
Owen Anderson
22925d93e9 Fix a misplaced paren bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144692 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 20:30:41 +00:00
Jim Grosbach
a68e90c36e ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.
Yet more of rdar://10435076.

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2011-11-15 20:29:42 +00:00
Jim Grosbach
bfb0a1717b ARM assembly parsing for two-operand form of 'mul' instruction.
rdar://10449856.

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2011-11-15 20:14:51 +00:00
Jim Grosbach
d2586daf06 ARM assembly parsing for two-operand form of 'mul' instruction.
Ongoing rdar://10435114.

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2011-11-15 20:02:06 +00:00
Jim Grosbach
7f1ec9570d Thumb2 two-operand 'mul' instruction wide encoding parsing.
rdar://10449724

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2011-11-15 19:55:16 +00:00
Owen Anderson
b589be9334 Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144683 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 19:55:00 +00:00
Jim Grosbach
1de0bd1945 Thumb2 assembly parsing for mul.w in IT block fix.
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.

rdar://10449281

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2011-11-15 19:29:45 +00:00
Benjamin Kramer
b5ccb25bc2 StringRefize and simplify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 19:12:09 +00:00
Rafael Espindola
6c5b2dcd83 We currently use a callback to handle an IL pass deleting a BB that still
has a reference to it. Unfortunately, that doesn't work for codegen passes
since we don't get notified of MBB's being deleted (the original BB stays).

Use that fact to our advantage and after printing a function, check if
any of the IL BBs corresponds to a symbol that was not printed. This fixes
pr11202.

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2011-11-15 19:08:46 +00:00
Akira Hatanaka
1b71950812 Fix functions in MipsFrameLowering.cpp and MipsRegisterInfo.cpp. Use 64-bit
registers and instructions when ABI is N64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144666 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 18:53:55 +00:00
Akira Hatanaka
ac20aad81c Set nomacro before emitting the sequence of instructions that set global pointer
register.


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2011-11-15 18:44:44 +00:00
Akira Hatanaka
160408546c Simplify function PassByValArg64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144664 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 18:42:25 +00:00
Akira Hatanaka
00e1fa499d Remove function printMipsSymbolRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144663 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 18:38:35 +00:00
Benjamin Kramer
2bbb7e3ca6 Remove Value::getNameStr. It has been deprecated for a while and provides no additional value over getName().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144657 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 18:30:12 +00:00
Benjamin Kramer
2774dc085d Missed some users of Value::getNameStr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144656 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 18:30:06 +00:00
Akira Hatanaka
870b3b2dd4 Delete files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144655 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 18:22:48 +00:00
Akira Hatanaka
73c38f0aa2 Remove MipsMCSymbolRefExpr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144654 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 18:20:08 +00:00
Jim Grosbach
c5a6a687fd ARM parsing datatype suffix variants for register-writeback VLD1/VST1 instructions.
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144650 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 17:49:59 +00:00
Jim Grosbach
946227d64a Tidy up. 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144649 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 16:46:22 +00:00
Benjamin Kramer
a7b0cb7594 Remove all remaining uses of Value::getNameStr().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144648 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 16:27:03 +00:00
Benjamin Kramer
25ad1cc32a Twinify GraphWriter a little bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144647 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 16:26:38 +00:00
Jakob Stoklund Olesen
d1bfc30198 Check all overlaps when looking for used registers.
A function using any RC alias is enough to enable the ExeDepsFix pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144636 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 08:20:43 +00:00
Jay Foad
f4a5084d06 Make use of MachinePointerInfo::getFixedStack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144635 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 07:51:13 +00:00
Jay Foad
8c2e35269c Remove some unnecessary includes of PseudoSourceValue.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144634 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 07:50:46 +00:00
Jay Foad
bf8356b37c Fix typo in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144633 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 07:50:05 +00:00
Jay Foad
978e0dfe46 Make use of MachinePointerInfo::getFixedStack. This removes all mention
of PseudoSourceValue from lib/Target/.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144632 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 07:34:52 +00:00
Jay Foad
d9190c0f14 Remove some unnecessary includes of PseudoSourceValue.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144631 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 07:24:32 +00:00
Craig Topper
44ec9fddc2 Fix PR11370 for real. Prevents converting 256-bit FP instruction to AVX2 256-bit integer instructions when AVX2 isn't enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144629 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 06:39:01 +00:00
Evan Cheng
f178418729 Set SeenStore to true to prevent loads from being moved; also eliminates a non-deterministic behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144628 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 06:26:51 +00:00
Chandler Carruth
3273c8937b Rather than trying to use the loop block sequence *or* the function
block sequence when recovering from unanalyzable control flow
constructs, *always* use the function sequence. I'm not sure why I ever
went down the path of trying to use the loop sequence, it is
fundamentally not the correct sequence to use. We're trying to preserve
the incoming layout in the cases of unreasonable control flow, and that
is only encoded at the function level. We already have a filter to
select *exactly* the sub-set of blocks within the function that we're
trying to form into a chain.

The resulting code layout is also significantly better because of this.
In several places we were ending up with completely unreasonable control
flow constructs due to the ordering chosen by the loop structure for its
internal storage. This change removes a completely wasteful vector of
basic blocks, saving memory allocation in the common case even though it
costs us CPU in the fairly rare case of unnatural loops. Finally, it
fixes the latest crasher reduced out of GCC's single source. Thanks
again to Benjamin Kramer for the reduction, my bugpoint skills failed at
it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144627 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 06:26:43 +00:00
Craig Topper
4c077a1f04 Properly qualify AVX2 specific parts of execution dependency table. Also enable converting between 256-bit PS/PD operations when AVX1 is enabled. Fixes PR11370.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144622 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 05:55:35 +00:00
Evan Cheng
eaa192af18 Add vmov.f32 to materialize f32 immediate splats which cannot be handled by
integer variants. rdar://10437054


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2011-11-15 02:12:34 +00:00
Jim Grosbach
bfc9429c2b ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions.
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144606 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 01:46:57 +00:00
Nick Lewycky
e7c1aef2b8 Move WEAK marking to the declaration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144603 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 01:23:22 +00:00
Jakob Stoklund Olesen
c2ecf3efbf Break false dependencies before partial register updates.
Two new TargetInstrInfo hooks lets the target tell ExecutionDepsFix
about instructions with partial register updates causing false unwanted
dependencies.

The ExecutionDepsFix pass will break the false dependencies if the
updated register was written in the previoius N instructions.

The small loop added to sse-domains.ll runs twice as fast with
dependency-breaking instructions inserted.

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2011-11-15 01:15:30 +00:00
Jakob Stoklund Olesen
2947f730a9 Track register ages more accurately.
Keep track of the last instruction to define each register individually
instead of per DomainValue.  This lets us track more accurately when a
register was last written.

Also track register ages across basic blocks.  When entering a new
basic block, use the least stale predecessor def as a worst case
estimate for register age.

The register age is used to arbitrate between conflicting domains. The
most recently defined register wins.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144601 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 01:15:25 +00:00
Nick Lewycky
ec381a4183 Fix linking for some users who already have tsan enabled code and are trying to
link it against llvm code, by making our definitions weak. "Some users."


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144596 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 00:14:04 +00:00
Jim Grosbach
dd47e0b5d4 ARM parsing datatype suffix variants for non-writeback VST1 instructions.
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144593 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:43:46 +00:00
Jim Grosbach
e052b9afa1 ARM parsing datatype suffix variants for non-writeback VLD1 instructions.
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144592 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:32:59 +00:00
Jim Grosbach
04db7f7a7d Add explanatory comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144589 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:21:09 +00:00
Jim Grosbach
0530d0d5d9 Split out the plain '.{8|16|32|64}' suffix handling.
Make it easier to deal with aliases for instructions that do require a suffix
but accept more specific variants of the same size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144588 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:20:14 +00:00
Jim Grosbach
ef448767a3 ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions.
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144587 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:11:19 +00:00
Chad Rosier
2c42b8c912 Supporting inline memmove isn't going to be worthwhile. The only way to avoid
violating a dependency is to emit all loads prior to stores.  This would likely
cause a great deal of spillage offsetting any potential gains.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144585 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:04:09 +00:00
Jim Grosbach
ffc658b056 ARM VLDR/VSTR instructions don't need a size suffix.
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:03:21 +00:00
Nick Lewycky
88990248d3 Refactor capture tracking (which already had a couple flags for whether returns
and stores capture) to permit the caller to see each capture point and decide
whether to continue looking.

Use this inside memdep to do an analysis that basicaa won't do. This lets us
solve another devirtualization case, fixing PR8908!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144580 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 22:49:42 +00:00
Chad Rosier
909cb4f2f2 Add support for inlining small memcpys.
rdar://10412592


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144578 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 22:46:17 +00:00
Chad Rosier
e489af8dce Fix a performance regression from r144565. Positive offsets were being lowered
into registers, rather then encoded directly in the load/store.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144576 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 22:34:48 +00:00
Jim Grosbach
02e3d9268f ARM assembly parsing type suffix options for VLDR/VSTR.
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144575 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 22:28:39 +00:00
Evan Cheng
8aee7d8f9e Avoid dereferencing off the beginning of lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144569 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 21:11:15 +00:00
Evan Cheng
41e00172c5 At -O0, multiple uses of a virtual registers in the same BB are being marked
"kill". This looks like a bug upstream. Since that's going to take some time
to understand, loosen the assertion and disable the optimization when
multiple kills are seen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144568 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 21:02:09 +00:00
Nick Lewycky
4d0a9ff365 Add support for tsan annotations (thread sanitizer, a valgrind-based tool).
These annotations are disabled entirely when either ENABLE_THREADS is off, or
building a release build. When enabled, they add calls to functions with no
statements to ManagedStatic's getters.

Use these annotations to inform tsan that the race used inside ManagedStatic
initialization is actually benign. Thanks to Kostya Serebryany for helping
write this patch!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144567 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 20:50:16 +00:00
Evan Cheng
76c8f08567 Add a missing pattern for X86ISD::MOVLPD. rdar://10436044
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144566 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 20:35:52 +00:00
Chad Rosier
57b2997966 Add support for Thumb load/stores with negative offsets.
rdar://10412592



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144565 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 20:22:27 +00:00
Benjamin Kramer
6296ee3ee2 Unbreak Release builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144560 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 19:51:48 +00:00
Evan Cheng
2a4410df44 Teach two-address pass to re-schedule two-address instructions (or the kill
instructions of the two-address operands) in order to avoid inserting copies.
This fixes the few regressions introduced when the two-address hack was
disabled (without regressing the improvements).
rdar://10422688


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144559 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 19:48:55 +00:00
Pete Cooper
a77214a4c4 Changed SSE4/AVX <2 x i64> extract and insert ops to be Custom lowered
Constant idx case is still done in tablegen but other cases are then expanded

Fixes <rdar://problem/10435460>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144557 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 19:38:42 +00:00
Benjamin Kramer
b518cae015 Fold ConstantVector::isAllOnesValue into Constant::isAllOnesValue and simplify it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144555 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 19:12:20 +00:00
Akira Hatanaka
788dc0f4e5 32-to-64-bit extended load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144554 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 19:06:14 +00:00
Akira Hatanaka
4961709688 AnalyzeCallOperands function for N32/64.
N32/64 places all variable arguments in integer registers (or on stack),
regardless of their types, but follows calling convention of non-vaarg function
when it handles fixed arguments.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144553 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 19:02:54 +00:00
Akira Hatanaka
bad53f41c2 Modify LowerFormalArguments to correctly handle vaarg arguments for Mips64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144552 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 19:01:09 +00:00
Justin Holewinski
a3f7e229b6 PTX: Let LLVM use loads/stores for all mem* intrinsics, instead of relying on custom implementations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144551 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 18:58:20 +00:00
Akira Hatanaka
47a4ab84fe Remove variable that keeps the size of area used to save byval or variable
argument registers on the callee's stack frame, along with functions that set
and get it.
    
It is not necessary to add the size of this area when computing stack size in
emitPrologue, since it has already been accounted for in
PEI::calculateFrameObjectOffsets.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144549 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 18:56:20 +00:00
Jakob Stoklund Olesen
f054e19819 Fix early-clobber handling in shrinkToUses.
I broke this in r144515, it affected most ARM testers.

<rdar://problem/10441389>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144547 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 18:45:38 +00:00
Bob Wilson
96b685b4aa Disable generation of compact unwind encodings. <rdar://problem/10441578>
This still seems to be causing some failures.  It needs more testing before
it gets enabled again.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144543 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 18:21:07 +00:00
Jim Grosbach
430052b084 Tidy up. 80 column.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144538 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 17:52:47 +00:00
Benjamin Kramer
aa5354c3ba Make headers standalone, move a virtual method out of line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144536 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 17:22:45 +00:00
Chandler Carruth
f5e47ac596 It helps to deallocate memory as well as allocate it. =] This actually
cleans up all the chains allocated during the processing of each
function so that for very large inputs we don't just grow memory usage
without bound.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144533 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 10:57:23 +00:00
Chandler Carruth
bc83fcd9bd Remove an over-eager assert that was firing on one of the ARM regression
tests when I forcibly enabled block placement.

It is apparantly possible for an unanalyzable block to fallthrough to
a non-loop block. I don't actually beleive this is correct, I believe
that 'canFallThrough' is returning true needlessly for the code
construct, and I've left a bit of a FIXME on the verification code to
try to track down why this is coming up.

Anyways, removing the assert doesn't degrade the correctness of the algorithm.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144532 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 10:55:53 +00:00
Chandler Carruth
fa97658b1c Begin chipping away at one of the biggest quadratic-ish behaviors in
this pass. We're leaving already merged blocks on the worklist, and
scanning them again and again only to determine each time through that
indeed they aren't viable. We can instead remove them once we're going
to have to scan the worklist. This is the easy way to implement removing
them. If this remains on the profile (as I somewhat suspect it will), we
can get a lot more clever here, as the worklist's order is essentially
irrelevant. We can use swapping and fold the two loops to reduce
overhead even when there are many blocks on the worklist but only a few
of them are removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144531 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 09:46:33 +00:00
Chandler Carruth
340d596509 Under the hood, MBPI is doing a linear scan of every successor every
time it is queried to compute the probability of a single successor.
This makes computing the probability of every successor of a block in
sequence... really really slow. ;] This switches to a linear walk of the
successors rather than a quadratic one. One of several quadratic
behaviors slowing this pass down.

I'm not really thrilled with moving the sum code into the public
interface of MBPI, but I don't (at the moment) have ideas for a better
interface. My direction I'm thinking in for a better interface is to
have MBPI actually retain much more state and make *all* of these
queries cheap. That's a lot of work, and would require invasive changes.
Until then, this seems like the least bad (ie, least quadratic)
solution. Suggestions welcome.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144530 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 09:12:57 +00:00
Chandler Carruth
c4e1562825 Reuse the logic in getEdgeProbability within getHotSucc in order to
correctly handle blocks whose successor weights sum to more than
UINT32_MAX. This is slightly less efficient, but the entire thing is
already linear on the number of successors. Calling it within any hot
routine is a mistake, and indeed no one is calling it. It also
simplifies the code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144527 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 08:55:59 +00:00
Chandler Carruth
2770c14185 Fix an overflow bug in MachineBranchProbabilityInfo. This pass relied on
the sum of the edge weights not overflowing uint32, and crashed when
they did. This is generally safe as BranchProbabilityInfo tries to
provide this guarantee. However, the CFG can get modified during codegen
in a way that grows the *sum* of the edge weights. This doesn't seem
unreasonable (imagine just adding more blocks all with the default
weight of 16), but it is hard to come up with a case that actually
triggers 32-bit overflow. Fortuately, the single-source GCC build is
good at this. The solution isn't very pretty, but its no worse than the
previous code. We're already summing all of the edge weights on each
query, we can sum them, check for an overflow, compute a scale, and sum
them again.

I've included a *greatly* reduced test case out of the GCC source that
triggers it. It's a pretty lame test, as it clearly is just barely
triggering the overflow. I'd like to have something that is much more
definitive, but I don't understand the fundamental pattern that triggers
an explosion in the edge weight sums.

The buggy code is duplicated within this file. I'll colapse them into
a single implementation in a subsequent commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144526 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 08:50:16 +00:00
Craig Topper
dcce244dd8 Add AVX2 version of instructions to load folding tables. Also add a bunch of missing SSE/AVX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 08:07:55 +00:00
Craig Topper
3426a3efef Add neverHasSideEffects, mayLoad, and mayStore to many patternless SSE/AVX instructions. Remove MMX check from LowerVECTOR_SHUFFLE since MMX vector types won't go through it anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144522 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 06:46:21 +00:00
Chad Rosier
dc9205d9c2 Add support for ARM halfword load/stores and signed byte loads with negative
offsets.
rdar://10412592



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 04:09:28 +00:00
Jakob Stoklund Olesen
194eb71a11 Use getVNInfoBefore() when it makes sense.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 01:39:36 +00:00
Chandler Carruth
b5856c83ff Teach machine block placement to cope with unnatural loops. These don't
get loop info structures associated with them, and so we need some way
to make forward progress selecting and placing basic blocks. The
technique used here is pretty brutal -- it just scans the list of blocks
looking for the first unplaced candidate. It keeps placing blocks like
this until the CFG becomes tractable.

The cost is somewhat unfortunate, it requires allocating a vector of all
basic block pointers eagerly. I have some ideas about how to simplify
and optimize this, but I'm trying to get the logic correct first.

Thanks to Benjamin Kramer for the reduced test case out of GCC. Sadly
there are other bugs that GCC is tickling that I'm reducing and working
on now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144516 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 00:00:35 +00:00
Jakob Stoklund Olesen
6c9cc21d85 Use kill slots instead of the previous slot in shrinkToUses.
It's more natural to use the actual end points.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144515 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 23:53:25 +00:00
Chandler Carruth
c0f05b3c3f Cleanup some 80-columns violations and poor formatting. These snuck by
when I was reading through the code for style.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144513 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 22:50:09 +00:00
Jakob Stoklund Olesen
1f81e316b0 Terminate all dead defs at the dead slot instead of the 'next' slot.
This makes no difference for normal defs, but early clobber dead defs
now look like:

  [Slot_EarlyClobber; Slot_Dead)

instead of:

  [Slot_EarlyClobber; Slot_Register).

Live ranges for normal dead defs look like:

  [Slot_Register; Slot_Dead)

as before.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144512 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 22:42:13 +00:00
Jakob Stoklund Olesen
d14614e677 Simplify early clobber slots a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144507 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 22:05:42 +00:00
Chandler Carruth
10252db69b Enhance the assertion mechanisms in place to make it easier to catch
when we fail to place all the blocks of a loop. Currently this is
happening for unnatural loops, and this logic helps more immediately
point to the problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144504 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 21:39:51 +00:00
Jakob Stoklund Olesen
2debd48ca7 Rename SlotIndexes to match how they are used.
The old naming scheme (load/use/def/store) can be traced back to an old
linear scan article, but the names don't match how slots are actually
used.

The load and store slots are not needed after the deferred spill code
insertion framework was deleted.

The use and def slots don't make any sense because we are using
half-open intervals as is customary in C code, but the names suggest
closed intervals.  In reality, these slots were used to distinguish
early-clobber defs from normal defs.

The new naming scheme also has 4 slots, but the names match how the
slots are really used.  This is a purely mechanical renaming, but some
of the code makes a lot more sense now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144503 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 20:45:27 +00:00
Craig Topper
e6a6277d36 Add BLSI, BLSMSK, and BLSR to getTargetNodeName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144502 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 17:31:07 +00:00
Chandler Carruth
6527ecc918 Teach MBP to force-merge layout successors for blocks with unanalyzable
branches that also may involve fallthrough. In the case of blocks with
no fallthrough, we can still re-order the blocks profitably. For example
instruction decoding will in some cases continue past an indirect jump,
making laying out its most likely successor there profitable.

Note, no test case. I don't know how to write a test case that exercises
this logic, but it matches the described desired semantics in
discussions with Jakob and others. If anyone has a nice example of IR
that will trigger this, that would be lovely.

Also note, there are still assertion failures in real world code with
this. I'm digging into those next, now that I know this isn't the cause.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144499 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 12:17:28 +00:00
Chandler Carruth
f3fc0050ab Hoist another gross nested loop into a helper method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144498 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 11:42:26 +00:00
Chandler Carruth
729bec89bd Add a missing doxygen comment for a helper method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144497 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 11:34:55 +00:00
Chandler Carruth
9fd4e056e4 Hoist a nested loop into its own method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144496 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 11:34:53 +00:00
Chandler Carruth
df234353fb Rewrite #3 of machine block placement. This is based somewhat on the
second algorithm, but only loosely. It is more heavily based on the last
discussion I had with Andy. It continues to walk from the inner-most
loop outward, but there is a key difference. With this algorithm we
ensure that as we visit each loop, the entire loop is merged into
a single chain. At the end, the entire function is treated as a "loop",
and merged into a single chain. This chain forms the desired sequence of
blocks within the function. Switching to a single algorithm removes my
biggest problem with the previous approaches -- they had different
behavior depending on which system triggered the layout. Now there is
exactly one algorithm and one basis for the decision making.

The other key difference is how the chain is formed. This is based
heavily on the idea Andy mentioned of keeping a worklist of blocks that
are viable layout successors based on the CFG. Having this set allows us
to consistently select the best layout successor for each block. It is
expensive though.

The code here remains very rough. There is a lot that needs to be done
to clean up the code, and to make the runtime cost of this pass much
lower. Very much WIP, but this was a giant chunk of code and I'd rather
folks see it sooner than later. Everything remains behind a flag of
course.

I've added a couple of tests to exercise the issues that this iteration
was motivated by: loop structure preservation. I've also fixed one test
that was exhibiting the broken behavior of the previous version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144495 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 11:20:44 +00:00
Chad Rosier
9eb674880b The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144494 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 09:44:21 +00:00
Chad Rosier
a517ab155b Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144492 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 05:14:43 +00:00
Chad Rosier
5be833de76 Fix comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144490 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 04:25:02 +00:00
Chad Rosier
b29b950bf2 Add support for emitting both signed- and zero-extend loads. Fix
SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3).  This enables a load followed by an integer 
extend to be folded into a single load.

For example:
ldrb r1, [r0]       ldrb r1, [r0]
uxtb r2, r1     =>
mov  r3, r2         mov  r3, r1


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 02:23:59 +00:00
NAKAMURA Takumi
569561c7ee Prune more RALinScan. RALinScan was also here!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144487 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 01:33:10 +00:00
Jakob Stoklund Olesen
0cb80d9f0f More dead code elimination in VirtRegMap.
This thing is looking a lot like a virtual register map now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 01:23:34 +00:00
Jakob Stoklund Olesen
cb39064e7a Stop tracking spill slot uses in VirtRegMap.
Nobody cared, StackSlotColoring scans the instructions to find used stack
slots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 01:23:30 +00:00
Jakob Stoklund Olesen
3cb0b0edd9 Remove dead code and data from VirtRegMap.
Most of this stuff was supporting the old deferred spill code insertion
mechanism.  Modern spillers just edit machine code in place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144484 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 01:02:04 +00:00
Jakob Stoklund Olesen
929e4da68b Stop tracking unused registers in VirtRegMap.
The information was only used by the register allocator in
StackSlotColoring.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144482 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 00:39:45 +00:00
Jakob Stoklund Olesen
334575e79b Remove the -color-ss-with-regs option.
It was off by default.

The new register allocators don't have the problems that made it
necessary to reallocate registers during stack slot coloring.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144481 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 00:31:23 +00:00
Jakob Stoklund Olesen
6e49be7101 Delete VirtRegRewriter.
And there was much rejoicing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144480 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 00:16:01 +00:00
Jakob Stoklund Olesen
c3f2722615 Switch PBQP to VRM's trivial rewriter.
The very complicated VirtRegRewriter is going away.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144479 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 00:02:24 +00:00
Jakob Stoklund Olesen
f5eeaf221c Delete the old spilling framework from LiveIntervalAnalysis.
This is dead code, all register allocators use InlineSpiller.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144478 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 23:57:05 +00:00
Jakob Stoklund Olesen
5d9b109181 Delete the 'standard' spiller with used the old spilling framework.
The current register allocators all use the inline spiller.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144477 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 23:29:02 +00:00
Jakob Stoklund Olesen
cfa8101409 Switch PBQP to the modern InlineSpiller framework.
It is worth noting that the old spiller would split live ranges around
basic blocks. The new spiller doesn't do that.

PBQP should do its own live range splitting with
SplitEditor::splitSingleBlock() if desired.  See
RAGreedy::tryBlockSplit().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144476 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 23:17:52 +00:00
Jakob Stoklund Olesen
799c1ede71 Delete the linear scan register allocator.
RegAllocGreedy has been the default for six months now.

Deleting RegAllocLinearScan makes it possible to also delete
VirtRegRewriter and clean up the spiller code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144475 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 22:39:45 +00:00
Craig Topper
7be5dfd1a1 Add more AVX2 shift lowering support. Move AVX2 variable shift to use patterns instead of custom lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144457 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 09:58:49 +00:00
Nick Lewycky
d7ecff49d9 Don't try to loop on iterators that are potentially invalidated inside the loop. Fixes PR11361!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144454 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 03:09:12 +00:00
Akira Hatanaka
7386612a16 Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144453 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 02:38:12 +00:00
Akira Hatanaka
6df3e7b162 Implement Mips64's handling of byval arguments in LowerCall.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144452 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 02:34:50 +00:00
Sean Callanan
afe153c53f Fixed the MCJIT so that it can emit not only instance
methods but also class methods for Objective-C.

Clang emits Objective-C method names with '\1' at the
beginning, and the JIT has pre-existing logic to try
prepending a '\1' when searching a module for an
instance method (that is, a method whose name begins
with '-').  I simply extended it to do the same thing
when it encountered a class method (a method whose
name begins with '+').


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2011-11-12 02:31:32 +00:00
Akira Hatanaka
3a5257de21 Implement Mips64's handling of byval arguments in LowerFormalArguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144449 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 02:29:58 +00:00
Akira Hatanaka
deab22a556 64-bit arbitrary immediate pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144448 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 02:25:00 +00:00
Akira Hatanaka
2c5d65202e Function for handling byval arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144447 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 02:20:46 +00:00
Daniel Dunbar
b8ebca83f4 build: Attempt to rectify inconsistencies between CMake and LLVMBuild versions of explicit dependencies.
- The hope is that we have a tool/test to verify these are accurate (and tight) soon.

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2011-11-12 02:10:57 +00:00
Eli Friedman
75f69e3a3d Make sure scalarrepl picks the correct alloca when it rewrites a bitcast. Fixes PR11353.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144442 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 02:07:50 +00:00
Rafael Espindola
d1ac3a47f2 The dwarf standard says that the only differences between a out-of-line
instance and a concrete inlined instance are the use of DW_TAG_subprogram
instead of DW_TAG_inlined_subroutine and the who owns the tree.

We were also omitting DW_AT_inline from the abstract roots. To fix this,
make sure we mark abstract instance roots with DW_AT_inline even when
we have only out-of-line instances referring to them with DW_AT_abstract_origin.

FileCheck is not a very good tool for tests like this, maybe we should add
a -verify mode to llvm-dwarfdump.

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2011-11-12 01:57:54 +00:00
Jim Grosbach
9588c10b69 ARM refactor simple immediate asm operand render methods.
These immediate operands all use the same simple logic for rendering to
MCInst, so have them share the method for doing so.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144439 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 00:58:43 +00:00
Eli Friedman
501852423d Don't try to form pre/post-indexed loads/stores until after LegalizeDAG runs. Fixes PR11029.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144438 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 00:35:34 +00:00
Jim Grosbach
742c4bac07 Re-apply 144430, this time with the associated isel and disassmbler bits.
Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.'

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2011-11-12 00:31:53 +00:00
Eli Friedman
0e3642a587 Some cleanup and bulletproofing for node replacement in LegalizeDAG. To maintain LegalizeDAG invariants, whenever we a node is replaced, we must attempt to delete it, and if it still
has uses after it is replaced (which can happen in rare cases due to CSE), we must revisit it.



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2011-11-11 23:58:27 +00:00
Jim Grosbach
4d06138d53 Oops. Missed the isel half of this. revert while I sort that out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144431 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 23:51:31 +00:00
Jim Grosbach
10a630dea6 ARM assembly parsing for VST1 two-register encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144430 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 23:45:47 +00:00
Jim Grosbach
c7352f8ca0 ARM optional size suffix for VLDR/VSTR syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144427 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 23:34:43 +00:00
Chad Rosier
11add26ec2 Add support in fast-isel for selecting memset/memcpy/memmove intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144426 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 23:31:03 +00:00
Daniel Dunbar
b12f97534c CMake: Fix CMake build for new Mips tblgen file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144423 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 23:12:56 +00:00
Jim Grosbach
7aef99b677 ARM vldm and vstm VFP instructions can take a data type suffix.
It's ignored by the assembler when present, but is legal syntax. Other
instructions have something similar, but for some mnemonics it's
only sometimes not significant, so this quick check in the parser will
need refactored into something more robust soon-ish. This gets some
basics working in the meantime.

Partial for rdar://10435264

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2011-11-11 23:08:10 +00:00
Daniel Dunbar
8396893fa5 LLVMBuild: Alphabetize required_libraries lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144416 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 22:59:23 +00:00
Daniel Dunbar
f779757ceb Target/LLVMBuild: Order components alphabetically.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144415 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 22:59:16 +00:00
Bruno Cardoso Lopes
47b92f3d83 Mips MC object code emission improvements:
"With this patch we can now generate runnable Mips code through LLVM
direct object emission. We have run numerous simple programs, both C
and C++ and with -O0 and -O3 from the output. The code is not production
ready, but quite useful for experimentation." Patch and message by
Jack Carter

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2011-11-11 22:58:42 +00:00
Jim Grosbach
c3937b97c0 Nuke no longer accurate comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144411 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 22:30:06 +00:00
Andrew Trick
95bc85e4ee Preserve MachineMemOperands in ARMLoadStoreOptimizer.
Fixes PR8113.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144409 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 22:18:09 +00:00
Jim Grosbach
ce485e7f70 ARM allow Q registers in vldm/vstm register lists.
rdar://9672822

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144407 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 21:27:40 +00:00
Nicolas Geoffray
7b8c2f8587 Add a custom safepoint method, in order for language implementers to decide which machine instruction gets to be a safepoint.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144399 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 18:32:52 +00:00
Bob Wilson
900b16b99d Remove FIXME comment that should have been removed with r144351.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144392 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 17:34:14 +00:00
Dan Bailey
96e6458903 allow non-device function calls in PTX when natively handling device-side printf
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144388 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 14:45:12 +00:00
Dan Bailey
b812ee6d78 add rules in tabgen for PTX COPY_ADDRESS of frameindex
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144387 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 14:45:06 +00:00
Benjamin Kramer
178051fbae Clients are responsible for initializing the targets, remove it from the disassembler API.
This will break users of the LLVMCreateDisasm API (not that I know of any). They have to call the 
LLVMInitializeAll* functions from llvm-c/Target.h themselves now. edis' C API in all its horribleness 
should be unaffected.

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2011-11-11 13:20:40 +00:00
Benjamin Kramer
eea66f63d9 Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144384 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 12:39:41 +00:00
Benjamin Kramer
7fb12ef5a6 Remove the unnecessary dependency on libMBlazeCodeGen from libMBlazeDisassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144383 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 12:39:35 +00:00
Craig Topper
46154eb6fd Add lowering for AVX2 shift instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144380 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 07:39:23 +00:00
Chad Rosier
1c47de87c7 Rename variables to avoid confusion. No functionallity change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144377 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 06:27:41 +00:00
Chad Rosier
a07d3fc693 Add support for using immediates with select instructions.
rdar://10412592


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144376 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 06:20:39 +00:00
Akira Hatanaka
e184fec550 Do not try to detect DAG combine patterns for integer multiply-add/sub if value
type is not i32. MIPS does not have 64-bit integer multiply-add/sub
instructions.


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2011-11-11 04:18:21 +00:00
Akira Hatanaka
59068067cb 64-bit atomic instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144372 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 04:14:30 +00:00
Akira Hatanaka
46ac4399b1 Modify LowerFRAMEADDR. Use 64-bit register FP_64 when ABI is N64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144371 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 04:11:56 +00:00
Akira Hatanaka
c742e4fc90 Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144370 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 04:06:38 +00:00
Akira Hatanaka
642b109713 64-bit versions of jal, jalr and bal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144368 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 04:03:54 +00:00
Akira Hatanaka
a1fa08f66a Emit Mips64's sequence of instructions that set global register in prologue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144367 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 04:00:29 +00:00
Akira Hatanaka
d5cf5a631f Fix printing of MCSymbolRegExpr. Needs three closing parentheses for
VK_Mips_GPOFF_HI/LO.



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2011-11-11 03:58:36 +00:00
Eli Friedman
15f58c56e9 Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144361 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 03:16:38 +00:00
Eric Christopher
d61c34ba30 Initialize variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144360 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 03:16:32 +00:00
Chad Rosier
646abbfa30 When loading a value, treat an i1 as an i8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144356 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 02:38:59 +00:00
Eric Christopher
d117fbb231 If we have a DIE with an AT_specification use that instead of the normal
addr DIE when adding to the dwarf accelerator tables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144354 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 01:55:22 +00:00
Eli Friedman
b80f778bd3 Get rid of an optimization in SCCP which appears to have many issues. Specifically, it doesn't handle many cases involving undef correctly, and it is missing other checks which
lead to it trying to re-mark a value marked as a constant with a different value.  It also appears to trigger very rarely.

Fixes PR11357.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144352 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 01:16:15 +00:00
Bill Wendling
cf3b89f9a8 Reenable compact unwinding now that <rdar://problem/10430076> is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144351 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 01:03:50 +00:00
Bill Wendling
c739577d3c If we have to reset the calculation of the compact encoding, then also reset the
"saved register" index.
<rdar://problem/10430076>


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2011-11-11 00:59:14 +00:00
Chad Rosier
4e89d97e3a Add support for using MVN to materialize negative constants.
rdar://10412592

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144348 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 00:36:21 +00:00
Bill Wendling
7b809e08b9 Disable compact unwind generation until I can solve the codegen problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144346 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 00:28:42 +00:00
Daniel Dunbar
5ed5506f18 LLVMBuild: Add explicit information on whether targets define an assembly printer, assembly parser, or disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144344 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 00:23:56 +00:00
Jim Grosbach
0352b4679e Thumb2 ldm/stm updating w/ one register in the list are LDR/STR.
rdar://10429490

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144338 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 23:58:34 +00:00
Jim Grosbach
83ec87755e ARM let processInstruction() tranforms chain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144337 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 23:42:14 +00:00
Jim Grosbach
5402637ff2 Thumb2 parsing for push/pop w/ hi registers in the reglist.
rdar://10130228.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144331 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 23:17:11 +00:00
Jim Grosbach
fae02597bb Thumb1 diagnostics for reglist on PUSH/POP fix.
Was not checking the first register in the register list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144329 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 23:01:27 +00:00
Rafael Espindola
01b55b4a80 Check in getOrCreateSubprogramDIE if a declaration exists and if so output
it first.

This is a more general fix to pr11300.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144324 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 22:34:29 +00:00
Jim Grosbach
1b332860ae Thumb MUL assembly parsing for 3-operand form.
Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.

rdar://10428630

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 22:10:12 +00:00