Commit Graph

156698 Commits

Author SHA1 Message Date
Bob Haarman
d4f1cfbb84 LTO: don't fatal when value for cache key already exists
Summary:
LTO/Caching.cpp uses file rename to atomically set the value for a
cache key. On Windows, this fails when the destination file already
exists. Previously, LLVM would report_fatal_error in such
cases. However, because the old and the new value for the cache key
are supposed to be equivalent, it actually doesn't matter which one we
keep. This change makes it so that failing the rename when an openable
file with the desired name already exists causes us to report success
instead of fataling.

Reviewers: pcc, hans

Subscribers: mehdi_amini, llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D39874

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317899 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 17:08:21 +00:00
Adrian Prantl
dc7bbb86a4 Move test into X86 subdirectory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317896 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 16:36:04 +00:00
Jatin Bhateja
be808009ac [WebAssembly] Fix stack offsets of return values from call lowering.
Summary: Fixes PR35220

Reviewers: vadimcn, alexcrichton

Reviewed By: alexcrichton

Subscribers: pepyakin, alexcrichton, jfb, dschuff, sbc100, jgravelle-google, llvm-commits, aheejin

Differential Revision: https://reviews.llvm.org/D39866

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317895 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 16:26:04 +00:00
Florian Hahn
9239900417 [AArch64][SVE] Asm: More concise test format
Change the test format for SVE assembler/disassembler tests to be less verbose and have both tests in the same file.

The tests check the following:

 * All instructions are assembled correctly into the right encoding.
 * All instructions are disassembled correctly (into the preferred assembly format)
 * Without -mattr=+sve the instructions are not assembled.
 * Without -mattr=+sve the instructions are not disassembled.

This patch also adds several negative tests for SVE add/sub.


Patch by Sander De Smalen.

Reviewed by: rengolin, fhahn

Differential Revision: https://reviews.llvm.org/D39792


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317894 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 16:25:16 +00:00
Simon Pilgrim
3343c3a754 [X86] Add scheduling tests for DAA/DAS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317892 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 15:49:41 +00:00
Igor Laevsky
68960b1207 [llvm-opt-fuzzer] Add missed library dependence. Fir for rL317883
Differential Revision: https://reviews.llvm.org/D39555




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317889 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 15:08:14 +00:00
Simon Pilgrim
41ecf7e107 [X86] Test non-i64 shld/shll tests on x86_64 targets as well as i686
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317888 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 13:43:04 +00:00
Igor Laevsky
224217d714 [llvm-opt-fuzzer] Fix unused variable warning after rL317883
Differential Revision: https://reviews.llvm.org/D39555



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317887 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 13:19:14 +00:00
Simon Pilgrim
7702921068 [X86] Add scheduling tests
- CBW etc sign extensions
 - CLC/CLD/CMC flag modifiers
 - CPUID

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317885 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 12:32:34 +00:00
Alexander Timofeev
23476c4f80 [AMDGPU] Prevent Machine Copy Propagation from replacing live copy with the dead one
Differential revision: https://reviews.llvm.org/D38754

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317884 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 12:21:10 +00:00
Igor Laevsky
089f886ad9 [llvm-opt-fuzzer] Introduce llvm-opt-fuzzer for fuzzing optimization passes
This change adds generic fuzzing tools capable of running libFuzzer tests on
any optimization pass or combination of them.

Differential Revision: https://reviews.llvm.org/D39555



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317883 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 12:19:08 +00:00
Simon Pilgrim
d84a31be44 [X86] Added TODO list for missing generic x86 instruction scheduling tests.
Not sure if we want to add the more exotic system instructions (IRET etc.) as well?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317882 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 12:04:39 +00:00
Karl-Johan Karlsson
823bedeb8e [RegisterCoalescer] Move debug value after rematerialize trivial def
Summary:
The associated debug value is updated when the virtual source register
of a copy is completely eliminated and replaced with a rematerialize
value in the defed register of the copy. As the debug value now is
associated with another register it also need to be moved, otherwise
the debug value isn't valid.

Reviewers: aprantl

Reviewed By: aprantl

Subscribers: MatzeB, llvm-commits, qcolombet

Differential Revision: https://reviews.llvm.org/D38024

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317880 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 09:48:40 +00:00
Jonas Paulsson
a9fba7123d [RegAlloc, SystemZ] Increase number of LOCRs by passing "hard" regalloc hints.
* The method getRegAllocationHints() is now of bool type instead of void. If
true is returned, regalloc (AllocationOrder) will *only* try to allocate the
hints, as opposed to merely trying them before non-hinted registers.

* TargetRegisterInfo::getRegAllocationHints() is implemented for SystemZ with
an increase in number of LOCRs.

In this case, it is desired to force the hints even though there is a slight
increase in spilling, because if a non-hinted register would be allocated,
the LOCRMux pseudo would have to be expanded with a jump sequence. The LOCR
(Load On Condition) SystemZ instruction must have both operands in either the
low or high part of the 64 bit register.

Reviewers: Quentin Colombet and Ulrich Weigand
https://reviews.llvm.org/D36795

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317879 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 08:46:26 +00:00
Craig Topper
cad7a316e0 [X86] Add support for combining FMADDSUB(A, B, FNEG(C))->FMSUBADD(A, B, C)
Support the opposite direction as well. Also add a TODO for not being able to combine FMSUB/FNMADD/FNMSUB with FNEG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317878 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 08:22:37 +00:00
Craig Topper
f737152c33 [X86] Remove GCCBuiltin from intrinsics that are no longer used by clang.
I've also added TODOs for intrinsic removal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317876 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 06:07:37 +00:00
Yaxun Liu
bd2cfd038d [AMDGPU] Fix pointer info for lowering load/store for r600 for amdgiz environment
r600 uses dummy pointer info for lowering load/store. Since dummy pointer info
assumes address space 0, this causes isel failure when temporary load/store SDNodes
are generated for amdgiz environment.

Since the offest is not constant, FixedStack pseudo source value cannot be used
to create the pointer info. This patch creates pointer info using llvm undef value.
At least this provides correct address space so that isel can be done correctly.

Differential Revision: https://reviews.llvm.org/D39698


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317862 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 02:03:28 +00:00
Yaxun Liu
d3bd6cf5cc [AMDGPU] Fix pointer info for pseudo source for r600
The pointer info for pseudo source for r600 is not correct when
alloca addr space is not 0, which causes invalid SDNode for r600---amdgiz.

This patch fixes that.

Differential Revision: https://reviews.llvm.org/D39670


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317861 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 01:53:24 +00:00
Tony Tye
9000e8c60d [AMDGPU] Update code object description
- Use ELF header flags to identify processor.
 - Remove isa note record.
 - Add target feature section.
 - Make metadata for NumVGPRs, NumSGPRs and MaxFlatWorkGroupSize required.
 - Add FixedWorkGroupSize to CodeProps metadata.
 - Add ReqdWorkGroupSize* to kernel descriptor and move MaxFlatWorkGroupSize to be adjacent.
 - Move IsXNACKEnabled in the kernel descriptor to be at the end of the unused flags.
 - Remove IsDynamicCallStack from the metadata and kernel descriptor.
 - Remove legacy debugger metadata.
 - Remove old XNACK enabled processor names.

Differential Revision: https://reviews.llvm.org/D39828


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317855 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 01:00:54 +00:00
Volodymyr Sapsai
8887214dfa [ThinLTO] Fix missing call graph edges for calls with bitcasts.
This change doesn't fix the root cause of the miscompile PR34966 as the root
cause is in the linker ld64. This change makes call graph more complete
allowing to have better module imports/exports.

rdar://problem/35344706

Reviewers: tejohnson

Reviewed By: tejohnson

Subscribers: mehdi_amini, inglorion, eraman, llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D39356



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317853 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 00:47:47 +00:00
Bob Haarman
37ff1dce27 [support] allocate exact size required for mapping in Support/Windws/Path.inc
Summary:
zturner suggested that mapped_file_region::init() on Windows seems to
create mappings that are larger than they need to be: Offset+Size
instead of Size. Indeed, that appears to be the case. I confirmed that
tests pass with mappings of just Size bytes, and fail with Size-1
bytes, suggesting that Size is indeed the correct value.

Reviewers: amccarth, zturner

Reviewed By: zturner

Subscribers: hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D39876

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317850 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 00:17:31 +00:00
Easwaran Raman
68d2cebf10 [SimplifyCFG] Fix a test case.
This was first committed in r317845, but had the order of branch weights
wrong and didn't properly check the output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317848 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 23:17:52 +00:00
Easwaran Raman
2f88f54e97 Add a wrapper function to set branch weights metadata.
Summary:
This wrapper checks if there is at least one non-zero weight before
setting the metadata.

Reviewers: davidxl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D39872

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317845 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 22:52:20 +00:00
Sanjay Patel
e69c03b3a1 [Reassociate] regenerate test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317841 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 22:41:39 +00:00
Kostya Serebryany
5808caed59 [libFuzzer] update links in the docs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317837 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 21:35:28 +00:00
Kostya Serebryany
05ceafb725 [libFuzzer] update the docs, document how to resume the merge
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317836 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 21:32:02 +00:00
Zachary Turner
c54ecd0482 Add a Cross-compilation toolchain file for MSVC.
With this patch, you can now cross-compile for Windows
on non-Windows hosts.

Differential Revision: https://reviews.llvm.org/D39814

This allows cross-compiling for windows on other platforms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317830 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 20:38:16 +00:00
Paul Robinson
4c7c4551f2 Fix out-of-order stepping behavior in programs with hoisted constants.
When the Constant Hoisting pass moves expensive constants into a
common block, it would assign a debug location equal to the last use
of that constant. While this is certainly intuitive, it places the
constant in an out-of-order location, according to the debug location
information. This produces out-of-order stepping when debugging
programs affected by this pass.

This patch creates in-order stepping behavior by merging the debug
locations for hoisted constants, and the new insertion point.

Patch by Matthew Voss!

Differential Revision: https://reviews.llvm.org/D38088

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317827 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 20:01:31 +00:00
Alex Bradbury
3fa053b41c [utils] Fix RISC-V support in update_llc_test_checks.py
scrub_asm_riscv now takes two arguments rather than one.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317826 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 20:01:25 +00:00
Adrian Prantl
13c8bc9216 Preserve debug info when DAG-combinging (zext (truncate x)) -> (and x, mask).
rdar://problem/27139077

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317825 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 19:50:20 +00:00
Zachary Turner
eef29544df [Support] Make llvm::Error and Expected faster.
Whenever LLVM_ENABLE_ABI_BREAKING_CHECKS is enabled, which
is usually the case for example when asserts are enabled,
Error's destructor does some additional checking to make sure
that that it does not represent an error condition and that it
was checked.

However, this is -- by definition -- not the likely codepath.
Some profiling shows that at least with some compilers, simply
calling assertIsChecked -- in a release build with full
optimizations -- can account for up to 15% of the entire
runtime of the program, even though this function should almost
literally be a no-op.

The problem is that the assertIsChecked function can be considered
too big to inline depending on the compiler's inliner.  Since it's
unlikely to ever need to failure path though, we can move it out
of line and force it to not be inlined, so that the fast path
can be inlined.

In my test (using lld to link clang with CMAKE_BUILD_TYPE=Release
and LLVM_ENABLE_ASSERTIONS=ON), this reduces link time from 27
seconds to 23.5 seconds, which is a solid 15% gain.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317824 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 19:31:52 +00:00
Alexey Bataev
9daf9c5c89 [SLP] Fix PR23510: Try to find best possible vectorizable stores.
Summary:
The analysis of the store sequence goes in straight order - from the
first store to the last. Bu the best opportunity for vectorization will
happen if we're going to use reverse order - from last store to the
first. It may be best because usually users have some initialization
part + further processing and this first initialization may confuse
SLP vectorizer.

Reviewers: RKSimon, hfinkel, mkuper, spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D39606

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317821 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 19:07:16 +00:00
Sanjay Patel
8b45407e72 [Reassociate] auto-generate test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317819 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 18:26:49 +00:00
Sanjay Patel
114cb60a37 [Reassociate] don't name values "tmp"; NFCI
The toxic stew of created values named 'tmp' and tests that already have
values named 'tmp' and CHECK lines looking for values named 'tmp' causes
bad things to happen in our test line auto-generation scripts because it
wants to use 'TMP' as a prefix for unnamed values. Use less 'tmp' to 
avoid that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317818 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 18:14:24 +00:00
Mandeep Singh Grang
d28baf6183 [GlobalMerge] Stable sort GlobalSets to fix non-deterministic sort order
Summary: This fixes failure in CodeGen/AArch64/global-merge-group-by-use.ll uncovered by D39245.

Reviewers: ab, asl

Reviewed By: ab

Subscribers: aemerson, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D39635

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317817 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 18:05:17 +00:00
Nuno Lopes
06f6588caf revert r317812 [BasicAA] fix build break by converting the previously introduced assert into an if stmt
The code has a bug, but some tests regress.
I'll discuss this further on the mailing list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317815 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 17:35:36 +00:00
Nuno Lopes
d90f53e14a [BasicAA] fix build break by converting the previously introduced assert into an if stmt
Apparently V1Size == -1 doest imply V2Size == -1, which is a bit surprising to me.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317812 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 17:06:42 +00:00
Sanjay Patel
3b01bb69f0 revert r317809 - [Reassociate] regenerate test checks; NFC
The reassociate pass generates named values such as "%tmp2" which trips up the script's regex's
because the script uses a 'TMP' prefix for unnamed values (%2).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317810 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 16:46:04 +00:00
Sanjay Patel
0e0f70edce [Reassociate] regenerate test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317809 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 16:35:30 +00:00
Ulrich Weigand
b9cdeecf25 [SystemZ] Add support for the "o" inline asm constraint
We don't really need any special handling of "offsettable"
memory addresses, but since some existing code uses inline
asm statements with the "o" constraint, add support for this
constraint for compatibility purposes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317807 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 16:31:57 +00:00
Sanjay Patel
60d2d2eec0 [Reassociate] regenerate test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317806 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 16:30:19 +00:00
Sanjay Patel
c7ddf7c3bc [Reassociate] add check lines; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317805 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 16:25:35 +00:00
Sanjay Patel
7f4962a61a [Reassociate] add tests with 'reassoc' FMF and regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317804 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 16:23:32 +00:00
Nuno Lopes
b0957fa675 [BasicAA] add assertion for corner case in aliasGEP()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317803 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 16:16:46 +00:00
Simon Dardis
5be95c6164 [mips] Correct microMIP's jump and add unconditional branch pseudo
Correct the definition of 'j' as being unavailable for microMIPS32R6 and
provide the 'b' assembly idiom for codegen purposes for microMIPS32r3.

Provide the necessary 'br' pattern for microMIPS32R6 as it now longer
incorrectly uses the 'j' instruction.

Reviewers: atanasyan

Differential Revision: https://reviews.llvm.org/D39741


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317801 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 16:02:18 +00:00
Alex Bradbury
2fe0076f87 [RISCV] Re-generate test/CodeGen/RISCV/alu32.ll using update_llc_test_checks.py
No real change, but makes it marginally easier to merge the remainder of the
out-of-tree patches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317796 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 15:45:42 +00:00
Alex Bradbury
d99baa702c [RISCV] MC layer support for the standard RV32A instruction set extension
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317791 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 15:00:03 +00:00
Simon Pilgrim
2ef1ea6408 Fix 'not all control paths return a value' warning on MSVC builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317790 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 14:56:17 +00:00
Dave Lee
9a5be1f566 Reapply: Allow yaml2obj to order implicit sections for ELF
Summary:
This change allows yaml input to control the order of implicitly added sections
(`.symtab`, `.strtab`, `.shstrtab`). The order is controlled by adding a
placeholder section of the given name to the Sections field.

This change is to support changes in D39582, where it is desirable to control
the location of the `.dynsym` section.

This reapplied version fixes:
  1. use of a function call within an assert
  2. failing lld test which has an unnamed section
  3. incorrect section count when given an unnamed section

Additionally, one more test to cover the unnamed section failure.

Reviewers: compnerd, jakehehrlich

Reviewed By: jakehehrlich

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D39749

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317789 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 14:53:43 +00:00
Alex Bradbury
f8c0f51efe [RISCV] MC layer support for the standard RV32M instruction set extension
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317788 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 14:46:30 +00:00