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12733 Commits

Author SHA1 Message Date
Unknown W. Brackets
259734bd47 irjit: Fix likely delay slot breakpoints. 2023-09-03 12:27:10 -07:00
Unknown W. Brackets
e1a1f56f4c irjit: Cleanup breakpoint ops. 2023-09-03 12:27:10 -07:00
Unknown W. Brackets
7607280837 arm64jit: Implement just the most basic ops. 
This improves the slowness a good bit.
 2023-09-03 12:20:16 -07:00
Unknown W. Brackets
1b756ff8c1 arm64jit: Add initial base for IR jit. 
This works, but very slowly at this point.
 2023-09-03 12:14:28 -07:00
Henrik Rydgård
8a5e4d3591
Merge pull request #18054 from unknownbrackets/memblockinfo 
HLE: Capture better allocation names
 2023-09-03 10:38:03 +02:00
Unknown W. Brackets
c7304eccdb x86jit: Avoid R15 for jitbase if near ctxreg. 2023-09-02 23:05:56 -07:00
Unknown W. Brackets
32feb82d16 HLE: Capture better allocation names. 
We know which FPL, so don't just say "FPL".
 2023-09-02 22:55:45 -07:00
Henrik Rydgård
f6c1493373
Merge pull request #18048 from unknownbrackets/irjit-vec4 
IR: Add a pass to keep things in vec4 more
 2023-09-02 15:11:06 +02:00
Henrik Rydgård
20dedec07e
Merge pull request #18046 from unknownbrackets/x86-jit-reduce 
x86jit: Reduce bloat further
 2023-09-02 13:37:20 +02:00
Unknown W. Brackets
739e474957 irjit: Improve dot and store vec4 interaction. 2023-09-01 22:35:59 -07:00
Unknown W. Brackets
becad54923 x86jit: Maintain Vec4 on FMov extract. 2023-09-01 22:35:59 -07:00
Unknown W. Brackets
2ca638868c irjit: Remove Vec4Scale/Vec4Dot aliasing in pass. 2023-09-01 22:35:59 -07:00
Unknown W. Brackets
96c90c19c6 irjit: Reduce unnecessary shuffles. 
If it's never used as a Vec4 again, it's often not worth it.
 2023-09-01 22:35:59 -07:00
Unknown W. Brackets
5f84887dea irjit: Add a pass to keep Vec4s in Vec4s. 2023-09-01 22:35:59 -07:00
Unknown W. Brackets
9bac755491 x86jit: Avoid pointerify if clobbered. 
For x86, it's not worth it for one.
 2023-09-01 22:34:22 -07:00
Unknown W. Brackets
b370a89ef2 x86jit: Reduce block link padding. 
Reduces bloat a good bit.
 2023-09-01 22:33:02 -07:00
Unknown W. Brackets
c5d0e1d0cc x86jit: Implement float to integer. 2023-09-01 22:31:25 -07:00
Unknown W. Brackets
c85886c11e irjit: Use enum for rounding modes. 2023-09-01 22:29:24 -07:00
iota97
01083c87ea Analog stick gesture 2023-09-01 09:32:21 +02:00
Henrik Rydgård
ce47055860 Touch controls: Add an option for "Sticky D-Pad". 
Will make it a lot easier to pull off certain moves in fighting games.

Should help #17950
 2023-08-31 22:37:11 +02:00
Henrik Rydgård
7a3eab9bfd
Merge pull request #18027 from unknownbrackets/memblockinfo 
Debugger: Reduce cost of small copy tracking
 2023-08-31 13:17:27 +02:00
Henrik Rydgård
ad1f378902 Also simplify __CtrlUpdateButtons to only do a single read and write to the global. 2023-08-31 11:10:02 +02:00
Unknown W. Brackets
d5c91fa02c Debugger: Reduce cost of small copy tracking. 
This uses another 400KB RAM and does a bit more writing, but makes lookups
faster.
 2023-08-31 00:17:30 -07:00
Henrik Rydgård
351de6eb25
Merge pull request #18026 from unknownbrackets/x86-jit-float 
x86jit: Fix vsat0 saturate
 2023-08-31 08:28:50 +02:00
Henrik Rydgård
fbc1fc417e
Merge pull request #18025 from unknownbrackets/x86-jit-regcache 
x86jit: Fix a vec4 clobber issue
 2023-08-31 08:20:01 +02:00
Unknown W. Brackets
bcac804cc5 x86jit: Fix vsat0 saturate. 2023-08-30 23:07:57 -07:00
Unknown W. Brackets
d5a51da95e x86jit: Fix pointer modify when masked. 2023-08-30 22:04:26 -07:00
Unknown W. Brackets
742dc0a0c7 x86jit: Fix vec4 clobber issue. 2023-08-30 22:04:25 -07:00
Henrik Rydgård
3d0051f34b Fix enabling of native keyboard input on Switch 2023-08-30 18:14:17 +02:00
Henrik Rydgård
5321cb97fd
Merge pull request #18007 from unknownbrackets/x86-jit-lsu 
x86jit: Implement CondStore
 2023-08-29 09:06:43 +02:00
Unknown W. Brackets
8233fdfd91 x86jit: Implement CondStore. 2023-08-28 23:32:49 -07:00
Unknown W. Brackets
181adde6f1 x86jit: Implement float saturates. 2023-08-28 23:11:46 -07:00
Unknown W. Brackets
c4d13e522b x86jit: Use a literal pool to avoid rip checks. 2023-08-28 23:11:46 -07:00
Unknown W. Brackets
eab05e32a7 x86jit: Implement FCvtScaledSW. 2023-08-28 23:11:46 -07:00
Unknown W. Brackets
2b6bd01417 x86jit: Optimize FMul. 2023-08-28 23:11:46 -07:00
Henrik Rydgård
ae0af175de
Merge pull request #18004 from unknownbrackets/x86-jit-minor 
x86jit: Small cleanup and tweaks, downcountInRegster, GetFPRLaneCount bugfix
 2023-08-29 08:01:47 +02:00
Unknown W. Brackets
0cb6a17ea3 x86jit: Small Clz codesize optimization. 2023-08-28 21:17:06 -07:00
Unknown W. Brackets
14d871730f x86jit: Optimize slow memory. 2023-08-28 21:16:38 -07:00
Unknown W. Brackets
1bfa054a41 irjit: Correct GetFPRLaneCount(). 
Oops, this was just wrong...
 2023-08-28 21:09:56 -07:00
Unknown W. Brackets
75e20af886 x86jit: Fix default prefix on core switch. 2023-08-28 21:09:56 -07:00
Unknown W. Brackets
8e8605935e irjit: Detect subtract-to-zero as constant. 2023-08-28 21:09:56 -07:00
Unknown W. Brackets
0a5eafa3de x86jit: Another small LEA optimization. 2023-08-28 21:09:56 -07:00
Unknown W. Brackets
289cb71790 x86jit: Small tweaks to fixed code. 2023-08-28 21:09:56 -07:00
Unknown W. Brackets
ee5381917a x86jit: Implement downcount in register. 2023-08-28 21:09:56 -07:00
Unknown W. Brackets
7f3e2e55b5 x86jit: Small opt for Sltu. 2023-08-28 21:09:56 -07:00
Unknown W. Brackets
4e90bd5070 x86jit: Use NEG more automatically for Sub x,0,y. 2023-08-28 21:09:56 -07:00
Henrik Rydgård
9291a4e52a
Merge pull request #17998 from hrydgard/minor-fixes 
Minor: Correct RA login retry behavior if disabled, improved logging in CLUTLoad case
 2023-08-28 16:09:34 +02:00
Henrik Rydgård
9e708fc82d Don't show RetroAchievements login failures (and don't retry) if the user has disabled them. 2023-08-28 14:38:32 +02:00
Henrik Rydgård
b637a9c42e Upgrade rcheevos to latest 
The timer issue has been fixed upstream. Hopefully nothing will regress on
32-bit Android this time.

See #17631
 2023-08-28 14:09:46 +02:00
Henrik Rydgård
26af6eb569 RetroAchievements: More connection notifications 
Trying to make it harder for a user to accidentally run without achievements enabled.
 2023-08-28 12:15:24 +02:00
Henrik Rydgård
dddf63d057
Merge pull request #17993 from unknownbrackets/x86-jit-minor 
x86jit: Replacements, expose for profiling better
 2023-08-28 10:23:00 +02:00
Henrik Rydgård
0ecfb6b112
Merge pull request #17992 from unknownbrackets/x86-jit-float 
x86jit: Implement trig instructions, couple other FPU
 2023-08-28 10:20:38 +02:00
Henrik Rydgård
54ebe461fc
Merge pull request #17994 from unknownbrackets/x86-jit-lea 
x86: Use LEA in a few sensible places
 2023-08-28 10:17:13 +02:00
Henrik Rydgård
24e0cb013b
Merge pull request #17991 from unknownbrackets/x86-jit-dot 
x86jit: Improve vdot performance
 2023-08-28 10:15:03 +02:00
Henrik Rydgård
3489ff5143
Merge pull request #17990 from unknownbrackets/x86-jit-alu 
x86jit: Implement divides and a couple more ALUs
 2023-08-28 10:12:31 +02:00
Unknown W. Brackets
f10444eb42 x86jit: Special case broadcast shuffles. 2023-08-27 23:24:30 -07:00
Unknown W. Brackets
61a99b4bac x86jit: Implement trig/reciprocals. 2023-08-27 23:24:30 -07:00
Unknown W. Brackets
4b1c809886 x86jit: Implement a few more float ops, shuffle. 2023-08-27 23:24:30 -07:00
Unknown W. Brackets
479ebaea11 x86: Use LEA in a few sensible places. 2023-08-27 13:59:19 -07:00
Unknown W. Brackets
8b77114da6 x86jit: Remove outdated file. 2023-08-27 13:01:22 -07:00
Unknown W. Brackets
2e64abd2a0 x86jit: Improve some debug labels. 
Helps when running a profiler that reads these.
 2023-08-27 12:51:29 -07:00
Unknown W. Brackets
303aa0548c x86jit: Handle replacements directly. 2023-08-27 12:51:24 -07:00
Unknown W. Brackets
35fe15d718 x86jit: Do not use Vec4Dot for vdot.t. 
It was much slower to do so in LittleBigPlanet.
 2023-08-27 12:39:21 -07:00
Unknown W. Brackets
1abd3ac361 x86jit: Use a faster vdot than DPPS. 2023-08-27 12:39:08 -07:00
Unknown W. Brackets
497fc09c29 x86jit: Implement divides. 2023-08-27 12:34:58 -07:00
Unknown W. Brackets
1b25f854a1 x86jit: Reduce code size a tiny bit. 2023-08-27 12:34:58 -07:00
Unknown W. Brackets
2231fb807b x86jit: Implement Clz, Not, XorConst. 2023-08-27 12:34:58 -07:00
Unknown W. Brackets
7d8dc0f8ab irjit: Detect clobber in lane change. 2023-08-27 12:27:05 -07:00
Unknown W. Brackets
6507251e83 irjit: Consider temps clobbered by block end. 2023-08-27 12:26:42 -07:00
Unknown W. Brackets
f263698897 irjit: Cleanup temp purging on exit. 
We were sometimes considering it read by exit and not purging.
 2023-08-27 12:26:05 -07:00
Henrik Rydgård
def25100df RetroAchievements: Warn the user if has token and not logged in. 2023-08-26 13:27:10 +02:00
Henrik Rydgård
5779e37f55
Merge pull request #17982 from ANR2ME/adhoc 
[Adhoc] An attempt to fix winsock error 10022 on Monster Hunter Freedom
 2023-08-26 07:14:13 +02:00
ANR2ME
270943dd59 Show socket id in Info Log when successfully created/accepted. 2023-08-26 06:43:24 +07:00
ANR2ME
47efec2782 Treat WSAEINVAL similar to WSAEALREADY during connect for backward-compatibility to Winsock 1.1, but might confuses with an actual invalid argument error on newer Winsock. 2023-08-26 06:25:09 +07:00
Henrik Rydgård
a70b36671a Show the RetroAchievements icon in a bunch of notifications 2023-08-25 16:36:29 +02:00
Henrik Rydgård
6d28ccbd8e Add HTTP log channel, and make ACHIEVEMENTS a proper one. 2023-08-25 13:53:46 +02:00
Henrik Rydgård
c59e9e51b2 Non-change to see if CI fixes itself.. 2023-08-25 12:39:19 +02:00
Henrik Rydgård
1025bbcf89 Log level/type: Use enum class instead of the awkward namespace trick. 
Just a small cleanup I've wanted to do for a long time.
 2023-08-25 11:48:59 +02:00
Henrik Rydgård
308e983a99
Merge pull request #17975 from unknownbrackets/x86-jit-ir 
More x86 IR JIT
 2023-08-25 09:41:38 +02:00
Unknown W. Brackets
be4fe52796 x86jit: A few more float ops. 2023-08-25 00:01:03 -07:00
Unknown W. Brackets
d021706eb3 x86jit: Implement conditional assigns. 2023-08-25 00:01:03 -07:00
Unknown W. Brackets
d1a30334bf x86jit: Implement multiplies. 2023-08-25 00:01:03 -07:00
Unknown W. Brackets
363f2b68e1 x86jit: Implement shifts. 2023-08-25 00:01:03 -07:00
Unknown W. Brackets
601bf344c1 x86jit: Implement vdot. 2023-08-25 00:01:03 -07:00
Unknown W. Brackets
bfb8df8472 x86jit: Implement fneg/abs. 2023-08-25 00:01:02 -07:00
Unknown W. Brackets
004c35cf76 x86jit: Implement syscalls and some system. 2023-08-25 00:01:02 -07:00
Unknown W. Brackets
2fbdc42a5c x86jit: Reduce code a bit in SETcc paths. 2023-08-25 00:00:35 -07:00
Henrik Rydgård
dfe187df1e Allow disabling HTTPS through the config file 
Simply set:

```ini
[General]
DisableHTTPS = True
```

Added to help debug issue #17969
 2023-08-24 21:28:30 +02:00
Henrik Rydgård
d2d8688e47 Add "Create frame dump" to the in-game developer menu (that can be enabled in dev settings) 
Makes it possible to create one without connecting the websocket
debugger, even on non-Windows platforms.
 2023-08-24 14:41:35 +02:00
Henrik Rydgård
fb84444043
Merge pull request #17965 from hrydgard/load-clut-old-framebuffers 
Add compat flag to not load CLUTs from old framebuffers
 2023-08-24 14:24:24 +02:00
Henrik Rydgård
0e56ed1f38 Android: Fix bug where autoconfigure for unknown pad types didn't do anything, instead of just doing the defaults. 2023-08-24 11:08:52 +02:00
Henrik Rydgård
16d073c4ad Add compat flag to not load CLUTs from old framebuffers 2023-08-24 10:30:37 +02:00
Henrik Rydgård
ca40de852a
Merge pull request #17960 from hrydgard/control-mapping-fixes 
Controls: Make the analog/digital mapping clash resolution more gentle.
 2023-08-24 09:52:40 +02:00
Henrik Rydgård
30016bc0d6
Merge pull request #17962 from hrydgard/toggle-wlan-switch 
Add mappable key to toggle networking
 2023-08-24 09:52:29 +02:00
Unknown W. Brackets
e2c6011906 x86jit: Implement VFPU Fcmp. 2023-08-23 22:17:55 -07:00
Unknown W. Brackets
00155790d6 x86jit: Add some notes for vector calls. 
Let's avoid the thunks to be more similar to other backends.
 2023-08-23 22:17:55 -07:00
Unknown W. Brackets
ef93b7547e x86jit: Add vmin/vmax. 2023-08-23 22:17:55 -07:00
Unknown W. Brackets
931c84f835 x86jit: Implement FCmp. 2023-08-23 22:17:55 -07:00
Unknown W. Brackets
d86f6ae618 x86jit: Implement set less thans. 2023-08-23 22:17:55 -07:00
Unknown W. Brackets
5473a5c698 x86jit: Add low MapWithFlags for Ext8to32. 2023-08-23 22:17:55 -07:00
Unknown W. Brackets
0b1953e5fd x86jit: Handle more Vec4 ops, some related. 2023-08-23 22:17:50 -07:00
Henrik Rydgård
feb0ea245e Add mappable key to toggle networking 
Fixes #17352

Requested in #17343
 2023-08-23 22:14:51 +02:00
Henrik Rydgård
797f88bf31 Fix ordering problem with screenshots that was causing crashes. 
Fixes #17781
 2023-08-23 19:03:33 +02:00
Henrik Rydgård
be2f81c3eb Controls: Make the analog/digital mapping clash resolution more gentle. 
Now takes the time into account, so clashing digital input will only shrink
analog inputs once it's a few seconds old.

Also fixes a bug where if there are both inputs, it was hard to reach
the limits because the digital input itself ended up getting shrunk.

This might help #17860
 2023-08-23 18:51:27 +02:00
Henrik Rydgård
a07079bdf9 Timestamp control inputs 2023-08-23 17:52:30 +02:00
Unknown W. Brackets
269a57a8b8 irjit: Fix vmin/vmax NAN handling. 
Oops, this needs to be signed.
 2023-08-23 06:50:42 -07:00
Henrik Rydgård
77355a1568
Merge pull request #17954 from unknownbrackets/x86-jit-ir 
x86jit: Fix Ext8to32/Ext16to32, some reg issues
 2023-08-23 08:50:02 +02:00
Unknown W. Brackets
efaf14a19f x86jit: Fix spilling zero register. 
We can't flush it, but it's likely not to get "clobbered".
 2023-08-22 23:29:13 -07:00
Unknown W. Brackets
c397e2e4da x86jit: Flush reg if dirty on map as ptr. 2023-08-22 23:29:13 -07:00
Unknown W. Brackets
a1bddd880d x86jit: Fix sign extension. 2023-08-22 23:29:13 -07:00
Unknown W. Brackets
74e5e43fdc jit: Skip known prefix writes. 
If we already know what's in memory and it's default, we can skip
overwriting with default values.  This is common, actually.
 2023-08-22 23:26:31 -07:00
Henrik Rydgård
6a3840d9b6 Implement bswap just because 2023-08-22 16:18:03 +02:00
Henrik Rydgård
7384d3d49f Debug mode buildfix 2023-08-22 16:15:07 +02:00
Henrik Rydgård
c5a076487e Disable extends on x86-32 2023-08-22 16:09:45 +02:00
Henrik Rydgård
b67741509c Implement a few ALU ops in the x86 JIT-from-IR. 2023-08-22 16:08:12 +02:00
Unknown W. Brackets
11c40e6889 x86: Implement a few basic float/vec4 ops. 2023-08-22 10:39:46 +02:00
Unknown W. Brackets
521b63dd2b x86jit: Implement FMul. 2023-08-22 10:39:46 +02:00
Unknown W. Brackets
edcb156897 x86jit: Add Vec4 and Float load/store. 2023-08-22 10:39:46 +02:00
Henrik Rydgård
951c35ba71
Merge pull request #17948 from unknownbrackets/x86-ir 
x86jit: Fix some issues in 32-bit
 2023-08-22 09:41:10 +02:00
Unknown W. Brackets
07fa1ed573 x86jit: Automatically flush incompatible regs. 2023-08-21 21:16:54 -07:00
Unknown W. Brackets
55654f52b2 x86jit: Fix Store8 on i386. 
Require an 8-bit capable register in mapping.
 2023-08-21 21:05:51 -07:00
Unknown W. Brackets
db34b85107 irjit: Allow flag-based allocation order. 
Sometimes backends have needs, like XMM0/v0-only, or similar.
 2023-08-21 20:46:05 -07:00
Unknown W. Brackets
bea74ba162 x86jit: Avoid negative offset warning. 2023-08-21 20:38:56 -07:00
ANR2ME
3c66523f04 A quick fix for Metal Gear Acid due to adhocctl's busy state never reset to false when there are no adhocctl's handler. 2023-08-22 04:29:07 +07:00
Unknown W. Brackets
1ccc2d5d2f x86jit: Fix address offsets with memview mask. 2023-08-21 09:03:10 -07:00
Unknown W. Brackets
40b3ff9573 x86jit: Fix spill issue. 2023-08-21 08:23:58 -07:00
Henrik Rydgård
1e269c1d3c
Merge pull request #17943 from unknownbrackets/x86-ir 
Add an x86/x64 backend for IR
 2023-08-21 09:21:37 +02:00
Unknown W. Brackets
538832940a x86jit: Implement some shifts. 2023-08-21 00:07:42 -07:00
Henrik Rydgård
61bf366d30
Merge pull request #17942 from unknownbrackets/irjit-clobber 
irjit: Fix regalloc clobber on exit
 2023-08-21 08:04:50 +02:00
Unknown W. Brackets
2b914046ff x86jit: Implement most exits. 2023-08-20 22:28:54 -07:00
Unknown W. Brackets
104b6d8c15 x86jit: Implement some basic arithmetic. 2023-08-20 22:28:54 -07:00
Unknown W. Brackets
5045cf012e x86jit: Fix flushing of zero register. 2023-08-20 22:28:54 -07:00
Unknown W. Brackets
08ea31f405 x86jit: Improve debug disasm. 2023-08-20 22:28:54 -07:00
Unknown W. Brackets
4e7f8cf213 x86jit: Implement load/store. 2023-08-20 22:28:54 -07:00
Unknown W. Brackets
a47b4424e5 x86jit: Fix some silly mistakes. 2023-08-20 22:28:54 -07:00
Unknown W. Brackets
4e3f3860f9 x86jit: Stub out op categories to files. 2023-08-20 22:28:54 -07:00
Unknown W. Brackets
622c69dbb9 x86jit: Expose option to select new IR based jit. 2023-08-20 22:28:54 -07:00
Unknown W. Brackets
c491f701ba x86jit: Add initial IR-based jit backend. 
It works, but pretty slow in some parts with everything stubbed.
 2023-08-20 22:28:54 -07:00
Unknown W. Brackets
81e24a9fee irjit: Fix regalloc clobber on exit. 2023-08-20 22:12:52 -07:00
Unknown W. Brackets
8dfc2f04d7 riscv: Use a single reg for LO/HI. 
This is the same optimization we have for arm64, basically.
 2023-08-20 14:49:09 -07:00
Henrik Rydgård
629d46ef5b
Merge pull request #17938 from unknownbrackets/riscv-centralize 
Centralize IR regcache from RISC-V
 2023-08-20 23:47:02 +02:00
Henrik Rydgård
6554b3eb75
Merge pull request #17939 from unknownbrackets/ir-vec-minor 
irjit: Implement vtfm 4x4 using dots
 2023-08-20 23:40:04 +02:00
Unknown W. Brackets
82fb41cba0 irjit: Implement vtfm 4x4 using dots. 2023-08-20 13:50:02 -07:00
Unknown W. Brackets
36b6aa4728 riscv: Allow GPR "SIMD" without FPR SIMD. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets
6a75e6712e riscv: Use automapping for special cases too. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets
a190793ad2 riscv: Simplify mapping for more instructions. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets
cc4bc406d5 riscv: Cleanup VfpuCtrlToReg meta, use auto-map. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets
e40ae60029 riscv: Mark normalized32 after mapping. 
It's less confusing to separate it.
 2023-08-20 12:42:11 -07:00
Unknown W. Brackets
f9bf7de701 riscv: Use a single reg cache. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets
e30fb82a64 riscv: Remove some unused reg funcs. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets
a23ade8f75 riscv: Map IR regs based on metadata. 
Only doing this in places without GPR/FPR mix or FPR/Vec overlap for now.
 2023-08-20 12:42:11 -07:00
Unknown W. Brackets
32d8f6196f irjit: Cut time flushing imm regs. 2023-08-20 08:59:47 -07:00
Unknown W. Brackets
552cd88938 irjit: Skip some work in PurgeTemps. 2023-08-20 08:59:47 -07:00
Unknown W. Brackets
57123e8f9e irjit: Reserve some arrays that churn. 
Improves IR compile time by around 20-30%.
 2023-08-20 08:59:47 -07:00
Henrik Rydgård
cd1c5beb60
Merge pull request #17934 from unknownbrackets/riscv-centralize 
RISC-V: Centralize IR regcaches
 2023-08-20 14:49:18 +02:00
Henrik Rydgård
efcd380842
Merge pull request #17935 from unknownbrackets/ir-long-inst 
irjit: Cleanup Write() calls with extra const
 2023-08-20 09:19:48 +02:00
Unknown W. Brackets
161465ab66 riscv: Centralize register FlushAll(). 2023-08-19 21:30:03 -07:00
Unknown W. Brackets
f3d4bd8c11 riscv: Centralize reg-as-pointer. 2023-08-19 21:24:36 -07:00
Unknown W. Brackets
bd1d93ae6f irjit: Cleanup Write() calls with extra const. 
Some instructions, such as Vec4Blend, are encoded requiring the const
field, and this interface was designed when we used a pool.
 2023-08-19 16:23:42 -07:00
Unknown W. Brackets
92f7374c89 riscv: Centralize reg mapping itself. 2023-08-19 16:15:49 -07:00
Unknown W. Brackets
83946eeef8 Core: Reduce log spam on exit. 
This doesn't need to be INFO.
 2023-08-19 16:15:49 -07:00
Unknown W. Brackets
718a1b3944 riscv: Centralize MarkDirty flagging. 2023-08-19 16:15:49 -07:00
Henrik Rydgård
88b3bdf857
Merge pull request #15840 from sum2012/Font-ltn12-hack 
Hack to Fix Earth Saver Plus font
 2023-08-18 15:41:46 +02:00
Henrik Rydgård
d8f8dcbc17
Merge pull request #17928 from hrydgard/unify-path-creation 
Unify memstick PSP/subdirectory creation
 2023-08-18 15:40:39 +02:00
Henrik Rydgård
94752ea7cf Android: On some newer devices with 32-bit userland, default to Vulkan. 
We already default to Vulkan on all recent 64-bit devices, but there are
some 32-bit devices that benefit, so let's set a high lower bound
for OS version.
 2023-08-18 15:13:58 +02:00
Henrik Rydgård
f3b2cb6fca Remove outdated hack for vsync parameter on Android. 2023-08-18 15:07:10 +02:00
Henrik Rydgård
5b76615463 Cleanup and more sensible defaults for current directory 2023-08-18 15:04:20 +02:00
Henrik Rydgård
7a4efb1a0a Call CreateSysDirectories on all platforms. 2023-08-18 14:03:38 +02:00
Henrik Rydgård
44d602ca7d Move InitSysDirectories to where it belongs and rename it. Plus warning fixes. 2023-08-18 13:03:32 +02:00
Henrik Rydgård
6f6ea4595a Windows: Split out Create... from InitSysDirectories, fixup uses 2023-08-18 12:46:40 +02:00
Unknown W. Brackets
4e41f83ecc riscv: Centralize IR reg cache metadata checks. 
These are all largely the same between backends.
 2023-08-17 23:03:31 -07:00
Unknown W. Brackets
ebab0e1591 riscv: Centralize reg allocation. 2023-08-17 18:50:33 -07:00
Henrik Rydgård
7f3f93a25b
Merge pull request #17919 from hrydgard/gamedatainstall_minor 
GamedataInstall: Add simple progress bar
 2023-08-18 00:57:50 +02:00
Henrik Rydgård
8a6e288fcc Add checkboxes in developer tools to allow disabling ubershaders. 
Might be helpful to diagnose performance problems on user devices.

Additionally, moves the texture replacement controls to the top. They
should probably be moved somewhere else entirely...

See #17918
 2023-08-17 20:16:04 +02:00
Henrik Rydgård
731d9b6d59
Merge branch 'master' into Font-ltn12-hack 2023-08-17 14:47:46 +02:00
Henrik Rydgård
1cf2a161a0 Replace the notifications with a bare-bones progress bar 2023-08-17 14:42:25 +02:00
sum2012
e00a41702c Add GamedataInstall of osm 
fix #14688
 2023-08-17 14:22:30 +02:00
Unknown W. Brackets
b30daa5760 riscv: Centralize state of regcaches. 2023-08-15 21:51:38 -07:00
Henrik Rydgård
ef2d7a810a Add comments, move some stuff around, get rid of some indentation. No functionality change. 2023-08-15 18:34:06 +02:00
Henrik Rydgård
b9b7342ffd
Merge pull request #17350 from basharast/master 
UWP Improvements
 2023-08-14 15:54:04 +02:00
Henrik Rydgård
d1b6aa7faa SoftGPU headless crashfix 2023-08-14 11:23:28 +02:00
Henrik Rydgård
1b2cffe632 Address feedback 2023-08-14 11:06:20 +02:00
Henrik Rydgård
aadb700505 Fix turning off VSync on Android, logic fix 2023-08-14 11:02:29 +02:00
Henrik Rydgård
ff6e118fff Get rid of a lot of ifdefs around presentation mode. Instead, set things dynamically. 2023-08-14 11:02:29 +02:00
Henrik Rydgård
bec9c5611e Rename PresentationMode to PresentMode 2023-08-14 11:02:29 +02:00
Henrik Rydgård
1beb01af6a
Merge pull request #17905 from unknownbrackets/irjit-opt 
irjit: Implement some missing, handle partial Vec4s more
 2023-08-14 07:49:45 +02:00
Henrik Rydgård
63b3b31feb
Merge pull request #17906 from unknownbrackets/riscv-blocklink 
riscv: Fix crash on clear icache
 2023-08-14 07:42:38 +02:00
Henrik Rydgård
a7bc70834c
Merge pull request #17907 from unknownbrackets/riscv-minor 
riscv: Implement vs2i
 2023-08-14 07:41:45 +02:00
Unknown W. Brackets
52cc38bf2a riscv: Implement vs2i. 2023-08-13 18:27:19 -07:00
Unknown W. Brackets
3f8f8d36d9 riscv: Fix crash on clear icache. 
Oops, can't avoid marking all blocks invalid.  Luckily a syscall should
always take more bytes than the bail invalidated block code.
 2023-08-13 18:25:46 -07:00
Unknown W. Brackets
159b41a0fa irjit: Fuse unaligned svl.q/svr.q together. 
They're almost never used outside paired, which we can do on most
platforms easily.
 2023-08-13 18:10:40 -07:00
Unknown W. Brackets
5729de90d2 irjit: Use more partial Vec4s / Vec4Blend. 2023-08-13 18:10:40 -07:00
Unknown W. Brackets
2e6dbab5fa irjit: Add flag to prefer Vec4, use for add/sub. 
This will improve things when using SIMD.
 2023-08-13 18:10:40 -07:00
Unknown W. Brackets
e0be6858b8 irjit: Implement vcrs.t. 
As used in Jeanne d'Arc.
 2023-08-13 18:10:12 -07:00
Unknown W. Brackets
217a1837ed irjit: Allow typical prefixes in vdiv/vasin/etc. 
Some of these behave strangely, but there are some common usages that work
fine.
 2023-08-13 18:10:07 -07:00
Bashar Astifan
07c119a80c Merge branch 'master' of https://github.com/hrydgard/ppsspp 2023-08-14 02:45:28 +04:00
Unknown W. Brackets
87668a5720
Merge pull request #17902 from hrydgard/ui-bugfixes 
Some debug overlays don't make sense when not in-game, disable them
 2023-08-13 13:13:16 -07:00
Henrik Rydgård
dc4de340b3 Some debug overlays don't make sense when not in-game, disable them. Minor feedback fixes. 2023-08-13 21:54:24 +02:00
Henrik Rydgård
5a9a2bf6fe
Merge pull request #17779 from EmulatorJS/master 
Cleanup emscripten libretro target
 2023-08-13 21:40:24 +02:00
Henrik Rydgård
2cdcc413b7
Merge pull request #17898 from unknownbrackets/irjit-vfputemps 
irjit: Cleanup/purge FPU/VFPU temps
 2023-08-13 21:08:00 +02:00
Henrik Rydgård
5dcd14b17a
Merge pull request #17901 from unknownbrackets/riscv-disasm 
riscv: Add debug log of block disasm
 2023-08-13 21:07:37 +02:00
Unknown W. Brackets
f03cd0b2ad
Merge pull request #17899 from unknownbrackets/riscv-minor 
Minor RISC-V cleanups, frame profiler fix
 2023-08-13 11:19:42 -07:00
Henrik Rydgård
d6cdb6e5d9
Merge pull request #17900 from unknownbrackets/irjit-vsgelt 
irjit: Implement vsge/vslt
 2023-08-13 19:59:14 +02:00
Unknown W. Brackets
23c79f8e7f irjit: Implement vsge/vslt. 
These are not ideal especially for SIMD, but they do work.
Improves performance in Silent Hill on RISC-V by like 20%.
 2023-08-13 10:40:47 -07:00
Unknown W. Brackets
5d20f2aabd irjit: Simplify VecDo3. 2023-08-13 10:40:47 -07:00
Unknown W. Brackets
2b36e0a625 irjit: ZeroFpCond -> FpCondFromReg. 
We already have a zero reg, so this is more useful and symmetrical.
 2023-08-13 10:40:47 -07:00
Unknown W. Brackets
2bb67db43c riscv: Switch to the logBlocks model for disasm. 2023-08-13 10:37:21 -07:00
Unknown W. Brackets
8c036a889d riscv: Add debug log of block disasm. 2023-08-13 10:32:04 -07:00
Unknown W. Brackets
7cc6c5fa62 riscv: Fix load error w/o pointerify. 2023-08-13 10:20:28 -07:00
Unknown W. Brackets
be938a850b riscv: Remove FMul safety check. 
Let's just see if everything's right, this bloats multiplies a lot.
Doesn't seem to impact perf a lot, though.
 2023-08-13 10:20:20 -07:00
Unknown W. Brackets
fa53b80574 irjit: Cleanup/purge FPU/VFPU temps. 
A lot of cases are followed by an FMov that just moved the temp to a
regular register, from VFPU instructions playing safe about overlaps.
 2023-08-13 10:14:10 -07:00
Henrik Rydgård
7bb1914fd3 Add FrameTiming.cpp/h (with no real contents) 2023-08-13 17:57:43 +02:00
Henrik Rydgård
2a74a0b98a
Merge pull request #17893 from unknownbrackets/riscv-blocklink 
riscv: Enable block linking
 2023-08-13 12:40:39 +02:00
Ethan O'Brien
8426b35a80 Cleanup emscripten libretro build target 2023-08-12 14:38:35 -05:00
Unknown W. Brackets
81f67c717c riscv: Fix block link for prev blocks. 
Oops, was just reversed so never linking.
 2023-08-12 10:48:39 -07:00
Unknown W. Brackets
fcc90095f7 riscv: Enable block linking. 2023-08-12 09:37:02 -07:00
Unknown W. Brackets
247788806a irjit: Add direct helper for start PC. 
It's annoying always fetching length too.
 2023-08-12 09:37:02 -07:00
Unknown W. Brackets
b3cdf06c5a riscv: Write fixup on block invalidation. 2023-08-12 09:37:02 -07:00
Unknown W. Brackets
3757ebca2d irjit: Invalidate/finalize target blocks. 
Doesn't actually do anything yet, but adds plumbing.
 2023-08-12 09:37:02 -07:00
Henrik Rydgård
1ea11c233c Remove "SwapBuffers" from the GraphicsContext interface. 
Buildfixes

More buildfix

headless buildfix

One more buildfix
 2023-08-11 01:57:02 +02:00
Henrik Rydgård
7c60022979 Fix hang after exiting a game. After running a game, coreState is POWERDOWN which counts as stepping. 2023-08-10 23:52:24 +02:00
Henrik Rydgård
779a156251 PortManager warning fix. The #pragma pack stuff was redundant anyway 2023-08-10 17:15:57 +02:00
Henrik Rydgård
4b0ac494d0 Even more simplification 2023-08-10 17:15:57 +02:00
Henrik Rydgård
0477ba8c78 Core.cpp: Some slight simplifications 2023-08-10 17:15:56 +02:00
Henrik Rydgård
be708e3e02 Move KeepScreenAwake to platform specific code. 2023-08-10 16:12:12 +02:00
Henrik Rydgård
50ea506b6a Revert "Regression experiment: Temporarily revert to returning 0 from bad achievement memory accesses." 
This reverts commit a044d8ccc2.
 2023-08-09 16:16:39 +02:00
Henrik Rydgård
2342c4522c
Merge pull request #17875 from unknownbrackets/riscv-jit 
RISC-V: Implement a few more ops
 2023-08-09 09:30:15 +02:00
Henrik Rydgård
bac4e8d42d
Merge pull request #17874 from unknownbrackets/irjit-exits 
IR: Simplify exits to ExitToConst when viable
 2023-08-09 09:11:52 +02:00
Henrik Rydgård
6758675054
Merge pull request #17873 from unknownbrackets/irjit-shuffle 
IR: Fix vqmul / Vec4Shuffle overlap
 2023-08-09 09:10:03 +02:00
Unknown W. Brackets
2c13b6d973 riscv: Implement vc2i. 2023-08-08 23:17:32 -07:00
Unknown W. Brackets
28c58c1d24 irjit: Allow more forms of vmidt. 
Mildly worth it.
 2023-08-08 23:17:32 -07:00
Unknown W. Brackets
4b9011e475 riscv: Reduce call bloat using temps. 2023-08-08 23:17:32 -07:00
Unknown W. Brackets
ddf3d02a3c riscv: Implement vi2uc. 2023-08-08 23:17:32 -07:00
Unknown W. Brackets
268adf1aa1 riscv: Implement scaled float/int convert. 2023-08-08 23:17:32 -07:00
Unknown W. Brackets
0b4e7d60f9 riscv: Implement ReverseBits in jit. 2023-08-08 23:17:32 -07:00
Unknown W. Brackets
ad4cbbab8e riscv: Don't cache mipState on backend. 
Bad sign if we're trying to use it, anyway.
 2023-08-08 23:17:32 -07:00
Unknown W. Brackets
31ff23746c irjit: Prefer ExitToConst over ExitToReg. 2023-08-08 23:14:01 -07:00
Unknown W. Brackets
3f97545f99 irjit: Reduce exits from constants. 
This reduces bloat a bit, and may help with common funcs that enter short
loops.
 2023-08-08 23:05:14 -07:00
Unknown W. Brackets
5f9a8fd1a1 irjit: Rename IRRegCache to IRImmRegCache. 
For clarity, since it's not a native regcache.
 2023-08-08 23:05:14 -07:00
Unknown W. Brackets
1a92027810 riscv: Make Vec4Shuffle overlap safe. 2023-08-08 23:00:45 -07:00
Unknown W. Brackets
e73c203984 irjit: Fix Vec4Shuffle overlap issue. 2023-08-08 23:00:39 -07:00
Henrik Rydgård
ac269aaa4b rcheevos: revert to before #17806 
PR #17806 upgraded rcheevos, after which a regression is reported in
issue #17631.

Experimentally revert to confirm.
 2023-08-08 15:38:22 +02:00
Henrik Rydgård
a044d8ccc2 Regression experiment: Temporarily revert to returning 0 from bad achievement memory accesses. 2023-08-08 15:33:46 +02:00
Henrik Rydgård
5ee04ce403 SDL: Break out event processing from main loop 
Makes things a bit easier to work with.
 2023-08-08 12:28:42 +02:00
Henrik Rydgård
bcae36d8cb Merge NativeUpdate and NativeRender, we always call them together. 2023-08-07 22:50:57 +02:00
Henrik Rydgård
096c168dd7
Add yield() function to tell the CPU that we're busy-waiting (rare) (#17862) 
* Add yield() function to tell the CPU that we're busy-waiting (rare)

Use it only for the busy-wait in lag sync, which only happens in
Windows.

* Buildfix attempt
 2023-08-07 21:38:03 +02:00
Henrik Rydgård
e9431d0d1e
Merge pull request #17859 from unknownbrackets/irjit-vec4 
irjit: Use Vec4 a bit more
 2023-08-06 23:05:33 +02:00
Unknown W. Brackets
3dc71cff75 irjit: Keep a couple more ops in Vec4. 2023-08-06 13:46:24 -07:00
Unknown W. Brackets
6a1dbd4cde irjit: Allow Vec4 to be used with masks. 2023-08-06 13:46:24 -07:00
Unknown W. Brackets
2b964fd3b0 irjit: Handle more common Vec4 prefix cases. 2023-08-06 13:38:00 -07:00